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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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NASA NTRS1997

Logic Design Pathology and Space Flight Electronics

Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.

Katz, Richard↗

NASA NTRS1972

Development of a satellite microwave radiometer to sense the surface temperature of the world oceans

A proposed S-band radiometer for determining the ocean surface temperature with an absolute accuracy of + or - 1 Kelvin and a resolution of + or - .1 Kelvin was placed under the Advanced Applications Flight Experiment for further development into Nimbus readiness state. The results of assessing the following are described: effects due to the state of the sea surface, effects caused by the intervening atmosphere, and effects associated with imperfections in the instrument itself. An extensive sea truth program is also described for correlation of aircraft test flight measurements or of satellite remote measurement to in-situ data. An improved radiometer design is a modified Dicke-switch type with temperature stabilized, microwave integrated circuit, front-end and with a pulsed injection-noise nulling system. The radiometer has a multimode rectangular horn antenna with very low ohmic losses and a beam efficiency of 98% or better.

Hidy, G. M.↗

NASA NTRS1976

DIP extractor simplifies circuit removal

Easily constructed tool can be used to pull dual in-line packaged integrated circuits off printed-wiring boards without damaging pins. Extractor can be designed for most popular IC configurations and sizes.

Nies, T.↗

NASA NTRS1979

CMOS circuit-fabrication handbook

Report describes complementary metal-oxide-semiconductor (CMOS) process used to fabricate integrated circuits at Marshall Space Flight Center. It also presents general discussions of circuit design, mask making packaging, and testing.

Bouldin, D. L.↗

NASA NTRS1983

Standard Transistor Arrays

Standard Transistor Array (STAR) design system is semicustom approach to generating random-logic integrated MOS digital circuits. Primary program in STAR system is CAPSTAR, STAR Cell Arrangement Program. CAPSTAR is augmented by automatic routining program, Display program and library of logic cells.

Cox, G. W.↗

NASA NTRS1986

Advanced detectors and signal processing

Continued progress is reported toward development of a silicon on garnet technology which would allow fabrication of advanced detection and signal processing circuits on bubble memories. The first integrated detectors and propagation patterns have been designed and incorporated on a new mask set. In addition, annealing studies on spacer layers are performed. Based on those studies, a new double layer spacer is proposed which should reduce contamination of the silicon originating in the substrate. Finally, the magnetic sensitivity of uncontaminated detectors from the last lot of wafers is measured. The measured sensitivity is lower than anticipated but still higher than present magnetoresistive detectors.

Greve, D. W.↗

NASA NTRS1988

Representation and matching of knowledge to design digital systems

A knowledge-based expert system is described that provides an approach to solve a problem requiring an expert with considerable domain expertise and facts about available digital hardware building blocks. To design digital hardware systems from their high level VHDL (Very High Speed Integrated Circuit Hardware Description Language) representation to their finished form, a special data representation is required. This data representation as well as the functioning of the overall system is described.

Jones, J. U.↗

NASA NTRS1991

A demonstration of CMOS VLSI circuit prototyping in support of the site facility using the 1.2 micron standard cell library developed by National Security Agency

Two silicon CMOS application specific integrated circuits (ASICs), a data generation chip, and a data checker chip were designed. The conversion of the data generator circuitry into a pair of CMOS ASIC chips using the 1.2 micron standard cell library is documented. The logic design of the data checker is discussed. The functions of the control circuitry is described. An accurate estimate of timing relationships is essential to make sure that the logic design performs correctly under practical conditions. Timing and delay information are examined.

Smith, Edwyn D.↗

NASA NTRS1994

Packaging Of Control Circuits In A Robot Arm

Packaging system houses and connects control circuitry mounted on circuit boards within shoulder, upper section, and lower section of seven-degree-of-freedom robot arm. Has modular design that incorporates surface-mount technology, multilayer circuit boards, large-scale integrated circuits, and multi-layer flat cables between sections for compactness. Three sections of robot arm contain circuit modules in form of stardardized circuit boards. Each module contains two printed-circuit cards, one of each face.

Kast, William↗

NASA NTRS1990

Optimal digital control of a Stirling cycle cooler

This short paper describes work in progress on the conceptual design of a control system for a cryogenic cooler intended for use aboard spacecraft. The cooler will produce 5 watts of cooling at 65 K and will be used to support experiments associated with the following: earth observation; atmospheric measurements; infrared, x-ray, and gamma-ray astronomy; and magnetic field characterization. The cooler has been designed and constructed for NASA/GSFC by Philips Laboratories and is described in detail. The cooler has a number of unique design features intended to enhance long life and maintenance free operation in space including use of the high efficiency Stirling thermodynamic refrigeration cycle, linear magnetic motors, clearance-seals, and magnetic bearings. The proposed control system design is based on optimal control theory and is targeted for custom integrated circuit implementation. The resulting control system will meet the following mission requirements: efficiency, reliability, optimal thermodynamic, electrical, and mechanical performance; freedom from operator intervention; light weight; and small size.

Feeley, J.↗

NASA NTRS1995

Simulation of 100-300 GHz solid-state harmonic sources

Accurate and efficient simulations of the large-signal time-dependent characteristics of second-harmonic Transferred Electron Oscillators (TEO's) and Heterostructure Barrier Varactor (HBV) frequency triplers have been obtained. This is accomplished by using a novel and efficient harmonic-balance circuit analysis technique which facilitates the integration of physics-based hydrodynamic device simulators. The integrated hydrodynamic device/harmonic-balance circuit simulators allow TEO and HBV circuits to be co-designed from both a device and a circuit point of view. Comparisons have been made with published experimental data for both TEO's and HBV's. For TEO's, excellent correlation has been obtained at 140 GHz and 188 GHz in second-harmonic operation. Excellent correlation has also been obtained for HBV frequency triplers operating near 200 GHz. For HBV's, both a lumped quasi-static equivalent circuit model and the hydrodynamic device simulator have been linked to the harmonic-balance circuit simulator. This comparison illustrates the importance of representing active devices with physics-based numerical device models rather than analytical device models.

NONLINEAR CIRCUITS↗

NASA NTRS2013

Fast, High-Precision Readout Circuit for Detector Arrays

The GEO-CAPE mission described in NASA's Earth Science and Applications Decadal Survey requires high spatial, temporal, and spectral resolution measurements to monitor and characterize the rapidly changing chemistry of the troposphere over North and South Americas. High-frame-rate focal plane arrays (FPAs) with many pixels are needed to enable such measurements. A high-throughput digital detector readout integrated circuit (ROIC) that meets the GEO-CAPE FPA needs has been developed, fabricated, and tested. The ROIC is based on an innovative charge integrating, fast, high-precision analog-to-digital circuit that is built into each pixel. The 128×128-pixel ROIC digitizes all 16,384 pixels simultaneously at frame rates up to 16 kHz to provide a completely digital output on a single integrated circuit at an unprecedented rate of 262 million pixels per second. The approach eliminates the need for off focal plane electronics, greatly reducing volume, mass, and power compared to conventional FPA implementations. A focal plane based on this ROIC will require less than 2 W of power on a 1×1-cm integrated circuit. The ROIC is fabricated of silicon using CMOS technology. It is designed to be indium bump bonded to a variety of detector materials including silicon PIN diodes, indium antimonide (InSb), indium gallium arsenide (In- GaAs), and mercury cadmium telluride (HgCdTe) detector arrays to provide coverage over a broad spectral range in the infrared, visible, and ultraviolet spectral ranges.

Rider, David M.↗

NASA NTRS1998

Assembly and Integration of Superconductive Measurement Circuits for a Spaceflight Experiment

Hybrid microelectronics containing both conventional electronic components and high-temperature superconductive films have been designed, fabricated, and tested. The devices operate from room temperature to 75K and perform d.c. four-probe resistance measurements on six superconductive specimens resident on each circuit. Four of these hybrid circuits were incorporated into the Materials In Devices As Superconductors (MIDAS) spaceflight experiment and evaluated over a 90-day period on the Mir space station. Prior to launch, comprehensive testing of the flight circuits was performed to determine the effects of thermal cycling, vibration loads, and long-term operation on circuit performance. This report describes the fabrication and assembly procedures used to produce the hybrid circuits, the techniques used to integrate the circuits into the MIDAS hardware system, and the results of pre-flight evaluations which verified circuit functionality.

Wise, Stephanie A.↗

NASA NTRS1997

Ultra Small Aperture Terminal for Ka-Band SATCOM

An ultra small aperture terminal (USAT) at Ka-band frequency has been developed by Lewis Research Center (LeRC) for data rates up to 1.5 Mbps in the transmit mode and 40 Mbps in receive mode. The terminal consists of a 35 cm diameter offset-fed parabolic antenna which is attached to a solid state power amplifier and low noise amplifier. A single down converter is used to convert the Ka-band frequency to 70 MHz intermediate frequency (IF). A variable rate (9.6 Kbps to 10 Mbps) commercial modem with a standard RS-449/RS-232 interface is used to provide point-to-point digital services. The terminal has been demonstrated numerous times using the Advanced Communications Technology Satellite (ACTS) and the 4.5 in Link Evaluation Terminal (LET) in Cleveland. A conceptual design for an advanced terminal has also been developed. This advanced USAT utilizes Microwave Monolithic Integrated Circuit (MMIC) and flat plate array technologies. This terminal will be self contained in a single package which will include a 1 watt solid state amplifier (SSPA), low noise amplifier (LNA) and a modem card located behind the aperture of the array. The advanced USAT will be light weight, transportable, low cost and easy to point to the satellite. This paper will introduce designs for the reflector based and array based USAT's.

Acosta, Roberto↗

NASA NTRS2005

A Ka-Band Wide-Bandgap Solid-State Power Amplifier: Architecture Performance Estimates

Motivated by recent advances in wide-bandgap (WBG) gallium nitride (GaN) semiconductor technology, there is considerable interest in developing efficient solidstate power amplifiers (SSPAs) as an alternative to the traveling-wave tube amplifier (TWTA) for space applications. This article documents the results of a study to investigate power-combining technology and SSPA architectures that can enable a 120-W, 40 percent power-added efficiency (PAE) SSPA. Results of the study indicate that architectures based on at least three power combiner designs are likely to enable the target SSPA. The proposed architectures can power combine 16 to 32 individual monolithic microwave integrated circuits (MMICs) with >80 percent combining efficiency. This corresponds to MMIC requirements of 5- to 10-W output power and >48 percent PAE. For the three proposed architectures [1], detailed analysis and design of the power combiner are presented. The first architecture studied is based on a 16-way septum combiner that offers low loss and high isolation over the design band of 31 to 36 GHz. Analysis of a 2-way prototype septum combiner had an input match >25 dB, output match >30 dB, insertion loss <0.02 dB, and isolation >30 dB over the design band. A 16-way design, based on cascading this combiner in a binary fashion, is documented. The second architecture is based on a 24-way waveguide radial combiner. A prototype 24-way radial base was analyzed to have an input match >30 dB (under equal excitation of all input ports). The match of the mode transducer that forms the output of a radial combiner was found to be >27 dB. The functional bandwidth of the radial base and mode transducer, which together will form a radial combiner/divider, exceeded the design band. The third architecture employs a 32-way, parallel-plate radial combiner. Simulation results indicated an input match >24 dB, output match >22 dB, insertion loss <0.23 dB, and adjacent port isolation >20 dB over the design band. All three architectures utilize a low-loss MMIC amplifier module based on commercial MMIC packaging and a custom microstrip-to-rectangular-waveguide transition. The insertion loss of the module is expected to be 0.45 dB over the design band.

Epp, L.↗

NASA NTRS2013

Remote Memory Access Protocol Target Node Intellectual Property

The MagnetoSpheric Multiscale (MMS) mission had a requirement to use the Remote Memory Access Protocol (RMAP) over its SpaceWire network. At the time, no known intellectual property (IP) cores were available for purchase. Additionally, MMS preferred to implement the RMAP functionality with control over the low-level details of the design. For example, not all the RMAP standard functionality was needed, and it was desired to implement only the portions of the RMAP protocol that were needed. RMAP functionality had been previously implemented in commercial off-the-shelf (COTS) products, but the IP core was not available for purchase. The RMAP Target IP core is a VHDL (VHSIC Hardware Description Language description of a digital logic design suitable for implementation in an FPGA (field-programmable gate array) or ASIC (application-specific integrated circuit) that parses SpaceWire packets that conform to the RMAP standard. The RMAP packet protocol allows a network host to access and control a target device using address mapping. This capability allows SpaceWire devices to be managed in a standardized way that simplifies the hardware design of the device, as well as the development of the software that controls the device. The RMAP Target IP core has some features that are unique and not specified in the RMAP standard. One such feature is the ability to automatically abort transactions if the back-end logic does not respond to read/write requests within a predefined time. When a request times out, the RMAP Target IP core automatically retracts the request and returns a command response with an appropriate status in the response packet s header. Another such feature is the ability to control the SpaceWire node or router using RMAP transactions in the extended address range. This allows the SpaceWire network host to manage the SpaceWire network elements using RMAP packets, which reduces the number of protocols that the network host needs to support.

Haddad, Omar↗

NASA NTRS1990

Support system for a 1750A VHSIC multiprocessor

A design approach for a support system or test station necessary to functionally operate a very high-speed integrated circuit (VHSIC) microprocessor brassboard is presented. Major subsystems which make up the support are the following: (1) power supply unit; (2) temperature controller unit; (3) input/output module; and (4) mechanical test fixture. Theoretical analyses and experimental techniques were utilized to design and implement the power and temperature requirements for the VHSIC processor. A functional description of the input/output module and test fixture is discussed. The support system provides the means to evaluate and functionally test a VHSIC microprocessor.

Ruggles, Stephen L.↗

NASA NTRSDate not supplied

A 96% Alumina based Packaging System for 500°C Test of SiC Integrated Circuits

With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire -bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500°C are reviewed.

High Temperature, Packaging, Alumina, Thick Film↗