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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 379 records · Page 21
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

The Regenerative Current Mirror: A Very Low Power Front-End Amplifier for Silicon Pixel Detectors

In pixelized detectors, reducing power consumption in the front- end ASIC chips becomes a crucial demand. Optimization based on mature pre-amplifier schemes today is unlikely to bring sufficient improvements. A new CMOS front-end gain stage topology with very low power consumption called regenerative current mirror is developed to fulfill the demand. The circuit takes advantage of high-speed performance of current amplification while operating with relatively low bias current. The regenerative current mirror uses a NMOS current mirror and a PMOS current mirror, both with nominal gain of 1, to form a loop-back topology that provides a positive feedback. An NMOS FET with an external adjustable voltage applied to it gate terminal is used to limit open loop gain of the current mirrors to be slightly lower than 1. This yields a net gain of the positive feedback loop to be much larger than 1 while operating the current mirrors under relatively low bias currents. Simulation shows that in 65 nm fabrication process, the power consumption of the gain stages suitable for silicon pixel detectors can be controlled < 10 micro-Watts per channel. Another novel low-power circuit called Pseudo-Thyristor presented in another document will replace traditional discriminator and the Regenerative Current Mirror plus Pseudo- Thyristor will provide a full solution for the silicon pixel low-power frontend ASIC.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

Switch leakage mitigation through differential cancellation

High speed analog-to-digital converters (ADC), switched-capacitor delay elements, and pulsed radio frequency (RF) systems all require switches in the signal path operating at high switching speeds, providing low resistance when enabled, and providing high signal isolation when disabled. In semiconductor technologies such as CMOS, the enabled state resistance directly scales with the sizing of the switch device, where a larger width switch provides a lower enabled state resistance. As the device width is increased, so is the capacitance formed between the gate, drain, and source of the device.

42 ENGINEERING↗
DOE OSTI2023

CMS High Granularity Calorimeter ECON-D ASIC overview and radiation testing results

The Compact Muon Solenoid (CMS) Experiment’s High Granularity Calorimeter (HGCAL) upgrade replaces the CMS electromagnetic and hadronic endcap calorimeters in preparation for the high-rate and high-radiation environment of the High Luminosity LHC. To effectively use the over 6 million channels of this highly-segmented “imaging” calorimeter, CMS is pioneering very front-end data compression with the Endcap Concentrator (ECON) ASICs – the ECON-T for the trigger path and the ECON-D for the data path. These 65 nm CMOS ASICs are radiation tolerant (200 Mrad) and low-power (< 2.5 mW/channel). In June 2023, we received the first full-functionality prototype of the data path concentrator ASIC, the ECON-D-P1. This talk will present an overview of the ECON-D-P1, summarize functionality and system testing, and present results from both Total Ionizing Dose (TID) and Single Event Effect (SEE) testing campaigns completed in summer 2023, validating the ECON-D radiation tolerant performance.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

Development of quantum dot materials for infrared cameras (Final CRADA Report)

The aim of this project was to develop scalable methods to produce infrared (IR) mercury telluride (HgTe) colloidal quantum dot (CQD) thin films and demonstrate their utility in a proof-of-concept monolithic SWIR focal plane array (FPA). These objectives were accomplished by scaling up the HgTe CQD synthesis, characterizing physical and electrical properties of HgTe CQDs, evaluating solution-processed coating methods for quality and efficiency, and developing a process flow to integrate HgTe CQDs with commercial-off-the-shelf silicon CMOS readout circuits by solution-processed coating to produce monolithic FPAs. The FPA is the image sensor in an infrared imaging system responsible for detecting and processing reflected or emitted light into an infrared image of the scene under observation. The quality of the image is determined by the sensitivity and resolution of the image sensor in the system. Higher resolution IR FPAs enable higher throughput in manufacturing quality assurance, wider field of view for autonomous navigation, and longer range surveillance for defense.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2024

Smart pixel sensors Towards on-sensor filtering of pixel clusters with deep learning

High granularity silicon pixel sensors are at the heart of energy frontier particle physics collider experiments. At an collision rate of 40\,MHz, these detectors create massive amounts of data. Signal processing that handles data incoming at those rate and intelligently reduces the data within the pixelated region of the detector \textit{at rate} will enhance physics performance and enable physics analyses that are not currently possible. Using the shape of charge clusters deposited in an array of small pixels, the physical properties of the traversing particle can be extracted with locally customized neural networks. In this first work, we present a neural network that can be embedded into the on-sensor readout and filter out hits from low momentum tracks, reducing the detector's data volume by 54.4-75.4\%. The network is designed and simulated as a custom readout integrated circuit with 28\,nm CMOS technology and is expected to operate at less than 300\,$\mu W$ with an area of less than 0.2\,mm$^2$.

43 PARTICLE ACCELERATORS↗
DOE OSTI2024

CryoPDK Development for 22nm FDSOI CryoCMOS

Cryogenic Process Design Kits (PDKs) are an indispensable tool in the design of complex integrated circuits across a wide spectrum of applications, from noble element detectors to Quantum Information Science, Superconducting Nanowire Single Photon Detectors (SNSPDs), and precision atomic clocks. The development of PDK-compatible SPICE models is a complex endeavor requiring test structures, measurements, model extraction and fitting. We will present the cryogenic modeling and development of a cryo-PDK for a 22nm FDSOI CMOS process for operation at 3.8 Kelvin.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.

Parpillon, Benjamin↗
DOE OSTI2024

Radiation-Hard Smart-Pixel Detector ASIC ReadOut with Digital AI in 28nm

Detectors at future high energy colliders will face enormous technical challenges. Disentangling the unprecedented numbers of particles expected in each event will require highly granular silicon pixel detectors with billions of readout channels. With event rates as high as 40 MHz, these detectors will generate petabytes of data per second. To enable discovery within strict bandwidth and latency constraints, future trackers must be capable of fast, power efficient, and radiation hard data-reduction at the source. This effort is pursuing the co-design development of high-performance readout smart pixel ASICs for a future Phase III High Luminosity upgrade of the Large Hadron Collider. A 1.6mm2 ASIC prototype was designed by Fermilab in CMOS 28 nm bulk process and submitted for manufacturing in February 2024. It leverages the analog front-end pixel design of a previous prototype fabricated and tested in 2023, which achieved a simulated detection level of ~400e- with 30fF input capacitance. The ROIC consists of two matrices of 16×16 smart pixels, each 25×25 μm2 in size. Each smart pixel contains a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. There is digital space for the integration of our fully combinatorial AI that performs momentum classification at the bunch crossing rate. The total power consumption is ∼6μW per pixel, which corresponds to ~1mW/cm2. The ASIC incorporates programmable front-end charge injection circuitry to generate pixel cluster charges during characterization. The cluster profile will be generated to duplicate hit characteristics of various momentum (pT). We will present early results from chip testing.

Parpillon, Benjamin↗
DOE OSTI2024

Fabrication of a Point-Like Transmission Target for Reducing Computed Tomography Imaging Artifacts

In this study, we address the challenge of enhancing image quality and spatial resolution in computed tomography (CT) imaging by introducing simulation and fabrication of high aspect ratio, point-like transmission targets. Utilizing advanced electroplating techniques, traditionally employed in the fabrication of Through Substrate Via (TSV) interconnects for CMOS circuitry, we successfully embed copper targets within silicon substrates. This method allows us to create high-aspect-ratio features specifically designed for X-ray transmission targets, resulting in micro targets that exhibit a volume increase compared to conventional evaporated surface targets. Furthermore, we present simulation results of the X-ray spectrum generated by these targets, demonstrating their potential to significantly improve both image quality and spatial resolution in CT applications. Our findings suggest that leveraging advanced fabrication techniques can open new avenues for the development of enhanced imaging technologies in medical diagnostics and beyond.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

The ETROC2 as the Final Version for CMS Endcap Timing Layer (ETL) Upgrade

The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD (Low Gain Avalanche Diodes) silicon devices, read out by ETROCs for precision timing measurement with down to ~30 ps timing resolution per track. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. The front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile. The ETROC chip is implemented in a commercial 65nm CMOS process. Each channel consists of a preamplifier, a discriminator, a TDC used for TOA (Time Of Arrival) and TOT (Time Over Threshold) measurements, and a memory for data storage and readout. An in-pixel auto threshold calibration is included, along with a self-testing pattern generator. The TOT is used for time-walk correction of the TOA measurement. The detailed hit information (TOA and TOT) from each cell will be read out from a local circular buffer after each Level-1 Accept (about 1 MHz). In addition, a charge injection circuit is implemented to allow for testing and calibration. For more detailed monitoring of the signal pulses, waveform sampling circuits are included for one pixel. The clock distribution is based on a 16x16 H-tree design with a shielding structure to alleviate potential interference. The global peripheral circuits include a PLL, a phase shifter, an I2C slave controller, a fast control block, a global readout, and a data driver along with an efuse and temperature sensor. The ETROC builds event data frames for each L1A selected event and is also capable of providing L1 trigger information for user-defined delayed hits. The main design challenge is how to extract precision timing information from the small LGAD signals in the presence of high irradiation fluence, while keeping the power consumption and digital activity low. The ETL design goal for the time resolution of 50 ps per hit is required to achieve a 35 ps arrival time measurement for a MIP particle, which has its track registered in two ETL disk layers. The LGAD contribution is known to be about 30 ps, this means that the jitter from the ETROC has to be kept below 40 ps. The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL and now becomes the final version. The ETROC2 chips have been extensively tested. We will present here new testing results including the bump bonding yield improvement study, the time walk correction (TWC) generality study with one pixel TWC applying to all pixels, the final SEU testing using both heavy ion and proton beam, more beam test studies including different sensors, and readiness for the ETROC2 production for CMS ETL upgrade.

Liu, Tiehui [Fermilab] (ORCID:0009000765225605)↗
DOE OSTI2025

Improved Charge Sensing on a SiMOS Double Quantum Dot using a Cryogenic Skipper Readout ASIC (Quandarum)

Major outstanding questions in high-energy physics such as the nature of dark matter and the existence of interactions beyond the standard model require new measurement techniques which are extremely sensitive to minute electromagnetic fields. An array of entangled spin qubits is a promising system for building novel detectors due to its combination of sensitivity and controllability. CMOS-based electron spin qubits, which have demonstrated the operational requirements for fault-tolerant quantum computing [1], offer a particular opportunity due to their compatibility with classical electronics, which allows the leveraging of decades of development of low-noise cryogenic detectors for physics. In this work, we combine a SiMOS double-quantum dot device architecture with a state-of-the-art cryoelectronic readout circuit [2-3] aimed to demonstrate improved charge readout using a single-electron transistor (SET). We identify the design characteristics for an SET that facilitate the use of on-chip classical electronics as a low-power, high-bandwidth first amplification stage and explore opportunities for sensor-readout co-design to minimize noise. This is the first of a series of steps to demonstrate high-fidelity readout of a large array of spin qubit with enough sensitivity to probe processes of interest for the investigation of beyond-standard-model physics.

Quinn, Adam [Fermilab]↗
DOE OSTI2026

A New Route Toward Atomically Flat and Defect-Free Ge/SiGe Planar Heterostructures

Germanium-based planar heterostructures are emerging as versatile platforms for realizing quantum devices. In particular, planar Ge/SiGe quantum wells (QWs) host hole states with exceptionally high mobility and strong, electrically tunable spin–orbit interactions, enabling full electrical control of quantum information. A key requirement for these systems is the growth of microscopic, defect-free, atomically flat Ge QW heterostructures on relaxed or reverse-graded SiGe buffer layers, as well as on commercial Ge substrates. While several physical deposition techniques have demonstrated high-quality planar Ge/SiGe QWs, a major challenge remains: minimizing defect density typically requires high growth temperatures, which are incompatible with standard CMOS process flows. Here, we present a convenient low-temperature process for realizing high-quality planar SiGe/Ge heterostructures using a combination of thermal and electron-beam evaporation. We systematically map the effects of ex-situ and in-situ substrate preparation protocols, growth temperature, and post-deposition annealing conditions, and correlate these parameters with surface roughness and defect density. We find that in-situ oxide desorption conditions and post-annealing parameters have the most pronounced impact on improving surface quality. Under optimized conditions, we achieve atomically smooth surfaces with root-mean-square roughness σrms​ ≤ 10 Å and negligible defect density. Interestingly, thermally evaporated Ge layers exhibit oriented triangular crystallites that elongate upon post-annealing in the presence of high Ge vapor pressure. These results demonstrate that this simple, low-temperature deposition approach is a viable and effective route for achieving high-quality Ge QW heterostructures, with strong potential for scalable quantum computing and sensing applications.

Tripathi, Malvika [Fermilab] (ORCID:00000001989251↗
DOE OSTI2026

A New Route Toward Atomically Flat and Defect-Free Ge/SiGe Planar Heterostructures

Germanium-based planar heterostructures are emerging as versatile platforms for realizing quantum devices. In particular, planar Ge/SiGe quantum wells (QWs) host hole states with exceptionally high mobility and strong, electrically tunable spin–orbit interactions, enabling full electrical control of quantum information. A key requirement for these systems is the growth of microscopic, defect-free, atomically flat Ge QW heterostructures on relaxed or reverse-graded SiGe buffer layers, as well as on commercial Ge substrates. While several physical deposition techniques have demonstrated high-quality planar Ge/SiGe QWs, a major challenge remains: minimizing defect density typically requires high growth temperatures, which are incompatible with standard CMOS process flows. Here, we present a convenient low-temperature process for realizing high-quality planar SiGe/Ge heterostructures using a combination of thermal and electron-beam evaporation. We systematically map the effects of ex-situ and in-situ substrate preparation protocols, growth temperature, and post-deposition annealing conditions, and correlate these parameters with surface roughness and defect density. We find that in-situ oxide desorption conditions and post-annealing parameters have the most pronounced impact on improving surface quality. Under optimized conditions, we achieve atomically smooth surfaces with root-mean-square roughness σrms​ ≤ 10 Å and negligible defect density. Interestingly, thermally evaporated Ge layers exhibit oriented triangular crystallites that elongate upon post-annealing in the presence of high Ge vapor pressure. These results demonstrate that this simple, low-temperature deposition approach is a viable and effective route for achieving high-quality Ge QW heterostructures, with strong potential for scalable quantum computing and sensing applications.

Tripathi, Malvika [Fermilab] (ORCID:00000001989251↗
DOE OSTI2025

Using High-Performance Cameras for Advanced Plasma Diagnostics

We will present insights, challenges, and recent progress on using a multi-megapixel deep-depletion CCD camera for quantitative X-ray spectra in a single-hit exposure mode in order to optimize X-ray diffraction experiments. We will also present some applications of Sandia’s in-house developed hybrid CMOS (hCMOS) sensors, which can record up to four full frames of optical or X-ray images in sequences with only a few nanoseconds interframe timing in a single line-of-sight.

Geissel, Matthias [Sandia National Laboratories (S↗
DOE OSTI2020

RD53 analog front-end processors for the ATLAS and CMS experiments at the High-Luminosity LHC

This work discusses the design and the main results relevant to the characterization of analog front-end processors in view of their operation in the pixel detector readout chips of ATLAS and CMS at the High-Luminosity LHC. The front-end channels presented in this paper are part of RD53A, a large scale demonstrator designed in a 65 nm CMOS technology by the RD53 collaboration.The collaboration is now developing the full-sized readout chips for the actual experiments. Some details on the improvements implemented in the analog front-ends are provided in the paper.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗
DOE OSTI2021

Engineering Tunneling Selector to Achieve High Non-linearity for 1S1R Integration

Memristor devices have been extensively studied as one of the most promising technologies for next-generation non-volatile memory. However, for the memristor devices to have a real technological impact, they must be densely packed in a large crossbar array (CBA) exceeding Gigabytes in size. Devising a selector device that is CMOS compatible, 3D stackable, and has a high non-linearity (NL) and great endurance is a crucial enabling ingredient to reach this goal. Tunneling based selectors are very promising in these aspects, but the mediocre NL value limits their applications in large passive crossbar arrays. In this work, we demonstrated a trilayer tunneling selector based on the Ge/Pt/TaN 1+x /Ta 2 O 5 /TaN 1+x /Pd layers that could achieve a NL of 3 × 10 5 , which is the highest NL achieved using a tunnel selector so far. The record-high tunneling NL is partially attributed to the bottom electrode's ultra-smoothness (BE) induced by a Ge/Pt layer. We further demonstrated the feasibility of 1S1R (1-selector 1-resistor) integration by vertically integrating a Pd/Ta 2 O 5 /Ru based memristor on top of the proposed selector.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2025

Evaluation of fluxon synapse device based on superconducting loops for energy efficient neuromorphic computing

With Moore’s law nearing its end due to the physical scaling limitations of CMOS technology, alternative computing approaches have gained considerable attention as ways to improve computing performance. Here, we evaluate performance prospects of a new approach based on disordered superconducting loops with Josephson-junctions for energy efficient neuromorphic computing. Synaptic weights can be stored as internal trapped fluxon states of three superconducting loops connected with multiple Josephson-junctions (JJ) and modulated by input signals applied in the form of discrete fluxons (quantized flux) in a controlled manner. The stable trapped fluxon state directs the incoming flux through different pathways with the flow statistics representing different synaptic weights. We explore implementation of matrix–vector-multiplication (MVM) operations using arrays of these fluxon synapse devices. We investigate the energy efficiency of online-learning of MNIST dataset. Our results suggest that the fluxon synapse array can provide ~100× reduction in energy consumption compared to other state-of-the-art synaptic devices. This work presents a proof-of-concept that will pave the way for development of high-speed and highly energy efficient neuromorphic computing systems based on superconducting materials.

42 ENGINEERING↗