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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 379 records · Page 21
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Low-temperature processed beta-phase In 2 Se 3 ferroelectric semiconductor thin film transistors

As scaling becomes increasingly difficult, there is growing interest in vertical or three-dimensional stacking of transistors and especially memory. Ferroelectric semiconductor field effect transistors can be key enablers to improve energy efficiency and overall chip and memory performance. In this work, low-temperature processed, back-end-of-the-line compatible transistors were demonstrated by depositing a layered chalcogenide ferroelectric semiconductor, beta-phase In 2 Se 3 , at temperature as low as 400 °C. Top gate n-channel In 2 Se 3 thin film transistors were fabricated with field-effect mobility ∼1 cm 2 V −1 s −1 , and simple polarization switching based memory results are presented.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Characterizing and Modeling the Influence of Geometry on the Performance of Superconducting Nanowire Cryotrons

The scaling of superconducting nanowire detectors to larger arrays is often limited by room-temperature-readout cabling. Cryogenic integrated circuits constructed from nanowire cryotrons, or nanocryotrons, can address this limitation by performing signal processing on chip. In this study, we characterize key performance metrics of the nanocryotron to elucidate its potential as a logical element in cryogenic integrated circuits and develop an electro-thermal model to connect material parameters with device performance. We find that the performance of the nanocryotron depends on the device geometry, and trade-offs are associated with optimizing the gain, jitter, and energy dissipation. Here, we demonstrate that nanocryotrons fabricated on niobium nitride can achieve a grey zone less than 210 nA wide for a 5 ns long input pulse corresponding to a maximum achievable gain of 48 dB, an energy dissipation of less than 20 aJ per operation, and a jitter of less than 60 ps.

Superconductor↗
NASA NTRS2012

Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

Duong, Tuan A.↗
DOE OSTI2019

Negative Ion Drift Time Projection Chamber Development for High-Resolution Tracking

Gas Time Projection Chambers (TPCs) are used extensively in High Energy Physics. Modern micro-pattern gaseous detectors (MPGDs) have made it feasible to construct large-volume TPCs with high readout granularity, so that ionization can be imaged with spatial resolution of order 100 μm or better. A challenge with large TPCs is preserving the track geometry over large drift distances. The reduced diffusion offered by negative ion drift (NID) has long been considered a possible means to scaling up TPCs at reduced cost, but NID has up to now required toxic and often flammable multi-component gas mixtures. A number of recent breakthroughs in the field have, however, led to a resurgence of interest in NID gas TPCs: First, it was found that multiple charge carriers in NID can be utilized to measure the absolute position of primary ionization in the drift direction, yielding a powerful new handle on backgrounds, at zero additional cost. Second, work by one of the PIs has revealed SF6 gas to be a non-toxic, non-flammable, NID gas with suitable minority charge carriers present. Third, preliminary work by the PIs suggests that multiple MPGD technologies work well with SF6. This opens the door to a new generation of large, high-resolution, low-background, low-cost gas TPCs. In this work we will investigate MPGD charge multiplication and charge readout in NID TPCs with SF6 gas. The objectives are to quantify the improvement over electron drift TPCs, and to identify the optimal MPGD types, operational parameters, electronics, and vacuum technologies for future low-background experiments. We will measure low-level detector performance parameters such as gain, gain resolution, and spatial resolution, as well as the resulting higher-level performance parameters such nuclear recoil identification efficiency, gamma-ray background rejection, track angle resolution and recoil energy resolution. The proposed work also includes investigation of acrylic vacuum vessels and collaboration on dedicated charge readout chips, both required for next-generation NID MPGD TPCs. MGPD NID TPCs may prove transformative for applications which require both high readout granularity and large detector volumes, such as the reconstruction of nuclear recoils in the context of large-scale directional dark matter searches, measurements of coherent neutrino-nucleus scattering, and directional neutron detection. While the proposed work is focused on nuclear recoils, the lessons learned will be widely applicable to gas TPCs in HEP, and hence have broad impact.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
NASA NTRS1991

Single board system for fuzzy inference

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

Symon, James R.↗
NASA NTRS2006

Microfluidic Devices for Studying Biomolecular Interactions

Microfluidic devices for monitoring biomolecular interactions have been invented. These devices are basically highly miniaturized liquid-chromatography columns. They are intended to be prototypes of miniature analytical devices of the laboratory on a chip type that could be fabricated rapidly and inexpensively and that, because of their small sizes, would yield analytical results from very small amounts of expensive analytes (typically, proteins). Other advantages to be gained by this scaling down of liquid-chromatography columns may include increases in resolution and speed, decreases in the consumption of reagents, and the possibility of performing multiple simultaneous and highly integrated analyses by use of multiple devices of this type, each possibly containing multiple parallel analytical microchannels. The principle of operation is the same as that of a macroscopic liquid-chromatography column: The column is a channel packed with particles, upon which are immobilized molecules of the protein of interest (or one of the proteins of interest if there are more than one). Starting at a known time, a solution or suspension containing molecules of the protein or other substance of interest is pumped into the channel at its inlet. The liquid emerging from the outlet of the channel is monitored to detect the molecules of the dissolved or suspended substance(s). The time that it takes these molecules to flow from the inlet to the outlet is a measure of the degree of interaction between the immobilized and the dissolved or suspended molecules. Depending on the precise natures of the molecules, this measure can be used for diverse purposes: examples include screening for solution conditions that favor crystallization of proteins, screening for interactions between drugs and proteins, and determining the functions of biomolecules.

Wilson, Wilbur W.↗
NASA NTRS2019

Prototype Magnetic Calorimeter Arrays with Buried Wiring for the Lynx X-Ray Microcalorimeter

Metallic magnetic calorimeter (MMC) technology is a leading contender for detectors for the Lynx X-ray Microcalorimeter, which is an imaging spectrometer consisting of an array of greater than 100,000 pixels. The fabrication of such large arrays presents a challenge when attempting to route the superconducting wiring from the pixels to the multiplexed readout. If the wiring is designed to be planar, then an aggressive, submicron scale wiring pitch has to be employed, which is technically challenging to design and fabricate on account of the requirements of low inductance, low cross-talk, high critical currents and high yield. An alternative way to achieve large scale, high density wiring is through the use of multiple buried metal layers, planarized by Chemical Mechanical Planarization. This approach is well-suited for connecting thousands of pixels on a large focal plane to readout chips, and also for fabricating sensor meander coils with narrow line widths, which helps in increasing the sensor inductance and thus alleviates stray inductance issues associated with the wiring in large size arrays. In this work we describe the fabrication of high sensor inductance MMC arrays implementing Lynx concepts and incorporating multiple layers of buried Nb wiring. The detector array is composed of three sub-arrays with pixels optimized to meet the different science driven performance requirements of Lynx. In two of the sub-arrays we adopt a thermal multiplexing scheme to read out pixels by coupling 25 absorbers to a single sensor through thermal links of varied thermal conductance. We demonstrate the successful fabrication of multi-absorber MMCs with fine pitch pixels in very large size arrays.

Solid-State Physics↗
DOE OSTI2020

Notch insensitivity in fatigue failure of chopped carbon fiber chip-reinforced composites using experimental and computational analysis

This study focuses on the notch effect on the fatigue failure of chopped carbon fiber chip-reinforced sheet molding compound (SMC) composites by using both experimental and numerical methods. The S-N diagrams of notched specimens are first obtained experimentally, which exhibit large scatter and are shown to depend on the spatial distribution of local fiber orientations. After considering the effect of this spatial distribution by adopting a new fatigue damage parameter to normalize the results, we achieve a much better correlation in the normalized S-N diagram for all the notched specimens with different hole diameters. Next, compared with the fatigue results of smooth specimens without notches, we find that SMC composites under tension-tension fatigue loading exhibit notch-insensitivity, which renders this type of composites a better candidate in joints or similar applications. Meanwhile, the fatigue failure mechanisms of notched SMC composites are explored through a microstructure characterization procedure. On this basis, a computational micromechanics model considering the notch effect and an improved multi-scale progressive damage fatigue law, calibrated by coupon-level fatigue tests of smooth SMC composites under different loading conditions, are employed to predict the fatigue behavior of notched SMC composites. We show that detailed failure processes and fatigue life of notched SMC composites can be efficiently and adequately predicted by this computational framework.

36 MATERIALS SCIENCE↗
NASA NTRS2001

Lab-on-a-Chip Based Protein Crystallization

We are developing a novel technique with which we will grow protein crystals in very small volumes, utilizing chip-based, microfluidic ("LabChip") technology. This development, which is a collaborative effort between NASA's Marshall Space Flight Center and Caliper Technologies Corporation, promises a breakthrough in the field of protein crystal growth. Our initial results obtained from two model proteins, Lysozyme and Thaumatin, show that it is feasible to dispense and adequately mix protein and precipitant solutions on a nano-liter scale. The mixtures have shown crystal growth in volumes in the range of 10 nanoliters to 5 microliters. In addition, large diffraction quality crystals were obtained by this method. X-ray data from these crystals were shown to be of excellent quality. Our future efforts will include the further development of protein crystal growth with LabChip(trademark) technology for more complex systems. We will initially address the batch growth method, followed by the vapor diffusion method and the liquid-liquid diffusion method. The culmination of these chip developments is to lead to an on orbit protein crystallization facility on the International Space Station. Structural biologists will be invited to utilize the on orbit Iterative Biological Crystallization facility to grow high quality macromolecular crystals in microgravity.

vanderWoerd, Mark J.↗
NASA NTRS1994

From neural-based object recognition toward microelectronic eyes

Engineering neural network systems are best known for their abilities to adapt to the changing characteristics of the surrounding environment by adjusting system parameter values during the learning process. Rapid advances in analog current-mode design techniques have made possible the implementation of major neural network functions in custom VLSI chips. An electrically programmable analog synapse cell with large dynamic range can be realized in a compact silicon area. New designs of the synapse cells, neurons, and analog processor are presented. A synapse cell based on Gilbert multiplier structure can perform the linear multiplication for back-propagation networks. A double differential-pair synapse cell can perform the Gaussian function for radial-basis network. The synapse cells can be biased in the strong inversion region for high-speed operation or biased in the subthreshold region for low-power operation. The voltage gain of the sigmoid-function neurons is externally adjustable which greatly facilitates the search of optimal solutions in certain networks. Various building blocks can be intelligently connected to form useful industrial applications. Efficient data communication is a key system-level design issue for large-scale networks. We also present analog neural processors based on perceptron architecture and Hopfield network for communication applications. Biologically inspired neural networks have played an important role towards the creation of powerful intelligent machines. Accuracy, limitations, and prospects of analog current-mode design of the biologically inspired vision processing chips and cellular neural network chips are key design issues.

Sheu, Bing J.↗
NASA NTRS1976

The use of remote sensing imagery for environmental land use and flood hazard mapping

Flood hazard maps have been constructed for Graham, Yuma, and Yavapai Counties in Arizona using remote sensing techniques. Watershed maps of priority areas were selected on the basis of their interest to the county planning staff and represented areas of imminent or ongoing development and those known to be subject to inundation by storm runoff. Landsat color infrared imagery at scales of 1:1,000,000, 1:500,000, and 1:250,000 was used together with high-altitude aerial photography at scales of 1:120,000 and 1:60,000 to determine drainage patterns and erosional features, soil type, and the extent and type of ground cover. The satellite imagery was used in the form of 70 mm chips for enhancement in a color additive viewer and in all available enlargement modes. Field checking served as the main backup to the interpretations. Areas with high susceptibility to flooding were determined with a high level of confidence from the remotely sensed imagery.

Mouat, D. A.↗
NASA NTRS1999

Chandra Observations of the Young Cluster NGC 2516

The Chandra observatory was Launched July 23 1999. The first two months of the mission have been spent performing on-orbit calibration. This phase of the mission has included about 60 Ks of observing time on the young cluster NGC 2516. The observations have been made as part of the measurements of the boresight and the plate-scale of the various instruments. These observations will augment planned (deeper) GTO observation of this cluster. Here we present the results of these early observations. As of September 7, in a single ACIS 5'x5' field (one backside chip) examined 26 sources were detected in a single 10 Ks exposure. This represents less than one sixth of the total exposure time and less than one sixth of the total area to be observed during the calibration phase. we will compare the characteristics of those sources detected with Chandra with those detected by ROSAT. Since these observations are being made using all detectors, we will also compare observations among the various detectors.

Wolk, Scott J.↗
DOE OSTI2025

Designs for scalable construction of hybrid quantum photonic cavities

Nanophotonic resonators are central to numerous applications, from efficient spin–photon interfaces to laser oscillators and precision sensing. A leading approach consists of photonic crystal (PhC) cavities, which have been realized in a wide range of dielectric materials. However, translating proof-of-concept devices into a functional system entails a number of additional challenges, inspiring new approaches that combine resonators with wavelength-scale confinement and high quality factors; scalable integration with integrated circuits and photonic circuits; electrical or mechanical cavity tuning; and, in many cases, a need for heterogeneous integration with functional materials such as III–V semiconductors or diamond color centers for spin–photon interfaces. Here we introduce a concept that generates a finely tunable PhC cavity at a selected wavelength between two heterogeneous optical materials whose properties satisfy the above requirements. The cavity is formed by stamping a hard-to-process material with simple waveguide geometries on top of an easy-to-process material consisting of dielectric grating mirrors and active tuning capability. We simulate our concept for the particularly challenging design problem of multiplexed quantum repeaters based on arrays of cavity-coupled diamond color centers, achieving theoretically calculated unloaded quality factors of 106, mode volumes as small as 1.2(λ/neff)3, and maintaining >60% total on-chip collection efficiency of fluorescent photons. We further introduce a method of low-power piezoelectric tuning of these hybrid diamond cavities, simulating optical resonance shifts up to ∼760 GHz and color center fluorescence tuning of 5 GHz independent of cavity tuning. These results will motivate integrated photonic cavities toward larger scale systems-compatible designs.

Greenspon, Andrew S. (ORCID:0000000296317568)↗
DOE OSTI2021

Light-Front Field Theory on Current Quantum Computers

We present a quantum algorithm for simulation of quantum field theory in the light-front formulation and demonstrate how existing quantum devices can be used to study the structure of bound states in relativistic nuclear physics. Specifically, we apply the Variational Quantum Eigensolver algorithm to find the ground state of the light-front Hamiltonian obtained within the Basis Light-Front Quantization (BLFQ) framework. The BLFQ formulation of quantum field theory allows one to readily import techniques developed for digital quantum simulation of quantum chemistry. This provides a method that can be scaled up to simulation of full, relativistic quantum field theories in the quantum advantage regime. As an illustration, we calculate the mass, mass radius, decay constant, electromagnetic form factor, and charge radius of the pion on the IBM Vigo chip. This is the first time that the light-front approach to quantum field theory has been used to enable simulation of a real physical system on a quantum computer.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2019

A 4×4 electrooptic silicon photonic switch fabric with net neutral insertion loss

We present a strictly nonblocking 4×4 electrooptic silicon photonic switch fabric with on-chip gain. The switch integrates 12 Mach-Zehnder cells in a 3-stage topology equipped with fast electrooptic phase shifters, and thermooptic phase trimmers. To compensate for the losses of the fabric, a 4-channel GaInAsP/InP semiconductor optical amplifier array is flip-chip attached into an etched cavity in the silicon photonic chip with butt-coupled waveguide interfaces. The chip is wirebonded to a CMOS driver that provides push-pull drive to each elementary Mach-Zehnder cell. We demonstrate an optical switch assembly with net neutral insertion loss in the C-band together with nanosecond-scale reconfiguration time.

42 ENGINEERING↗
NASA NTRS1993

The Application of Microtechnology to Spacecraft On-Board Computing(abstract)

In this report, we will survey recent advances in chip packaging and stacking techniques that allow miniature computers to be developed for space applications. Several orders of magnitude reduction in mass, volume, and power consumption are possible using these techniques. Moreover, performance improvements can be achieved by increasing the scale of multiprocessing. Most importantly, long-term survivability can potentially be improved by increasing the level of redundancy and fault tolerance.

microtechnology computers multiprocessing packagin↗
NASA NTRS1979

Silicon Ingot Casting: Heat Exchanger Method. Multi-wire Slicing: Fixed Abrasine Slicing Technique, Phase 3

Ingot casting was scaled up to 16 cm by 16 cm square cross section size and ingots weighing up to 8.1 kg were cast. The high degree of crystallinity was maintained in the large ingot. For large sizes, the nonuniformity of heat treatment causes chipping of the surface of the ingot. Progress was made in the development of a uniform graded structure in the silica crucibles. The high speed slicer blade-head weight was reduced to 37 pounds, allowing surface speeds of up to 500 feet per minute. Slicing of 10 cm diameter workpieces at these speeds increased the through-put of the machine to 0.145 mm/min.

Schmid, F.↗
DOE OSTI2019

Balar: A SST GPU Component for Performance Modeling and Profiling

Programmable accelerators have become commonplace in modern computing systems. Advances in programming models and the availability of massive amounts of data have created a space for massively parallel accelerators capable of maintaining context for thousands of concurrent threads resident on-chip. These threads are grouped and interleaved on a cycle-by-cycle basis among several massively parallel computing cores. One path for the design of future supercomputers relies on an ability to model the performance of these massively parallel cores at scale. The SST framework has been proven to scale up to run simulations containing tens of thousands of nodes. A previous report described the initial integration of the open-source, execution-driven GPU simulator, GPGPU-Sim, into the SST framework. This report discusses the results of the integration and how to use the new GPU component in SST. It also provides examples of what it can be used to analyze and a correlation study showing how closely the execution matches that of a Nvidia V100 GPU when running kernels and mini-apps.

97 MATHEMATICS AND COMPUTING↗