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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 379 records · Page 21

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NASA NTRS1983

Array processor architecture

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

Barnes, George H.↗

NASA NTRS1976

Solar cell electrical connections

Study was conducted to find best methods of attaching pure silver and silver plated Kovar (trademark) interconnect ribbons to silicon solar cells with titanium-silver solderless contacts. Investigations include thermocompression bonding, parallel-gap welding, and ultrasonic welding.

Rauschenbach, H. S.↗

NASA NTRS1982

Digital system for structural dynamics simulation

State-of-the-art digital hardware and software for the simulation of complex structural dynamic interactions, such as those which occur in rotating structures (engine systems). System were incorporated in a designed to use an array of processors in which the computation for each physical subelement or functional subsystem would be assigned to a single specific processor in the simulator. These node processors are microprogrammed bit-slice microcomputers which function autonomously and can communicate with each other and a central control minicomputer over parallel digital lines. Inter-processor nearest neighbor communications busses pass the constants which represent physical constraints and boundary conditions. The node processors are connected to the six nearest neighbor node processors to simulate the actual physical interface of real substructures. Computer generated finite element mesh and force models can be developed with the aid of the central control minicomputer. The control computer also oversees the animation of a graphics display system, disk-based mass storage along with the individual processing elements.

Krauter, A. I.↗

NASA NTRS1990

Pressurized bellows flat contact heat exchanger interface

Disclosed is an interdigitated plate-type heat exchanger interface. The interface includes a modular interconnect to thermally connect a pair or pairs of plate-type heat exchangers to a second single or multiple plate-type heat exchanger. The modular interconnect comprises a series of parallel, plate-type heat exchangers arranged in pairs to form a slot therebetween. The plate-type heat exchangers of the second heat exchanger insert into the slots of the modular interconnect. Bellows are provided between the pairs of fins of the modular interconnect so that when the bellows are pressurized, they drive the plate-type heat exchangers of the modular interconnect toward one another, thus closing upon the second heat exchanger plates. Each end of the bellows has a part thereof a thin, membrane diaphragm which readily conforms to the contours of the heat exchanger plates of the modular interconnect when the bellows is pressurized. This ensures an even distribution of pressure on the heat exchangers of the modular interconnect thus creating substantially planar contact between the two heat exchangers. The effect of the interface of the present invention is to provide a dry connection between two heat exchangers whereby the rate of heat transfer can be varied by varying the pressure within the bellows.

Voss, Fred E.↗

NASA NTRS1966

Fluid logic control circuit operates nutator actuator motor

Fluid logic control circuit operates a pneumatic nutator actuator motor. It has no moving parts and consists of connected fluid interaction devices. The operation of this circuit demonstrates the ability of fluid interaction devices to operate in a complex combination of series and parallel logic sequence.

Source record↗

NASA NTRS1978

Effect of grazing flow on the acoustic impedance of Helmholtz resonators consisting of single and clustered orifices

A semiempirical fluid mechanical model is presented which predicts impedance of a Helmholtz resonator consisting of a single cavity-backed orifice as a function of grazing flow speed, boundary-layer thickness, incident sound amplitude and frequency, and resonator geometry. The incident and cavity sound fields are connected in terms of an orifice discharge coefficient. The effect of multiple orifices was studied experimentally. Interaction between orifices is important only for orifices aligned parallel to the grazing flow. Resistance was virtually independent of both orifice relative spacing and number. Reactance was found to be quite dependent upon orifice spacing but insensitive to the number of orifices.

Hersh, A. S.↗

NASA NTRS1988

DFT algorithms for bit-serial GaAs array processor architectures

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.

Mcmillan, Gary B.↗

NASA NTRS1990

A VLSI decomposition of the deBruijn graph

A new Viterbi decoder for convolutional codes with constraint lengths up to 15, called the Big Viterbi Decoder, is under development for the Deep Space Network. It will be demonstrated by decoding data from the Galileo spacecraft, which has a rate 1/4, constraint-length 15 convolutional encoder on board. Here, the mathematical theory underlying the design of the very-large-scale-integrated (VLSI) chips that are being used to build this decoder is explained. The deBruijn graph B sub n describes the topology of a fully parallel, rate 1/v, constraint length n+2 Viterbi decoder, and it is shown that B sub n can be built by appropriately wiring together (i.e., connecting together with extra edges) many isomorphic copies of a fixed graph called a B sub n building block. The efficiency of such a building block is defined as the fraction of the edges in B sub n that are present in the copies of the building block. It is shown, among other things, that for any alpha less than 1, there exists a graph G which is a B sub n building block of efficiency greater than alpha for all sufficiently large n. These results are illustrated by describing a special hierarchical family of deBruijn building blocks, which has led to the design of the gate-array chips being used in the Big Viterbi Decoder.

Collins, O.↗

NASA NTRS1990

Transition in high-speed free shear layers

The laminar free-shear layers considered in the study are formed by combinations of the velocities and momentum thicknesses of two adjacent parallel flows. Transition in wakes, pure free-shear layers of the Chapman type, and separate and partition flows are discussed. A stability-transition connection is emphasized, and it is suggested that a recurring deficiency in some stability calculations is the use of overly simplified laminar profiles. It is also noted that physical principles can be used for estimating the transition location or providing the factors affecting it. One such approach, a threshold theory, is discussed by way of example.

Demetriades, A.↗

NASA NTRS2003

P2P Technology for High-Performance Computing: An Overview

The transition from cluster computing to peer-to-peer (P2P) high-performance computing has recently attracted the attention of the computer science community. It has been recognized that existing local networks and dedicated clusters of headless workstations can serve as inexpensive yet powerful virtual supercomputers. It has also been recognized that the vast number of lower-end computers connected to the Internet stay idle for as long as 90% of the time. The growing speed of Internet connections and the high availability of free CPU time encourage exploration of the possibility to use the whole Internet rather than local clusters as massively parallel yet almost freely available P2P supercomputer. As a part of a larger project on P2P high-performance computing, it has been my goal to compile an overview of the 2P2 paradigm. I have studied various P2P platforms and I have compiled systematic brief descriptions of their most important characteristics. I have also experimented and obtained hands-on experience with selected P2P platforms focusing on those that seem promising with respect to P2P high-performance computing. I have also compiled relevant literature and web references. I have prepared a draft technical report and I have summarized my findings in a poster paper.

Follen, Gregory J.↗

NASA NTRS2011

Broadband Via-Less Microwave Crossover Using Microstrip-CPW Transitions

The front-to-back interface between microstrip and CPW (coplanar waveguide) typically requires complex fabrication or has high radiation loss. The microwave crossover typically requires a complex fabrication step. The prior art in microstrip-CPW transition requires a physical vias connection between the microstrip and CPW line on a separate layer. The via-less version of this transition was designed empirically and does not have a close form solution. The prior art of the micro wave crossover requires either additional substrate or wire bond as an air bridge to isolate two microwave lines at the crossing junction. The disadvantages are high radiation loss, no analytical solution to the problem, lengthy simulation time, and complex fabrication procedures to generate air bridges or via. The disadvantage of the prior crossover is a complex fabrication procedure, which also affects the device reliability and yield. This microstrip-CPW transition is visualized as two microstrip-slotline transitions combined in a way that the radiation from two slotlines cancels each other out. The invention is designed based on analytical methods; thus, it significantly reduces the development time. The crossover requires no extra layer to cross two microwave signals and has low radiation loss. The invention is simple to fabricate and design. It produces low radiation loss and can be designed with low insertion loss, with some tradeoff with signal isolation. The microstrip-CPW transition is used as an interface to connect between the device and the circuit outside the package. The via-less microwave crossover is used to allow two signals to cross without using an extra layer or fabrication processing step to enable this function. This design allows the solution to be determined entirely though analytical techniques. In addition, a planar via-less microwave crossover using this technique was proposed. The experimental results show that the proposed crossover at 5 GHz has a minimum isolation of 32 dB. It also has low in-band insertion loss and return loss of 1.2 dB and 18 dB, respectively, over more than 44 percent of bandwidth at room temperature. This microstrip-CPW transition requires the microstrip line to be split into two sections. Each section is connected to a microstrip quarter-wavelength openended stub. A slotline is also placed perpendicular to the microstrip section. The slot is connected to a grounded-end quarter-wavelength slotline and generates a microstrip-slotline transition. When two of these sections are placed in parallel and with the microstrip section combined at transition, a microstrip- CPW transition is formed. The slotline radiation is suppressed as two slots are excited with the electric field in an opposite direction, which cancels the radiation in far field. The invention on the crossover consists of the invented microstrip-CPW transitions combined back-to-back and a microstrip low-pass filter. One signal is crossed through to the microstrip layer, while the other signal is crossed through the CPW line located on the ground plane of the microstrip line. The microstrip low-pass filter produces a narrow line at the crossing point to enhance the system isolation. It also produces broadband response in the operating frequency band. The microstrip-CPW transition allows a microwave signal to travel from microstrip line to CPW line with low radiation loss. The crossover allows two microwave signals to cross with minimal parasitic coupling.

Stevenson, Thomas↗

NASA NTRS1999

Secondary Wing System for Use on an Aircraft

A secondary wing system for use on an aircraft augments the lift, stability, and control of the aircraft at subsonic speeds. The secondary wing system includes a mechanism that allows the canard to be retracted within the contour of the aircraft fuselage from an operational position to a stowed position. The top surface of the canard is exposed to air flow in the stowed position, and is contoured to integrate aerodynamically and smoothly within the contour of the fuselage when the canard is retracted for high speed flight. The bottom portion of the canard is substantially flat for rotation into a storage recess within the fuselage. The single canard rotates about a vertical axis at its spanwise midpoint. The canard can be positioned between a range of sweep angles during flight and a stowed position in which its span is substantially parallel to the aircraft fuselage. The canard can be deployed and retracted during flight. The deployment mechanism includes a circular mounting ring and drive mechanism that connects the canard with the fuselage and permits it to rotate and to change incidence. The deployment mechanism further includes retractable fairings which serve to streamline the wing when it is retracted into the top of the fuselage.

Smith, Brian E.↗

NASA NTRS2017

Long Duration Head Down Tilt Bed Rest and Spaceflight Effects on Neurocognitive Performance: Extent, Longevity and Neural Bases

We have recently completed a long duration head down tilt bed rest (HDBR) study in which we performed structural and functional magnetic resonance brain imaging to identify the relationships between changes in neurocognitive function and neural structural alterations in a spaceflight analog environment. We are also collecting the same measures in crewmembers prior to and following a six month International Space Station mission. We will present data demonstrating that bed rest resulted in functional mobility and balance deterioration with recovery post-HDBR. We observed numerous changes in brain structure, function, and connectivity relative to a control group which were associated with pre to post bed rest changes in sensorimotor function. For example, gray matter volume (GMv) increased in posterior parietal areas and decreased in frontal regions. GMv increases largely overlapped with fluid decreases and vice versa. Larger increases in precentral gyrus (M1)/ postcentral gyrus (S1+2) GMv and fluid decreases were associated with smaller balance decrements. Vestibular activation in the bilateral insular cortex increased with bed rest and subsequently recovered. Larger increases in vestibular activation in multiple brain regions were associated with greater decrements in balance and mobility. We found connectivity increases between left M1 with right S1+2 and the superior parietal lobule, and right vestibular cortex with the cerebellum. Decreases were observed between right Lobule VIII with right S1+2 and the supramarginal gyrus, right posterior parietal cortex (PPC) with occipital regions, and the right superior posterior fissure with right Crus I and II. Connectivity strength between left M1 and right S1+2/superior parietal lobule increased the most in individuals that exhibited the least balance impairments. In sum, we observed HDBR-related changes in measures of brain structure, function, and network connectivity, which correlated with indices of sensorimotor function. Recovery was observed post HDBR but remained incomplete at 12 days post-HDBR. Preliminary findings from our parallel ongoing flight study will be compared and contrasted with bed rest results during this presentation.

Seidler, R. D.↗

NASA NTRSDate not supplied

Segmented Hexagonal Antenna Reflector Concentrically Stacked Using Shape Memory Composite Tubular Hinges

A new architecture for solid surface reflector antennas scalable to sizes greater than 10 m is presented. The design combines the compact, lightness and simplicity characteristics of advanced deployable structures to create sub-reflectors that can be assembled in space into larger units using a robotic arm and operations under development by a related parallel project. The seven-panel hexagonal sub-reflector is divided into hexagonal panels of that efficiently stack concentrically and vertically. The central panel is connected to each side panel on the back side by a pair of tubular shape memory composite hinges that enable the required deployment kinematics. A secondary mechanism ultimately closes the interpanel gap. The focus of the paper is on the development of the sub-reflector elements, namely the tubular hinges that use embedded heaters and sensors for actuation, the actuation mechanisms, and the lightweight sandwich construction panels. A finite element analysis parametric study assessed how design features of the hinge affect its stowage and deployment dynamics. The component fabrication and testing plans for the two-panel assembly breadboard model are outlined.

deployable reflectors↗

NASA NTRSDate not supplied

Segmented Hexagonal Antenna Reflector Concentrically Stacked Using Shape Memory Composite Tubular Hinges

deployable reflectors↗

NASA NTRS1972

Temperature compensation of light emitting diodes and photodiodes.

Improved temperature compensation of the output from a GaAs LED can be obtained by connecting the diode in series with the emitter of an n-p-n transistor whose base circuit incorporates a high-gain operational amplifier and a parallel thermistor-resistor network. The temperature dependence of several photodiodes is also reported along with a practical temperature compensation scheme. Finally, the temperature compensation of a photon coupled pair consisting of a GaAs LED and a silicon photodiode is described. The combination provides a stability, linearity, and repeatability of about 1% over the upper 60% of the LED forward current range in the temperature interval from 15 to 45 C.

Burrous, C. N.↗

NASA NTRS1993

Fault-tolerant onboard digital information switching and routing for communications satellites

The NASA Lewis Research Center is developing an information-switching processor for future meshed very-small-aperture terminal (VSAT) communications satellites. The information-switching processor will switch and route baseband user data onboard the VSAT satellite to connect thousands of Earth terminals. Fault tolerance is a critical issue in developing information-switching processor circuitry that will provide and maintain reliable communications services. In parallel with the conceptual development of the meshed VSAT satellite network architecture, NASA designed and built a simple test bed for developing and demonstrating baseband switch architectures and fault-tolerance techniques. The meshed VSAT architecture and the switching demonstration test bed are described, and the initial switching architecture and the fault-tolerance techniques that were developed and tested are discussed.

Shalkhauser, Mary JO↗

NASA NTRS1989

Towards real-time simulation of large space structures: Stabilization of fluid/thermal/structure interactions and implementation on high performance supercomputers

Within the Center for Space Construction, the SIMSTRUC project's objectives center around the development of simulation tools for the realistic analysis of large space structures. The word 'tools' is the broad sense; it designates mathematical models, finite element/finite difference formulations, computational algorithms, implementations on advanced computer architectures, and visualization capabilities. The results of our activities during the first year within the SIMSTRUC project are reported. On the modeling side, an alternative approach to fluid/thermal/structure interaction analysis that is a departure from the 'loosely coupled' and 'unified' approaches that are being currently practiced are described. The advantages of our approach both in terms of accuracy and computational efficiency were demonstrated. On the computational side, a software architecture for parallel/vector and massively parallel supercomputers that speeds up finite element and finite difference computations by several orders of magnitude is presented. As an example, the simulation of the deployment of a space structure that used to require over six hours of a workstation using a conventional finite element software, now runs on a multiprocessor using a parallel computation strategy in less than three seconds. In order to promote the physical understanding of the simulation behavior, a real-time visualization capability on the Connection Machine, which allows the analyst to watch the graphical animation of the results at the same time these are generated, was also developed. It is believed that by combining efficient analytical formulations with the state-of-the-art high performance computer implementations and superfast visualization capabilities, SIMSTRUC is moving fast towards the real-time simulation of large space structures. The designers as well as the researchers will certainly benefit from this technology.

Farhat, C.↗