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DOE OSTI2022

Real-Time Drilling Optimization System for Improved Overall Rate of Penetration and Reduced Cost Per Foot in Geothermal Drilling

The key to success in geothermal drilling is economic feasibility, and a major cost in the development of geothermal resources is the actual drilling of the wells. In this project, a real-time drilling optimization system for geothermal drilling was developed. The system couples three individual components while drilling. The first component is a drill stem vibration analysis model, the second is Mechanical Specific Energy (MSE) analyses, and the third is a detailed PDC Rate of Penetration (ROP) drill bit model for optimum RPM and WOB combinations. The benefit of the coupled system is that the range of WOB and RPM could be selected to avoid drill stem vibrations. Secondly, MSE is used as an efficiency measure and the detailed PDC drill bit model ensures the drill bit does not endure temperatures that exceed the temperature at which the PDC cutters experience accelerated wear. The new detailed PDC bit model is based on rock/bit interaction that physically tracks the PDC cutter wear flats as the bit drills ahead giving the capability to calculate the temperature being generated underneath the worn cutters to better advise on operational parameters to avoid accelerated cutter wear and failure and to ensure that operational parameters are applied so that overall ROP is maximized. By combining the drill stem vibrations and the detailed PDC bit cutter wear and “safe” non-accelerated cutter wear temperature and optimum ranges of operating parameters, it results in higher ROP and lower cost drilling. Single cutter PDC testing performed in different lithologies at Sandia was utilized to verify the PDC cutter forces and depth of cut for new and worn cutters. Based on single cutter PDC temperature modeling, verification using single cutter data from the testing done by National Oilwell Varco (NOV) was performed. Sandia’s Hard-Rock Drilling Facility (HRDF) was utilized to test different drill bit configurations with different cutter designs and wear status with different induced modes of vibration to obtain the critical bit RPM/WOB ranges resulting in ineffective drilling and low ROP. The collected test data were further used to verify and calibrate the full hole PDC ROP model that was developed based on single cutter interaction data. A full coupled drill stem vibration model was formulated and verified with geothermal field data from the Chocolate Mountain Aerial Gunnery Range (CMAGR). A graphical user interface (GUI) was developed using Tkinter library in the computer programming language Python, which integrates all the developed models in one system. The developed system consists mainly of the PDC ROP model, PDC bit wear model, PDC cutter temperature model, Mechanical Specific Energy (MSE) model, and drillstring vibration model integrated into one system. The developed system can be used for both, post well analysis and real-time optimization using different criteria such as ROP maximization or MSE minimization. The software uses Differential Evolution Algorithm (DEA) to find optimum values for operational parameters based on last foot drilled while avoiding the drillstring vibration and cutter temperature critical operating parameters.

15 GEOTHERMAL ENERGY↗

NASA NTRS1982

The effects of transmitter/receiver clock time-base instability on coherent communication system performance

The purpose of this paper is to present a model and associated analysis of the deleterious effects which both transmitter and receiver data clock time-base instability have on bit-error probability. The types of time-base instability modeled and analyzed include what is commonly referred to as bit jitter (epoch jitter), bit-jitter rate (time interval jitter), and data asymmetry. The bit-error probability is determined as a function of the statistical characteristics of the time-base instability, the data-transition density, the signal-to-noise ratio in the bit-rate bandwidth and the mechanizations of both the data-bit detector and bit synchronizer. The latter is manifested through the bit synchronizer's natural frequency and loop-damping parameters. Numerical results which indicate the sensitivity of the system bit-error rate to various parameters of the model are provided.

Chie, C. M.↗

NASA NTRS2005

Reconfigurable data path processor

A reconfigurable data path processor comprises a plurality of independent processing elements. Each of the processing elements advantageously comprising an identical architecture. Each processing element comprises a plurality of data processing means for generating a potential output. Each processor is also capable of through-putting an input as a potential output with little or no processing. Each processing element comprises a conditional multiplexer having a first conditional multiplexer input, a second conditional multiplexer input and a conditional multiplexer output. A first potential output value is transmitted to the first conditional multiplexer input, and a second potential output value is transmitted to the second conditional multiplexer output. The conditional multiplexer couples either the first conditional multiplexer input or the second conditional multiplexer input to the conditional multiplexer output, according to an output control command. The output control command is generated by processing a set of arithmetic status-bits through a logical mask. The conditional multiplexer output is coupled to a first processing element output. A first set of arithmetic bits are generated according to the processing of the first processable value. A second set of arithmetic bits may be generated from a second processing operation. The selection of the arithmetic status-bits is performed by an arithmetic-status bit multiplexer selects the desired set of arithmetic status bits from among the first and second set of arithmetic status bits. The conditional multiplexer evaluates the select arithmetic status bits according to logical mask defining an algorithm for evaluating the arithmetic status bits.

Donohoe, Gregory↗

NASA NTRS2007

Analog Nonvolatile Computer Memory Circuits

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

MacLeod, Todd↗

NASA NTRS1984

Optimum Cyclic Redundancy Codes for Noisier Channels

Binary cyclic redundancy codes for feedback communication over noisy digital links are considered. The standard 16 bit American Data and Computer Communication Protocol (ADCCP) polynomial is designed for digital links which already have a low input bit error probability. For file transfer between personal computers over telephone circuits, the quality of resulting digital circuit may be much lower. The 3 byte (24 bit) and 4 byte (32 bit) polynomials are considered. Generator polynomials of a certain class have minimum weight and yet achieve the bound on minimum distance for arbitrary codes. Particular choices for 24 bit and 32 bit redundancies are exhibited: of weight and distance 6 in the 24-bit case; and weight 10 and distance 8 in the 32-bit case.

Merkey, P.↗

NASA NTRS1984

Optimum cyclic redundancy codes for noisy channels

Merkey, P.↗

NASA NTRS1996

DCTune Perceptual Optimization of Compressed Dental X-Rays

In current dental practice, x-rays of completed dental work are often sent to the insurer for verification. It is faster and cheaper to transmit instead digital scans of the x-rays. Further economies result if the images are sent in compressed form. DCTune is a technology for optimizing DCT (digital communication technology) quantization matrices to yield maximum perceptual quality for a given bit-rate, or minimum bit-rate for a given perceptual quality. Perceptual optimization of DCT color quantization matrices. In addition, the technology provides a means of setting the perceptual quality of compressed imagery in a systematic way. The purpose of this research was, with respect to dental x-rays, 1) to verify the advantage of DCTune over standard JPEG (Joint Photographic Experts Group), 2) to verify the quality control feature of DCTune, and 3) to discover regularities in the optimized matrices of a set of images. We optimized matrices for a total of 20 images at two resolutions (150 and 300 dpi) and four bit-rates (0.25, 0.5, 0.75, 1.0 bits/pixel), and examined structural regularities in the resulting matrices. We also conducted psychophysical studies (1) to discover the DCTune quality level at which the images became 'visually lossless,' and (2) to rate the relative quality of DCTune and standard JPEG images at various bitrates. Results include: (1) At both resolutions, DCTune quality is a linear function of bit-rate. (2) DCTune quantization matrices for all images at all bitrates and resolutions are modeled well by an inverse Gaussian, with parameters of amplitude and width. (3) As bit-rate is varied, optimal values of both amplitude and width covary in an approximately linear fashion. (4) Both amplitude and width vary in systematic and orderly fashion with either bit-rate or DCTune quality; simple mathematical functions serve to describe these relationships. (5) In going from 150 to 300 dpi, amplitude parameters are substantially lower and widths larger at corresponding bit-rates or qualities. (6) Visually lossless compression occurs at a DCTune quality value of about 1. (7) At 0.25 bits/pixel, comparative ratings give DCTune a substantial advantage over standard JPEG. As visually lossless bit-rates are approached, this advantage of necessity diminishes. We have concluded that DCTune optimized quantization matrices provide better visual quality than standard JPEG. Meaningful quality levels may be specified by means of the DCTune metric. Optimized matrices are very similar across the class of dental x-rays, suggesting the possibility of a 'class-optimal' matrix. DCTune technology appears to provide some value in the context of compressed dental x-rays.

Watson, Andrew B.↗

NASA NTRS2010

Performance Bounds on Two Concatenated, Interleaved Codes

A method has been developed of computing bounds on the performance of a code comprised of two linear binary codes generated by two encoders serially concatenated through an interleaver. Originally intended for use in evaluating the performances of some codes proposed for deep-space communication links, the method can also be used in evaluating the performances of short-block-length codes in other applications. The method applies, more specifically, to a communication system in which following processes take place: At the transmitter, the original binary information that one seeks to transmit is first processed by an encoder into an outer code (Co) characterized by, among other things, a pair of numbers (n,k), where n (n > k)is the total number of code bits associated with k information bits and n k bits are used for correcting or at least detecting errors. Next, the outer code is processed through either a block or a convolutional interleaver. In the block interleaver, the words of the outer code are processed in blocks of I words. In the convolutional interleaver, the interleaving operation is performed bit-wise in N rows with delays that are multiples of B bits. The output of the interleaver is processed through a second encoder to obtain an inner code (Ci) characterized by (ni,ki). The output of the inner code is transmitted over an additive-white-Gaussian- noise channel characterized by a symbol signal-to-noise ratio (SNR) Es/No and a bit SNR Eb/No. At the receiver, an inner decoder generates estimates of bits. Depending on whether a block or a convolutional interleaver is used at the transmitter, the sequence of estimated bits is processed through a block or a convolutional de-interleaver, respectively, to obtain estimates of code words. Then the estimates of the code words are processed through an outer decoder, which generates estimates of the original information along with flags indicating which estimates are presumed to be correct and which are found to be erroneous. From the perspective of the present method, the topic of major interest is the performance of the communication system as quantified in the word-error rate and the undetected-error rate as functions of the SNRs and the total latency of the interleaver and inner code. The method is embodied in equations that describe bounds on these functions. Throughout the derivation of the equations that embody the method, it is assumed that the decoder for the outer code corrects any error pattern of t or fewer errors, detects any error pattern of s or fewer errors, may detect some error patterns of more than s errors, and does not correct any patterns of more than t errors. Because a mathematically complete description of the equations that embody the method and of the derivation of the equations would greatly exceed the space available for this article, it must suffice to summarize by reporting that the derivation includes consideration of several complex issues, including relationships between latency and memory requirements for block and convolutional codes, burst error statistics, enumeration of error-event intersections, and effects of different interleaving depths. In a demonstration, the method was used to calculate bounds on the performances of several communication systems, each based on serial concatenation of a (63,56) expurgated Hamming code with a convolutional inner code through a convolutional interleaver. The bounds calculated by use of the method were compared with results of numerical simulations of performances of the systems to show the regions where the bounds are tight (see figure).

Moision, Bruce↗

NASA NTRS2006

Active Struts With Variable Spring Stiffness and Damping

An ultrasonic rock-abrasion tool (URAT) was developed using the same principle of ultrasonic/sonic actuation as that of the tools described in two prior NASA Tech Briefs articles: Ultrasonic/ Sonic Drill/Corers With Integrated Sensors (NPO-20856), Vol. 25, No. 1 (January 2001), page 38 and Ultrasonic/ Sonic Mechanisms for Drilling and Coring (NPO-30291), Vol. 27, No. 9 (September 2003), page 65. Hence, like those tools, the URAT offers the same advantages of low power demand, mechanical simplicity, compactness, and ability to function with very small axial loading (very small contact force between tool and rock). Like a tool described in the second of the cited previous articles, a URAT includes (1) a drive mechanism that comprises a piezoelectric ultrasonic actuator, an amplification horn, and a mass that is free to move axially over a limited range and (2) an abrasion tool bit. A URAT tool bit is a disk that has been machined or otherwise formed to have a large number of teeth and an overall shape chosen to impart the desired shape (which could be flat or curved) to the rock surface to be abraded. In operation, the disk and thus the teeth are vibrated in contact with the rock surface. The concentrated stresses at the tips of the impinging teeth repeatedly induce microfractures and thereby abrade the rock. The motion of the tool induces an ultrasonic transport effect that displaces the cuttings from the abraded area. The figure shows a prototype URAT. A piezoelectric-stack/horn actuator is housed in a cylindrical container. The movement of the actuator and bit with respect to the housing is aided by use of mechanical sliders. A set of springs accommodates the motion of the actuator and bit into or out of the housing through an axial range between 5 and 7 mm. The springs impose an approximately constant force of contact between the tool bit and the rock to be abraded. A dust shield surrounds the bit, serving as a barrier to reduce the migration of rock debris to sensitive instrumentation or mechanisms in the vicinity. A bushing at the tool-bit end of the housing reduces the flow of dust into the actuator and retains the bit when no axial load is applied.

Farley, Gary L.↗

NASA NTRS2006

Ultrasonically Actuated Tools for Abrading Rock Surfaces

Dolgin, Benjamin↗

NASA NTRS2004

Ultralow-Power Digital Correlator for Microwave Polarimetry

A recently developed high-speed digital correlator is especially well suited for processing readings of a passive microwave polarimeter. This circuit computes the autocorrelations of, and the cross-correlations among, data in four digital input streams representing samples of in-phase (I) and quadrature (Q) components of two intermediate-frequency (IF) signals, denoted A and B, that are generated in heterodyne reception of two microwave signals. The IF signals arriving at the correlator input terminals have been digitized to three levels (-1,0,1) at a sampling rate up to 500 MHz. Two bits (representing sign and magnitude) are needed to represent the instantaneous datum in each input channel; hence, eight bits are needed to represent the four input signals during any given cycle of the sampling clock. The accumulation (integration) time for the correlation is programmable in increments of 2(exp 8) cycles of the sampling clock, up to a maximum of 2(exp 24) cycles. The basic functionality of the correlator is embodied in 16 correlation slices, each of which contains identical logic circuits and counters (see figure). The first stage of each correlation slice is a logic gate that computes one of the desired correlations (for example, the autocorrelation of the I component of A or the negative of the cross-correlation of the I component of A and the Q component of B). The sampling of the output of the logic gate output is controlled by the sampling-clock signal, and an 8-bit counter increments in every clock cycle when the logic gate generates output. The most significant bit of the 8-bit counter is sampled by a 16-bit counter with a clock signal at 2(exp 8) the frequency of the sampling clock. The 16-bit counter is incremented every time the 8-bit counter rolls over.

Piepmeier, Jeffrey R.↗

DOE OSTI2021

Numerical Evidence for Many-Body Localization in Two and Three Dimensions

Disorder and interactions can lead to the breakdown of statistical mechanics in certain quantum systems, a phenomenon known as many-body localization (MBL). Much of the phenomenology of MBL emerges from the existence of localized-bits, or l-bits, a set of conserved quantities that are spatially localized and binary (i.e., possess only ±1 eigenvalues). While MBL and l-bits are known to exist in one-dimensional systems, their existence in dimensions greater than one is a key open question. To tackle this question, we develop an algorithm that can find approximate binary l-bits in arbitrary dimensions by adaptively generating a basis of operators in which to represent the l-bit. We use the algorithm to study four models: the one-, two-, and three-dimensional disordered Heisenberg models and the two-dimensional disordered hard-core Bose-Hubbard model. For all four of the models studied, our algorithm finds high-quality l-bits at large disorder strength and rapid qualitative changes in the distributions of l-bits in particular ranges of disorder strengths, suggesting the existence of MBL transitions. Furthermore, these transitions in the one-dimensional Heisenberg model and two-dimensional Bose-Hubbard model coincide well with past estimates of the critical disorder strengths in these models which further validates the evidence of MBL-like behavior in the other two and three-dimensional models we examine. In addition to finding MBL-like behavior in higher dimensions, our algorithm can be used to probe MBL in various geometries and dimensionality.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

NASA NTRS1977

Bandwidth compression of synthetic aperture radar imagery by quantization of raw radar data

A study is made of the effects of quantization of the radar returns transmitted from aircraft or spacecraft employing a synthetic aperture radar system. The study is based on the output images obtained after one-bit, two-bit, and eight-bit quantizations and comparing the results to ground truth. In this way the degradation resulting from data or bandwidth reduction is determined. Quantization is evaluated in terms of crater scene, number of looks, and transmission error rate. It is found that two-bit quantization of raw radar data from homogeneous scenes processed to 32 looks yields nearly all the details of the original. One-bit quantization of raw radar data from homogeneous scenes processed to 32 looks yields a good visual representation of the scene but some fine detail is lost and the absolute reflectivity level is not reliable. Image quality is observed to improve with more looks and video and intermediate frequency quantization are not distinguishable even for one-bit quantizations. Image quality is not influenced by bit error rates less than about 2 to the -7th power.

Lipes, R. G.↗

NASA NTRS1981

The effects of transmitter/receiver clock time base instability on coherent communication system performance

The purpose of this paper is to present a model and associated analysis of the deleterious effects which both transmitter and receiver data clock time-base instability have on bit error probability. The types of time-base instability modeled and analyzed include bit jitter (epoch jitter), bit jitter rate (time interval jitter) and data asymmetry. The bit error probability is determined as a function of the statistical characteristics of the time-base instability, the data transition density, the signal-to-noise ratio in the bit rate bandwidth and the mechanizations of both the data bit detector and bit synchronizer. Numerical results are provided.

Chie, C. M.↗

NASA NTRS1983

Symbol synchronization for the TDRSS decoder

Each 8 bits out of the Viterbi decoder correspond to one symbol of the R/S code. Synchronization must be maintained here so that each 8-bit symbol delivered to the R/S decoder corresponds to an 8-bit symbol from the R/S encoder. Lack of synchronization, would cause an error in almost every R/S symbol since even a - 1-bit sync slip shifts every bit in each 8-bit symbol by one position, therby confusing the mapping betweeen 8-bit sequences and symbols. The error correcting capability of the R/S code would be exceeded. Possible ways to correcting this condition include: (1) designing the R/S decoder to recognize the overload and shifting the output sequence of the inner decoder to establish a different sync state; (2) using the characteristics of the inner decoder to establish symbol synchronization for the outer code, with or without a deinterleaver and an interleaver; and (3) modifying the encoder to alternate periodically between two sets of generators.

Costello, D. J., Jr.↗

NASA NTRS1994

Four Channel Laser Firing Unit Using Laser Diodes

This paper describes the accomplishments and status of PS/EDD's (Pacific Scientific/Energy Dynamics Division) internal research and development effort to prototype and demonstrate a practical four channel laser firing unit (LFU) that uses laser diodes to initiate pyrotechnic events. The LFU individually initiates four ordnance devices using the energy from four diode lasers carried over the fiber optics. The LFU demonstrates end-to-end optical built in test (BIT) capabilities. Both Single Fiber Reflective BIT and Dual Fiber Reflective BIT approaches are discussed and reflection loss data is presented. This paper includes detailed discussions of the advantages and disadvantages of both BIT approaches, all-fire and no-fire levels, and BIT detection levels. The following topics are also addressed: electronic control and BIT circuits, fiber optic sizing and distribution, and an electromechanical shutter type safe/arm device. This paper shows the viability of laser diode initiation systems and single fiber BIT for typing military applications.

David Rosner Sr.↗

NASA NTRS2007

Dog-Bone Horns for Piezoelectric Ultrasonic/Sonic Actuators

A shape reminiscent of a dog bone has been found to be superior to other shapes for mechanical-amplification horns that are components of piezoelectrically driven actuators used in a series of related devices denoted generally as ultrasonic/sonic drill/corers (USDCs). The first of these devices was reported in Ultrasonic/Sonic Drill/Corers With Integrated Sensors (NPO-20856), NASA Tech Briefs, Vol. 25, No. 1 (January 2001), page 38. The dog-bone shape was conceived especially for use in a more recent device in the series, denoted an ultrasonic/ sonic gopher, that was described in Ultrasonic/Sonic Mechanisms for Drilling and Coring (NPO-30291), NASA Tech Briefs, Vol. 27, No. 9 (September 2003), page 65. The figure shows an example of a dog-bone-shaped horn and other components of an ultrasonic gopher. Prerequisite to a meaningful description of this development is an unavoidably lengthy recapitulation of the principle of operation of a USDC and, more specifically, of the ultrasonic/sonic gopher as described previously in NASA Tech Briefs. The ultrasonic actuator includes a stack of piezoelectric rings, the horn, a metal backing, and a bolt that connects the aforementioned parts and provides compressive pre-strain to the piezoelectric stack to prevent breakage of the rings during extension. The stack of piezoelectric rings is excited at the resonance frequency of the overall ultrasonic actuator. Through mechanical amplification by the horn, the displacement in the ultrasonic vibration reaches tens of microns at the tip of the horn. The horn hammers an object that is denoted the free mass because it is free to move longitudinally over a limited distance between hard stops: The free mass bounces back and forth between the ultrasonic horn and a tool bit (a drill bit or a corer). Because the longitudinal speed of the free mass is smaller than the longitudinal speed of vibration of the tip of the horn, contact between the free mass and the horn tip usually occurs at a phase of the vibration favorable to transfer of momentum from the horn to the free mass. Therefore, the free mass picks up momentum and is accelerated back to the tool bit. Upon impact of the free mass on the tool bit, momentum is transferred to the tool bit. The impacts of the free mass on the tool bit repeat at a sonic frequency that can range from tens of hertz to about 1 kHz. The shock waves caused by the impacts of the free mass propagate to the interface between the tool bit and the medium (typically, rock, ice, or other brittle material) to be drilled or cored. The medium becomes fractured when its ultimate strain is exceeded at the medium/tool-bit interface. This concludes the description of the principle of operation.

Sherrit, Stewart↗

DOE OSTI2020

Dynamic variable precision computation

A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

97 MATHEMATICS AND COMPUTING↗