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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 379 records · Page 21
All sourcesNASA NTRSDOE OSTI
NASA NTRS1981

Video framerate, resolution and grayscale tradeoffs for undersea telemanipulator

The product of Frame Rate (F) in frames per second, Resolution (R) in total pixels and grayscale in bits (G) equals the transmission band rate in bits per second. Thus for a fixed channel capacity there are tradeoffs between F, R and G in the actual sampling of the picture for a particular manual control task in the present case remote undersea manipulation. A manipulator was used in the MASTER/SLAVE mode to study these tradeoffs. Images were systematically degraded from 28 frames per second, 128 x 128 pixels and 16 levels (4 bits) grayscale, with various FRG combinations constructed from a real-time digitized (charge-injection) video camera. It was found that frame rate, resolution and grayscale could be independently reduced without preventing the operator from accomplishing his/her task. Threshold points were found beyond which degradation would prevent any successful performance. A general conclusion is that a well trained operator can perform familiar remote manipulator tasks with a considerably degrade picture, down to 50 K bits/ sec.

Ranadive, V.↗
NASA NTRS1981

Performance of quadrature overlapped raised-cosine modulation over nonlinear satellite channels

This paper considers the performance evaluation of Staggered Quadrature Overlapped Raised Cosine (SQORC) signal transmission through wideband nonlinear satellite channels in the presence of uplink and downlink additive Gaussian noise. Expressions for the bit error rate are derived for a general transponder model with AM-AM and AM-PM conversion. It is shown that the bit error rate of SQORC is one-half of the sum of the bit error rate of MSK at 2/3 of the uplink signal-to-noise ratio and the bit error rate of Quadriphase Phase-Shift Keying QPSK at 4/3 of the uplink signal-to-noise ratio, whereas the spectrum of SQROC is the product of MSK and QPSK spectra. Numerical results are presented for a transponder which is modelled as a hard limiter.

Divsalar, D.↗
NASA NTRS1983

Massively parallel processor computer

An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array is described. It comprises a large number (e.g., 16,384 in a 128 x 128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered parallel data, including spatial translation by shifting or sliding of bits vertically or horizontally to neighboring processing elements.

Fung, L. W.↗
NASA NTRS1985

Digital Ratiometer

Small, low-cost comparator with 24-bit-precision yields ratio signal from pair of analog or digital input signals. Arithmetic logic chips (bit-slice) sample two 24-bit analog-to-digital converters approximately once every millisecond and accumulate them in two 24-bit registers. Approach readily modified to arbitrary precision.

Beer, R.↗
NASA NTRS1984

Navier-Stokes Simulation of Homogeneous Turbulence on the CYBER 205

A computer code which solves the Navier-Stokes equations for three dimensional, time-dependent, homogenous turbulence has been written for the CYBER 205. The code has options for both 64-bit and 32-bit arithmetic. With 32-bit computation, mesh sizes up to 64 (3) are contained within core of a 2 million 64-bit word memory. Computer speed timing runs were made for various vector lengths up to 6144. With this code, speeds a little over 100 Mflops have been achieved on a 2-pipe CYBER 205. Several problems encountered in the coding are discussed.

Wu, C. T.↗
NASA NTRS1984

Postprocessing for the UCLA climate model

Postprocessing programs written to analyze the results of a general circulation model are described. The model history data is interpolated to pressure surfaces, converted from 64-bit Cyber words to 32 bit IBM words, and transferred to tape for further analysis. The time average program reads the interpolation output tape and produces 15-day time averages. The model outputs a very detailed record for selected grid points. This data is sent to a tape in Cyber full words. The conversion program changes the format of the tape from 64 bit Cyber words to 32 bit IBM words, processing a month of data at a time. The grid-point history sorting program inputs the converted grid point history tape and sorts it by time. The end product is a tape with a time history of each field for every point. After the PBP data has been stored, it can be plotted. The plotting package is flexible, and allows the choice of fields and grid points. The one-dimensional fields are plotted as functions of time, and a daily summary is also produced. For the two-dimensional fields, time-height cross sections and daily summaries are produced. The model plotting package produces plots for all fields on the time average and pressure tapes. These plots include world maps, polar projections, zonal means, vectors, streamlines, and latitude-height plots.

Abeles, J.↗
NASA NTRS1986

Optimum Cyclic Redundancy Codes for Noisy Channels

Capabilities and limitations of cyclic redundancy codes (CRC's) for detecting transmission errors in data sent over relatively noisy channels (e.g., voice-grade telephone lines or very-high-density storage media) discussed in 16-page report. Due to prevalent use of bytes in multiples of 8 bits data transmission, report primarily concerned with cases in which both block length and number of redundant bits (check bits for use in error detection) included in each block are multiples of 8 bits.

Posner, E. C.↗
NASA NTRS1984

The undetected error probability for shortened hamming codes

Hamming or shortened Hamming codes are widely used for error detection in data communications. For example, the CCITT (International Telegraph and Telephone Consultative Committee) recommendation X.25 for packet-switched data networks adopts a distance-4 cyclic Hamming code with 16 parity-check bits for error detection. The natural length of this code is n = 2(15)-1 = 32,767. In practice the length of a data packet is no more than a few thousand bits which is much shorter than the natural length of the code. Consequently, a shortened version of thecode is used. Often the length of a data packet varies, say from a few hundred bits to a few thousand bits, hence the code must be shortened by various degrees. Shortening affects the performance of the code. The error-detection performance of shortened Hamming codes, particularly the codes obtained from the distance-4 Hamming codes adopted by CCITT recommendation X.25, is investigated. A method for computing the probability of an undetected error is presented.

Costello, D. J., Jr.↗
NASA NTRS1984

A high-speed digital signal processor for atmospheric radar, part 7.3A

The Model SP-320 device is a monolithic realization of a complex general purpose signal processor, incorporating such features as a 32-bit ALU, a 16-bit x 16-bit combinatorial multiplier, and a 16-bit barrel shifter. The SP-320 is designed to operate as a slave processor to a host general purpose computer in applications such as coherent integration of a radar return signal in multiple ranges, or dedicated FFT processing. Presently available is an I/O module conforming to the Intel Multichannel interface standard; other I/O modules will be designed to meet specific user requirements. The main processor board includes input and output FIFO (First In First Out) memories, both with depths of 4096 W, to permit asynchronous operation between the source of data and the host computer. This design permits burst data rates in excess of 5 MW/s.

Brosnahan, J. W.↗
NASA NTRS1985

In search of a 2-dB coding gain

A recent code search found a (15,1/5), a (14,1/6), and a (15,1/6) convolutional code which, when concatenated with a 10-bit (1023,959) Reed-Solomon (RS) code, achieves a bit-error rate (BER) of 0.000001 at a bit signal-to-noise ratio (SNR) of 0.50 dB, 0.47 dB and 0.42 B, respectively. All of these three codes outperform the Voyager communication system, our baseline, which achieves a BER of 10.000001 at bit SNR of 2.53 db, by more than 2 dB. The 2 dB coding improvement goal was exceeded.

Yuen, J. H.↗
NASA NTRS1989

A new VLSI architecture for a single-chip-type Reed-Solomon decoder

A new very large scale integration (VLSI) architecture for implementing Reed-Solomon (RS) decoders that can correct both errors and erasures is described. This new architecture implements a Reed-Solomon decoder by using replication of a single VLSI chip. It is anticipated that this single chip type RS decoder approach will save substantial development and production costs. It is estimated that reduction in cost by a factor of four is possible with this new architecture. Furthermore, this Reed-Solomon decoder is programmable between 8 bit and 10 bit symbol sizes. Therefore, both an 8 bit Consultative Committee for Space Data Systems (CCSDS) RS decoder and a 10 bit decoder are obtained at the same time, and when concatenated with a (15,1/6) Viterbi decoder, provide an additional 2.1-dB coding gain.

Hsu, I. S.↗
NASA NTRS1990

Synchronization Technique For Reception Of Coded Data

Shortest sequence of bits likely to be filled with error bursts examined. Algorithm improves synchronization of frames of noisy binary-coded data signals after Viterbi decoding (recovery from "inner" convolutional code used in transmission channel) and before Reed-Solomon or other decoding (recovery from "outer" error-correcting block code). Based on comparisons of sequences of correct and erroneous Viterbi-decoded received bits with known marker sequence denoting beginning of frame of data. Does not require count of number of bits in received sequence disagreeing with corresponding bits in marker sequence.

Shahshahani, Mehrdad M.↗
NASA NTRS1989

Frame synchronization methods based on channel symbol measurements

The current DSN frame synchronization procedure is based on monitoring the decoded bit stream for the appearance of a sync marker sequence that is transmitted once every data frame. The possibility of obtaining frame synchronization by processing the raw received channel symbols rather than the decoded bits is explored. Performance results are derived for three channel symbol sync methods, and these are compared with results for decoded bit sync methods reported elsewhere. It is shown that each class of methods has advantages or disadvantages under different assumptions on the frame length, the global acquisition strategy, and the desired measure of acquisition timeliness. It is shown that the sync statistics based on decoded bits are superior to the statistics based on channel symbols, if the desired operating region utilizes a probability of miss many orders of magnitude higher than the probability of false alarm. This operating point is applicable for very large frame lengths and minimal frame-to-frame verification strategy. On the other hand, the statistics based on channel symbols are superior if the desired operating point has a miss probability only a few orders of magnitude greater than the false alarm probability. This happens for small frames or when frame-to-frame verifications are required.

Dolinar, S.↗
NASA NTRS1989

Floating point arithmetic in future supercomputers

Considerations in the floating-point design of a supercomputer are discussed. Particular attention is given to word size, hardware support for extended precision, format, and accuracy characteristics. These issues are discussed from the perspective of the Numerical Aerodynamic Simulation Systems Division at NASA Ames. The features believed to be most important for a future supercomputer floating-point design include: (1) a 64-bit IEEE floating-point format with 11 exponent bits, 52 mantissa bits, and one sign bit and (2) hardware support for reasonably fast double-precision arithmetic.

Bailey, David H.↗
NASA NTRS1991

Space Communications Artificial Intelligence for Link Evaluation Terminal (SCAILET)

A software application to assis end-users of the Link Evaluation Terminal (LET) for satellite communication is being developed. This software application incorporates artificial intelligence (AI) techniques and will be deployed as an interface to LET. The high burst rate (HBR) LET provides 30 GHz transmitting/20 GHz receiving, 220/110 Mbps capability for wideband communications technology experiments with the Advanced Communications Technology Satellite (ACTS). The HBR LET and ACTS are being developed at the NASA Lewis Research Center. The HBR LET can monitor and evaluate the integrity of the HBR communications uplink and downlink to the ACTS satellite. The uplink HBR transmission is performed by bursting the bit-pattern as a modulated signal to the satellite. By comparing the transmitted bit pattern with the received bit pattern, HBR LET can determine the bit error rate BER) under various atmospheric conditions. An algorithm for power augmentation is applied to enhance the system's BER performance at reduced signal strength caused by adverse conditions. Programming scripts, defined by the design engineer, set up the HBR LET terminal by programming subsystem devices through IEEE488 interfaces. However, the scripts are difficult to use, require a steep learning curve, are cryptic, and are hard to maintain. The combination of the learning curve and the complexities involved with editing the script files may discourage end-users from utilizing the full capabilities of the HBR LET system. An intelligent assistant component of SCAILET that addresses critical end-user needs in the programming of the HBR LET system as anticipated by its developers is described. A close look is taken at the various steps involved in writing ECM software for a C&P, computer and at how the intelligent assistant improves the HBR LET system and enhances the end-user's ability to perform the experiments.

Shahidi, Anoosh↗
NASA NTRS1990

Neural computation of arithmetic functions

An area of application of neural networks is considered. A neuron is modeled as a linear threshold gate, and the network architecture considered is the layered feedforward network. It is shown how common arithmetic functions such as multiplication and sorting can be efficiently computed in a shallow neural network. Some known results are improved by showing that the product of two n-bit numbers and sorting of n n-bit numbers can be computed by a polynomial-size neural network using only four and five unit delays, respectively. Moreover, the weights of each threshold element in the neural networks require O(log n)-bit (instead of n-bit) accuracy. These results can be extended to more complicated functions such as multiple products, division, rational functions, and approximation of analytic functions.

Siu, Kai-Yeung↗
NASA NTRS1990

50 Mbps free space direct detection laser diode optical communication system with Q = 4 PPM signaling

A 50 Mbps direct detection optical communication system for use in an intersatellite link was constructed with an AlGaAs laser diode transmitter and a silicon avalanche photodiode photodetector. The system used a Q = 4 PPM format. The receiver consisted of a maximum likelihood PPM detector and a timing recovery subsystem. The PPM slot clock was recovered at the receiver by using a transition detector followed by a PLL. The PPM word clock was recovered by using a second PLL whose input was derived from the presence of back-to-back PPM pulses contained in the received random PPM pulse sequences. The system achieved a bit error rate of 0.000001 at less than 50 detected signal photons/information bit. The receiver was capable of acquiring and maintaining slot and word synchronization for received signal levels greater than 20 photons/information bit, at which the receiver bit error rate was about 0.01.

Sun, Xiaoli↗
NASA NTRS1992

Integrated-Circuit Pseudorandom-Number Generator

Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.

Steelman, James E.↗