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DOE OSTI2020

Radiation-hard miniature optical engine with high bandwidth

Future silicon trackers will be operated in an intense radiation environment and require large volumes of data to be transmitted off detector. In addition, the optical modules must be of low mass in order to limit multiple scattering and nuclear interactions that would degrade the overall performance of the detector. Here, we present a miniature optical engine that satisfies these constraints. The optical engine consists of an ASIC driving a VCSEL (Vertical Cavity Surface Emitting Laser) array in an optical package. Two ASICs are designed to operate a 12-channel VCSEL array at 1.28 or 5.12 Gb/s per channel, which yields a total data rate of up to 60 Gb/s. The core transistors are fabricated in a 65 nm CMOS process which enhance the radiation-hardness. Each channel contains equalizer (CTLE) and clock-data recovery circuits (CDR) so that the ASIC can restore the highly distorted electrical signal after propagating through several meters of cables of small diameter. The equalizer, CDR, and VCSEL driver are configured via a digital I 2 C chip interface with triple redundant memory to mitigate single event upset (SEU) effects. The bias and modulation currents are controlled by a digital-to-analog converter (DAC). We present the design of the circuit together with the results of the simulations and preliminary measurements.

47 OTHER INSTRUMENTATION↗

DOE OSTI2023

A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors

The Skipper CCD-in-CMOS Parallel Read-Out Circuit (SPROCKET) is a mixed-signal front-end design for the readout of Skipper CCD-in-CMOS image sensors. SPROCKET is fabricated in a 65 nm CMOS process and each pixel occupies a 50$\mu$m $\times$ 50$\mu$m footprint. SPROCKET is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor array, such that one readout pixel is connected to a multiplexed array of nine Skipper-in-CMOS pixels to enable massively parallel readout. The front-end includes a variable gain preamplifier, a correlated double sampling circuit, and a 10-bit serial successive approximation register (SAR) ADC. The circuit achieves a sample rate of 100 ksps with 0.48 $\mathrm{e^-_{rms}}$ equivalent noise at the input to the ADC. SPROCKET achieves a maximum dynamic range of 9,000 $e^-$ at the lowest gain setting (or 900 $e^-$ at the lowest noise setting). The circuit operates at 100 Kelvin with a power consumption of 40 $\mu W$ per pixel. A SPROCKET test chip was submitted in September 2022, and test results will be presented at the conference.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2024

Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads

Abstract This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate machine learning (ML) workloads. We conducted an exploration of device fabrication and proposed system-algorithm co-design to boost performance. A novel FeCap device, incorporating an interfacial layer (IL) and$$\text {Hf}_{0.5}\text {Zr}_{0.5}\text {O}_2$$ Hf 0.5 Zr 0.5 O 2 (HZO), ensures a reduction in operating voltage and enhances HZO scaling while being compatible with CMOS circuits. The IL also enriches ferroelectricity and retention properties. When integrated into crossbar arrays, FeCaps and FeFETs demonstrate their effectiveness as IMC components, eliminating sneak paths and enabling selector-less operation, leading to notable improvements in energy efficiency and area utilization. However, it is worth noting that limited capacitance ratios in FeCaps introduced errors in multiply-and-accumulate (MAC) computations. The proposed co-design approach helps in mitigating these errors and achieves high accuracy in classifying the CIFAR-10 dataset, elevating it from a baseline of 10% to 81.7%. FeFETs in crossbars, with a higher on-off ratio, outperform FeCaps, and our proposed charge-based sensing scheme achieved at least an order of magnitude reduction in power consumption, compared to prevalent current-based methods.

Science & Technology - Other Topics↗

DOE OSTI2021

SULI Research Report Paper

Hybrid-CMOS (hCMOS) nanosecond x-ray imagers are a powerful timeresolved HED (high-energy-density) diagnostic due to their sensitivity to visible light, x-rays, and charged particles. However, significant pseudosinusoidal background oscillations have been observed in these sensors when exposed to an early incident excitation, a phenomenon that has been experimentally linked the sensor’s bond wire inductance. We analyze the oscillations both in the time domain and spatially to account for variations on the pixel level. Both theoretical techniques and analysis of experimental data have shown that the oscillations are a global sensor phenomenon. In addition, we effectively describe the oscillations with a physics-based model, giving further insight into the processes affecting them. This technique allows the hCMOS user to subtract out the oscillations from their measurements and improve accuracy.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2021

Billion-pixel x-ray camera (BiPC-X)

The continuing improvement in quantum efficiency (above 90% for single visible photons), reduction in noise (below 1 electron per pixel), and shrink in pixel pitch (less than 1 μm) enable billion-pixel x-ray cameras (BiPC-X) based on commercial complementary metal–oxide–semiconductor (CMOS) imaging sensors. We describe BiPC-X designs and prototype construction based on flexible tiling of commercial CMOS imaging sensors with millions of pixels. Device models are given for direct detection of low energy x rays (<10 keV) and indirect detection of higher energies using scintillators. Modified Birks’s law is proposed for light yield non-proportionality in scintillators as a function of x-ray energy. Single x-ray sensitivity and spatial resolution have been validated experimentally using a laboratory x-ray source and the Argonne Advanced Photon Source. Possible applications include wide field-of-view or large x-ray aperture measurements in high-temperature plasmas, the state-of-the-art synchrotron, x-ray free electron laser, and pulsed power facilities.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2023

The Regenerative Current Mirror: A Very Low Power Front-End Amplifier for Silicon Pixel Detectors

In pixelized detectors, reducing power consumption in the front end ASIC chips becomes a crucial demand. Optimization based on mature pre-amplifier schemes today is unlikely to bring sufficient improvements. A new CMOS front-end gain stage topology with very low power consumption called regenerative current mirror is developed to fulfill the demand. The circuit takes advantage of high speed performance of current amplification while operating with relatively low bias current. The regenerative current mirror uses a NMOS current mirror and a PMOS current mirror, both with nominal gain of 1, to form a loop-back topology that provides a positive feedback. An NMOS FET with an external adjustable voltage applied to it gate terminal is used to limit open loop gain of the current mirrors to be slightly lower than 1. This yields a net gain of the positive feedback loop to be much larger than 1 while operating the current mirrors under relatively low bias currents. Simulation shows that in 65 nm fabrication process, the power consumption of the gain stages suitable for silicon pixel detectors can be controlled < 10 micro-Watts per channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

NASA NTRS1997

Micro-Mechanical Voltage Tunable Fabry-Perot Filters Formed in (111) Silicon

The MEMS (Micro-Electro-Mechanical-Systems) technology is quickly evolving as a viable means to combine micro-mechanical and micro-optical elements on the same chip. One MEMS technology that has recently gained attention by the research community is the micro-mechanical Fabry-Perot optical filter. A MEMS based Fabry-Perot consists of a vertically integrated structure composed of two mirrors separated by an air gap. Wavelength tuning is achieved by applying a bias between the two mirrors resulting in an attractive electrostatic force which pulls the mirrors closer. In this work, we present a new micro-mechanical Fabry-Perot structure which is simple to fabricate and is integratable with low cost silicon photodetectors and transistors. The structure consists of a movable gold coated oxide cantilever for the top mirror and a stationary Au/Ni plated silicon bottom mirror. The fabrication process is single mask level, self aligned, and requires only one grown or deposited layer. Undercutting of the oxide cantilever is carried out by a combination of RIE and anisotropic KOH etching of the (111) silicon substrate. Metallization of the mirrors is provided by thermal evaporation and electroplating. The optical and electrical characteristics of the fabricated devices were studied and show promissing results. A wavelength shift of 120nm with 53V applied bias was demonstrated by one device geometry using 6.27 micrometer air gap. The finesse of the structure was 2.4. Modulation bandwidths ranging from 91KHz to greater than 920KHz were also observed. Theoretical calculations show that if mirror reflectivity, smoothness, and parallelism are improved, a finesse of 30 is attainable. The predictions also suggest that a reduction of the air gap to 1 micrometer results in an increased wavelength tuning range of 175 nm with a CMOS compatible 4.75V.

Patterson, James D.↗

DOE OSTI2024

A Cryogenic readout integrated circuit with analog pile-up and in-Pixel ADC for high frame rate Skipper CCD-in-CMOS Sensors

The Skipper CCD-in-CMOS Parallel Read-Out Circuit V2 (SPROCKET2) is designed to enable high frame rate readout of Skipper CCD-in-CMOS image sensors. The SPROCKET2 pixel is fabricated in a 65 nm CMOS process and occupies a 60$\mu$m $\times$ 60$\mu$m footprint. SPROCKET2 is intended to be heterogeneously integrated with a pixelated Skipper CCD-in-CMOS sensor, such that one readout pixel is connected to a multiplexed array of 16 active image sensor pixels, to match their spatial geometry. Our design benefits from the Skipper CCD-in-CMOS sensor's non-destructive readout capability to achieve exceptionally low noise through multi-sampling and averaging while optimizing for total power consumption. The pixel readout utilizes correlated double sampling to minimize 1/f noise and includes "pile-up" of ten successive samples in the analog domain before digitizing at a rate of 66.7 ksps. Measurement results of in-pixel serial SAR ADC show DNL and INL of ~0. 44 LSB and 0.58 LBS respectively. A large area array of 20,000 SPROCKET2 ADC pixels (multiplexed 1:16 to 320,000 sensor pixels) is currently under test. By reading out data over a 10 Gbps optical link, this pixel design enables a frame rate of $\sim$ 4 kfps for large sensing areas with minimal sensing deadtime. In the highest gain mode, the pixelated ADC has an input-referred resolution of 10$\mu$V with a simulated power consumption of 50$\mu$W. The pixel operates with constant current draw to minimize power-rail crosstalk.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2023

Demonstration of sub-micron UCN position resolution using room-temperature CMOS sensor

High spatial resolution of ultracold neutron (UCN) measurement is of growing interest to UCN experiments such as UCN spectrometers, UCN polarimeters, quantum physics of UCNs, and quantum gravity. Here we utilize physics informed deep learning to enhance the experimental position resolution and to demonstrate sub-micron spatial resolutions for UCN position measurements obtained using a room-temperature CMOS sensor, extending our previous work that demonstrated a position uncertainty of 1.5 microns. We explore the use of the open-source software Allpix Squared to generate experiment-like synthetic hit images with ground-truth position labels. We use physics-informed deep learning by training a fully connected neural network (FCNN) to learn a mapping from input hit images to output hit position. The automated analysis for sub-micron position resolution in UCN detection combined with the fast data rates of current and next generation UCN sources will enable improved precision for future UCN research and applications.

10B nanometer thin film↗

DOE OSTI2023

High-bandwidth density silicon photonic resonators for energy-efficient optical interconnects

The growth of artificial intelligence applications demands ever larger and more complex deep learning models, dominating today's—and tomorrow's—data center and high-performance computing systems. While traditional electronics are failing to keep pace with application demands, silicon photonic (SiPh) interconnects have emerged as a necessary technology to support these systems. SiPh-driven wavelength-division multiplexing (WDM) offers a particularly promising path toward supporting incredibly high-aggregate link bandwidth in a compact and efficient form factor. One of the basic building blocks of these integrated WDM interconnects is the SiPh resonator. Their inherent wavelength selectivity and compact footprint allow for efficient data transmission multiplexed across dozens of carrier wavelengths. Used as add-drop (AD) filters, SiPh resonators are critical to constructing integrated tunable wavelength-selective optical circuit switches as well as for demultiplexing the different carrier wavelengths toward independent wavelength-insensitive photodiodes in a dense wavelength-division multiplexing receiver. Resonators in the all-pass (AP) configuration are widespread as well, allowing for wavelength-selective modulation to drive aggregate link bandwidths far beyond the individual channel data rate. Unlike SiPh Mach–Zehnder modulators (MZM), resonant modulators can be driven using low, complementary metal-oxide-semiconductor drive voltages, allowing for tight co-integration between photonic integrated circuits, fabricated with larger process node technologies, and electronic integrated circuits, designed to exploit the advantages of the latest node. To push toward practical peta-scale interconnects, a comprehensive review of SiPh resonators is required, addressing bottlenecks and design constraints at both the architecture and device levels. We first describe the predominant integrated link architectures and identify their limits. We then discuss the device-level design considerations that can be made for both AD and AP configuration resonators to overcome the system level limits with novel resonator device designs. Analytical models and numerical simulation of resonators are validated by experimental measurement of devices fabricated in a commercial 300-mm foundry, showing a clear path toward volume manufacturing. The demonstrated resonant modulators and filters support the feasibility of increasing the aggregate bandwidth of resonator-driven SiPh interconnects into the peta-scale regime.

42 ENGINEERING↗

NASA NTRS2012

Development of Two Color Fluorescent Imager and Integrated Fluidic System for Nanosatellite Biology Applications

Nanosatellites offer frequent, low-cost space access as secondary payloads on launches of larger conventional satellites. We summarize the payload science and technology of the Microsatellite in-situ Space Technologies (MisST) nanosatellite for conducting automated biological experiments. The payload (two fused 10-cm cubes) includes 1) an integrated fluidics system that maintains organism viability and supports growth and 2) a fixed-focus imager with fluorescence and scattered-light imaging capabilities. The payload monitors temperature, pressure and relative humidity, and actively controls temperature. C. elegans (nematode, 50 m diameter x 1 mm long) was selected as a model organism due to previous space science experience, its completely sequenced genome, size, hardiness, and the variety of strains available. Three strains were chosen: two green GFP-tagged strains and one red tdTomato-tagged strain that label intestinal, nerve, and pharyngeal cells, respectively. The integrated fluidics system includes bioanalytical and reservoir modules. The former consists of four 150 L culture wells and a 4x5 mm imaging zone the latter includes two 8 mL fluid reservoirs for reagent and waste storage. The fluidic system is fabricated using multilayer polymer rapid prototyping: laser cutting, precision machining, die cutting, and pressure-sensitive adhesives it also includes eight solenoid-operated valves and one mini peristaltic pump. Young larval-state (L2) nematodes are loaded in C. elegans Maintenance Media (CeMM) in the bioanalytical module during pre-launch assembly. By the time orbit is established, the worms have grown to sufficient density to be imaged and are fed fresh CeMM. The strains are pumped sequentially into the imaging area, imaged, then pumped into waste. Reagent storage utilizes polymer bags under slight pressure to prevent bubble formation in wells or channels. The optical system images green and red fluorescence bands by excitation with blue (473 nm peak) and amber (587 nm peak) LEDs it achieves 8 m lateral resolution using a CMOS imaging chip (as configured for serial data speeds) or 4 m resolution using USB imaging chips. The imager consists of a modified commercial off-the-shelf CMOS chip camera, amber, blue and white LEDs, as well as a relay lens and dual-band filters to obviate moving parts while supporting both fluorescence wavelengths.

Wu, Diana Terri↗

DOE OSTI2023

A Sub-Electron-Noise Multi-Channel Cryogenic Skipper-CCD Readout ASIC

The MIDNA application specific integrated circuit (ASIC) is a skipper-CCD readout chip fabricated in a 65 nm LP-CMOS process that is capable of working at cryogenic temperatures. The chip integrates four front-end channels that process the skipper-CCD signal and performs differential averaging using a dual slope integration (DSI) circuit. Each readout channel contains a pre-amplifier, a DC restorer, and a dual-slope integrator with chopping capability. The integrator chopping is a key system design element in order to mitigate the effect of low-frequency noise produced by the integrator itself, and it is not often required with standard CCDs. Each channel consumes 4.5 mW of power, occupies 0.156 mm${^2}$ area and has an input referred noise of 2.7${\mu\nu}_{rms}$. It is demonstrated experimentally to achieve sub-electron noise when coupled with a skipper-CCD by means of averaging samples of each pixel. Here, sub-electron noise is shown in three different acquisition approaches. The signal range is 6000 electrons. The readout system achieves 0.2${e^{-}}$ RMS by averaging 1000 samples with MIDNA both at room temperature and at 180 Kelvin.

1/f noise↗

DOE OSTI2020

The Analog Front-end for the LGAD Based Precision Timing Application in CMS ETL

The analog front-end for the Low Gain Avalanche Detector (LGAD) based precision timing application in the CMS Endcap Timing Layer (ETL) has been prototyped in a 65 nm CMOS mini-ASIC named ETROC0. Serving as the very first prototype of ETL readout chip (ETROC), ETROC0 aims to study and demonstrate the performance of the analog frontend, with the goal to achieve 40 to 50 ps time resolution per hit with LGAD (therefore reach about 30ps per track with two detector-layer hits per track). ETROC0 consists of preamplifier and discriminator stages, which amplifies the LGAD signal and generates digital pulses containing time of arrival and time over threshold information. This paper will focus on the design considerations that lead to the ETROC front-end architecture choice, the key design features of the building blocks, the methodology of using the LGAD simulation data to evaluate and optimize the front-end design. The ETROC0 prototype chips have been extensively tested using charge injection and the measured performance agrees well with simulation. The initial beam test results are also presented, with time resolution of around 33 ps observed from the preamplifier waveform analysis and around 41 ps from the discriminator pulses analysis. A subset of ETROC0 chips have also been tested to a total ionizing dose of 100 MRad with X-ray and no performance degradation been observed.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2022

Metaplastic and energy-efficient biocompatible graphene artificial synaptic transistors for enhanced accuracy neuromorphic computing

CMOS-based computing systems that employ the von Neumann architecture are relatively limited when it comes to parallel data storage and processing. In contrast, the human brain is a living computational signal processing unit that operates with extreme parallelism and energy efficiency. Although numerous neuromorphic electronic devices have emerged in the last decade, most of them are rigid or contain materials that are toxic to biological systems. In this work, we report on biocompatible bilayer graphene-based artificial synaptic transistors (BLAST) capable of mimicking synaptic behavior. The BLAST devices leverage a dry ion-selective membrane, enabling long-term potentiation, with ~50 aJ/µm 2 switching energy efficiency, at least an order of magnitude lower than previous reports on two-dimensional material-based artificial synapses. The devices show unique metaplasticity, a useful feature for generalizable deep neural networks, and we demonstrate that metaplastic BLASTs outperform ideal linear synapses in classic image classification tasks. With switching energy well below the 1 fJ energy estimated per biological synapse, the proposed devices are powerful candidates for bio-interfaced online learning, bridging the gap between artificial and biological neural networks.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2025

Design of an 8-channel 40 GS/s 20 mW/Ch waveform sampling ASIC in 65 nm CMOS

One picosecond timing resolution is the entry point to signature based searches relying on secondary/tertiary vertices and particle identification. We describe PSEC5, an 8-channel 40 GS/s waveform-sampling ASIC in TSMC 65 nm process targetting one picosecond resolution at 20 mW power per channel. Each channel consists of four fast and one slow switched capacitor arrays (SCA), allowing for picosecond time resolution combined with a long effective buffer. Each fast SCA is 1.6 ns long and has a nominal sampling rate of 40 GS/s. The slow SCA is 204.8 ns long and samples at 5 GS/s. Recording of the analog data for each channel is triggered by a fast discriminator capable of multiple triggering during the window of the slow SCA. To achieve a large dynamic range, low leakage, and high bandwidth, the SCA sampling switches are implemented as 2.5 V nMOSFETs controlled by 1.2 V shift registers. Stored analog data are digitized by an external ADC at 10 bits or better. Specifications on operational parameters include a 4 GHz analog bandwidth and a dead time of 20 microseconds, corresponding to a 50 kHz readout rate, determined by the choice of the external ADC. PSEC5 has been submitted for fabrication.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

NASA NTRS2012

Downsampling Photodetector Array with Windowing

In a photon counting detector array, each pixel in the array produces an electrical pulse when an incident photon on that pixel is detected. Detection and demodulation of an optical communication signal that modulated the intensity of the optical signal requires counting the number of photon arrivals over a given interval. As the size of photon counting photodetector arrays increases, parallel processing of all the pixels exceeds the resources available in current application-specific integrated circuit (ASIC) and gate array (GA) technology; the desire for a high fill factor in avalanche photodiode (APD) detector arrays also precludes this. Through the use of downsampling and windowing portions of the detector array, the processing is distributed between the ASIC and GA. This allows demodulation of the optical communication signal incident on a large photon counting detector array, as well as providing architecture amenable to algorithmic changes. The detector array readout ASIC functions as a parallel-to-serial converter, serializing the photodetector array output for subsequent processing. Additional downsampling functionality for each pixel is added to this ASIC. Due to the large number of pixels in the array, the readout time of the entire photodetector is greater than the time between photon arrivals; therefore, a downsampling pre-processing step is done in order to increase the time allowed for the readout to occur. Each pixel drives a small counter that is incremented at every detected photon arrival or, equivalently, the charge in a storage capacitor is incremented. At the end of a user-configurable counting period (calculated independently from the ASIC), the counters are sampled and cleared. This downsampled photon count information is then sent one counter word at a time to the GA. For a large array, processing even the downsampled pixel counts exceeds the capabilities of the GA. Windowing of the array, whereby several subsets of pixels are designated for processing, is used to further reduce the computational requirements. The grouping of the designated pixel frame as the photon count information is sent one word at a time to the GA, the aggregation of the pixels in a window can be achieved by selecting only the designated pixel counts from the serial stream of photon counts, thereby obviating the need to store the entire frame of pixel count in the gate array. The pixel count se quence from each window can then be processed, forming lower-rate pixel statistics for each window. By having this processing occur in the GA rather than in the ASIC, future changes to the processing algorithm can be readily implemented. The high-bandwidth requirements of a photon counting array combined with the properties of the optical modulation being detected by the array present a unique problem that has not been addressed by current CCD or CMOS sensor array solutions.

Patawaran, Ferze D.↗

DOE OSTI2024

Developing time-resolved x-ray diffraction diagnostics at the National Ignition Facility (invited)

As part of a program to measure phase transition timescales in materials under dynamic compression, we have designed new x-ray imaging diagnostics to record multiple x-ray diffraction measurements during a single laser-driven experiment. Our design places several ns-gated hybrid CMOS (hCMOS) sensors within a few cm of a laser-driven target. The sensors must be protected from an extremely harsh environment, including debris, electromagnetic pulses, and unconverted laser light. Another key challenge is reducing the x-ray background relative to the faint diffraction signal. Building on the success of our predecessor (Target Diffraction In Situ), we implemented a staged approach to platform development. First, we built a demonstration diagnostic (Gated Diffraction Development Diagnostic) with two hCMOS sensors to confirm we could adequately protect them from the harsh environment and also acquire acceptable diffraction data. This allowed the team to quickly assess the risks and address the most significant challenges. Here, we also collected scientifically useful data during development. Leveraging what we learned, we recently developed a much more ambitious instrument (Flexible Imaging Diffraction Diagnostic for Laser Experiments) that can field up to eight hCMOS sensors in a flexible geometry and participate in back-to-back shots at the National Ignition Facility (NIF). The design also allows for future iterations, such as faster hCMOS sensors and an embedded x-ray streak camera. The enhanced capabilities of the new instrument required a much more complex design, and the unexpected issues encountered on the first few shots at NIF remind us that complexity has consequences. Our progress in addressing these challenges is described herein, as is our current focus on improving data quality by reducing x-ray background and quantifying the uncertainties of our diffraction measurements.

36 MATERIALS SCIENCE↗

DOE OSTI2024

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗