Porous Semiconducting Polymers Enable High;#8208;Performance Electrochemical Transistors
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Huang, Lizhen↗
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Biaxial Tensile Strain Enhances Electron Mobility of Monolayer Transition Metal Dichalcogenides
Strain engineering can modulate the material properties of two-dimensional (2D) sem- iconductors for electronic and optoelectronic applications. Recent theory and experiments have found that uniaxial tensile strain can improve the electron mobility of monolayer MoS 2 , a 2D semiconductor, but the effects of biaxial strain on charge transport are not well-understood in 2D semiconductors. Here, we use biaxial tensile strain on flexible substrates to probe the electron mobility in monolayer WS 2 and MoS 2 transistors. Further, this approach experimentally achieves ~2× higher on-state current and mobility with ~0.3% applied biaxial strain in WS 2 , the highest mobility improvement at the lowest strain reported to date. We also examine the mechanisms behind this improvement through density functional theory simulations, concluding that the enhancement is primarily due to reduced intervalley electron-phonon scattering. These results underscore the role of strain engineering 2D semiconductors for flexible electronics, sensors, integrated circuits, and other opto-electronic applications.
2D materials↗
Inter-Oligomer Interaction Influence on Photoluminescence in Cis-Polyacetylene Semiconductor Materials
Semiconducting conjugated polymers (CPs) are pivotal in advancing organic electronics, offering tunable properties for solar cells and field-effect transistors. Here, we carry out first-principle calculations to study individual cis-polyacetylene (cis-PA) oligomers and their ensembles. The ground electronic structures are obtained using density functional theory (DFT), and excited state dynamics are explored by computing nonadiabatic couplings (NACs) between electronic and nuclear degrees of freedom. We compute the nonradiative relaxation of charge carriers and photoluminescence (PL) using the Redfield theory. Our findings show that electrons relax faster than holes. The ensemble of oligomers shows faster relaxation compared to the single oligomer. The calculated PL spectra show features from both interband and intraband transitions. The ensemble shows broader line widths, redshift of transition energies, and lower intensities compared to the single oligomer. This comparative study suggests that the dispersion forces and orbital hybridizations between chains are the leading contributors to the variation in PL. It provides insights into the fundamental behaviors of CPs and the molecular-level understanding for the design of more efficient optoelectronic devices.
37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
Radiation tolerance studies of the HV-mux GaNFETs for the HL-LHC ATLAS ITk Strip detector
For the High-Luminosity upgrade of the LHC, the current ATLAS inner detector will be replaced with a new silicon charged-particle tracker, the ITk, which consists of the ITk Pixel and the ITk Strip subdetector. The high voltage multiplexing (HV-Mux) GaNFETs are radiation-tolerant transistors that permit switching off high voltage to malfunctioning sensors on the ITk Strip modules. To ensure the reliability of the GaNFETs in the high radiation environment expected at the HL-LHC, a sample of the production batch was exposed to gamma radiation. Finally, the GaNFETs were characterized pre-irradiation and post-irradiation, and monitored during irradiation.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Three dimensional vertically structured electronic devices
In one embodiment, a method of forming a vertical transistor includes forming a layer comprising a semiconductor material above a substrate, defining three dimensional (3D) structures in the layer, forming a second region in at least one vertical sidewall of each 3D structure, and forming an isolation region between the 3D structures. In another embodiment, an apparatus includes at least one vertical transistor, where the at least one vertical transistor includes: a substrate comprising a semiconductor material, an array of 3D structures above the substrate, and an isolation region positioned between the 3D structures. Each 3D structure includes the semiconductor material. Each 3D structure also includes a first region having a first conductivity type and a second region having a second conductivity type, the second region including a portion of at least one vertical sidewall of the 3D structure.
Conway, Adam↗
Strain-insensitive intrinsically stretchable transistors and circuits
An all-elastomer strain engineering approach, which uses patterned elastomer layers with tunable stiffnesses, can be used to create intrinsically stretchable transistor arrays with a device density of 340 transistors cm -2 and strain insensitivity of less than 5% performance variation when stretched to 100% strain. Intrinsically stretchable electronics can form intimate interfaces with the human body, creating devices that could be used to monitor physiological signals without constraining movement. However, mechanical strain invariably leads to the degradation of the electronic properties of the devices. Here we show that strain-insensitive intrinsically stretchable transistor arrays can be created using an all-elastomer strain engineering approach, in which the patterned elastomer layers with tunable stiffnesses are incorporated into the transistor structure. By varying the cross-linking density of the elastomers, areas of increased local stiffness are introduced, reducing strain on the active regions of the devices. This approach can be readily incorporated into existing fabrication processes, and we use it to create arrays with a device density of 340 transistors cm -2 and a strain insensitivity of less than 5% performance variation when stretched to 100% strain. We also show that it can be used to fabricate strain-insensitive circuit elements, including NOR gates, ring oscillators and high-gain amplifiers for the stable monitoring of electrophysiological signals.
42 ENGINEERING↗
Evaluation of the DC bus link capacitors and power transistor modules in the qualification testing of PV inverters
To achieve useful, fair, and cost-effective design qualification and type approval testing for PV inverters, two procedures were developed and demonstrated to evaluate the bus link capacitors and power transistor—and where applicable, its module—for long-term reliability. We evaluate the inverter under simulated use conditions with heat run tests to find the highest operating temperatures reached by these components. The procedures are demonstrated in this study with a 4-kVA class string inverter. The maximum temperature of the DC bus link capacitors was determined to be 76.4°C when the ambient temperature was at the inverter's maximum rated temperature of 60°C with derating occurring. On the other hand, the power transistor module's maximum temperature using the heat sink temperature as the index, 92.6°C, occurred in an ambient of 40.8°C when derating was not occurring. The conditions found for upper temperatures exhibited by these components are, respectively, proposed for implementation in the dry heat and thermal cycling tests in the IEC 62093 “Power conversion equipment for photovoltaic systems – Design qualification testing” international standard draft so that the levels applied in the tests are in proportion to those experienced in the field. Finally as a result, fairer evaluation of inverter reliability is realized.
14 SOLAR ENERGY↗
Additive-Induced Morphology Change of Polymer Film Enables Enhanced Charge Mobility and Faster Organic Electrochemical Transistor Switching
Conjugated polymers (CPs) play an important role in organic electrochemical transistors (OECTs) for bioelectronics and related applications, where they serve as channel materials. Currently, most successful polymers for CPs are re-engineered from traditional CPs by replacing hydrophobic alkyl side chains with hydrophilic ethylene glycol or ionic groups. Frustratingly, the enhanced ion transport often compromises the charge mobility of the original CP. In this work, we present an additive-mediated method to construct a modified poly(3-hexylthiophene) (P3HT) film to enable efficient ion migration. The additive is designed with a cleavable diazo group that releases nitrogen and 2-methoxyethanol, a volatile compound, to alter the P3HT film morphology. OECTs based on the film exhibit improved response times. Interestingly, the process also enhances the crystallinity of P3HT, leading to higher hole mobility compared with pristine P3HT. This study proposes an in situ strategy to achieve the functionality of the OMIEC via morphological regulation, offering a promising route to simultaneously enhance both ion accessibility and charge mobility.
Organic polymers↗
On-Chip Batteries as Distributed Energy Sources in Heterogeneous 2.5D/3D Integrated Circuits
Energy efficiency in digital systems faces challenges due to the constraints imposed by small-scale transistors. Moreover, the growing demand for portable consumer electronics necessitates the use of compact energy sources. To address these challenges, heterogeneous 3D IC technology has emerged as a promising solution for the former. Regarding the latter, we propose the concept of distributed batteries within a heterogeneous 3D IC. This approach involves utilizing multiple smaller batteries with different specifications among different modules of 3D ICs. This approach optimizes performance and overcomes limitations associated with both 3D ICs and conventional power delivery methods. Distributed batteries play a vital role in effectively managing the heat generated by energy sources and modules within a 3D IC. Furthermore, they contribute to achieving a uniform distribution of heat throughout the entire structure, which ultimately ensures the optimal performance of the batteries and modules. The simulation results indicate a 40 percent enhancement in achieving a more even distribution of generated heat. Additionally, the proposed distributed battery techniques improve power delivery, enhance reliability, and enable optimized voltage regulation while improving efficiency. In addition to the primary benefits, alternative configurations of the proposed approach can offer extra energy storage capacity and act as efficient electromagnetic shields, resulting in an impressive reduction of external electromagnetic noises by 60 dB.
47 OTHER INSTRUMENTATION↗
Monostable circuits need power only when they work.
Monostable circuit design satisfies space requirements for minimum power dissipation
SPACECRAFT ELECTRONIC EQUIPMENT↗
Engineering Mechanics Division
Screening methods for metal oxide semiconductor field effect transistors and resistors, impact survival testing of spacecraft electronic parts, and parachute jettisoning from planetary capsules
Source record↗
Low Temperature Reliability of FD-SOI Transistors Abstract #: IRPS_DP118
Fully-depleted silicon on insulator transitors were characterized at low temperatures for performance reliability.
IRPS_DP118 FD-SOI Transistors Low Temperature SOI ↗
Fabrication of a Thermally Isolated and Pre-amplified Transistor Module with Polyimide Micro-wires for Cryogenic Detectors
For use in cryogenic applications such as bolometer and x-ray microcalorimeter arrays, pre-amplifying Junction Field Effect Transistors (JFETs) are often required for the readout electronics. The optimum operating temperature of the JFETs is 130 Kelvin while the cryogenic detectors operate in the milli-Kelvin range. Thus, the JFETs must be heated up but thermally isolated from the surrounding cryogenic instruments. In the past, the thermal isolation was accomplished by suspending the JFETs with low conductance wires such as manganium or stainless steel on a Kevlar support platform [I]. This also achieved electrical connections. However, this assembly required manual soldering work, which could raise a reliability issue for the cryogenic applications. In order to eliminate the manual work, polyimide micro-wires were developed [2]. The wires must be of sufficient length to decrease the heat load and in tension to prevent microphonic noise from vibration of the wires: the polyimide wires were patterned into llS"shaped curves over a thin metal wires such as aluminum, titanium, or niobium. The bilayer of the films were then suspended by etching silicon substrate thus to make freestanding air bridges (enough explanation?). In this paper, we present a method to fabricate micromachined JFET mechanical modules suspended by polyimide Pyraline micro-wires and heated up with built-in aluminum micro-heaters.
Oh, L. H.↗
Towards Prognostics of Power MOSFETs: Accelerated Aging and Precursors of Failure
This paper presents research results dealing with power MOSFETs (metal oxide semiconductor field effect transistor) within the prognostics and health management of electronics. Experimental results are presented for the identification of the on-resistance as a precursor to failure of devices with die-attach degradation as a failure mechanism. Devices are aged under power cycling in order to trigger die-attach damage. In situ measurements of key electrical and thermal parameters are collected throughout the aging process and further used for analysis and computation of the on-resistance parameter. Experimental results show that the devices experience die-attach damage and that the on-resistance captures the degradation process in such a way that it could be used for the development of prognostics algorithms (data-driven or physics-based).
Celaya, Jose R.↗
Recent Advances in GaAs JFETs for Deep Cryogenic Focal Plane Readouts
The progress of Jet Propulsion Laboratory in developing gallium arsenide junction field-effect transistors (GaAs JFETs) for application in infrared readout electronics operating below 10 Kelvin is discussed.
GaAs↗
Ionic‐Liquid Free and Flexible Transistors Made of 2D Material Inks
The development of thin-film transistors (TFTs) using 2D materials is crucial for enabling scalable, low-cost, and flexible electronics. Currently, 2D TFTs with the highest performance have been achieved by using ionic-liquid gating (ILG), a technique suited for proof-of-concept studies. However, ILG suffers from slow switching speeds, temperature sensitivity, poor long-term stability, and integration challenges, making it unsuitable for practical use. Moreover, typical fabrication methods for 2D TFTs involve harsh conditions such as strong acids or high temperatures (>300 °C), limiting integration with flexible substrates. This work provides the first demonstration of an ILG-free, all-2D-material TFT fabricated onto a flexible substrate. Water-based graphene and hexagonal boron nitride (h-BN) inks are printed to deposit the electrodes and dielectric layers, respectively. The MoS 2 channel is produced via supramolecular interfacial self-assembly, yielding uniform, monolayer-rich films transferable to rigid and flexible substrates. The resulting TFTs operate below 3 V, exhibit negligible leakage current, and achieve field-effect mobilities up to 0.46 cm 2 V −1 s −1 (rising to 2.47 cm 2 V −1 s −1 with silver electrodes) measured under ambient conditions, while maintaining excellent mechanical flexibility. This work establishes a low-cost and scalable solution-processable platform for flexible electronics based on 2D materials that match requirements for practical applications.
2D materials↗
Two-Dimensional Palladium Diselenide with Strong In-Plane Optical Anisotropy and High Mobility Grown by Chemical Vapor Deposition
Two-dimensional (2D) palladium diselenide (PdSe 2 ) has strong interlayer coupling and a puckered pentagonal structure, leading to remarkable layer-dependent electronic structures and highly anisotropic in-plane optical and electronic properties. However, the lack of high-quality, 2D PdSe 2 crystals grown by bottom-up approaches limits the study of their exotic properties and practical applications. In this work, chemical vapor deposition growth of highly crystalline few-layer (≥2 layers) PdSe 2 crystals on various substrates is reported. The high quality of the PdSe 2 crystals is confirmed by low-frequency Raman spectroscopy, scanning transmission electron microscopy, and electrical characterization. In addition, strong in-plane optical anisotropy is demonstrated via polarized Raman spectroscopy and second-harmonic generation maps of the PdSe 2 flakes. A theoretical model based on kinetic Wulff construction theory and density functional theory calculations is developed and described the observed evolution of “square=like” shaped PdSe 2 crystals into rhombus due to the higher nucleation barriers for stable attachment on the (1,1) and (1,-1) edges, which results in their slower growth rates. Finally, few-layer PdSe 2 field-effect transistors reveal tunable ambipolar charge carrier conduction with an electron mobility up to ≈294 cm 2 V -1 s -1 , which is comparable to that of exfoliated PdSe 2 , indicating the promise of this anisotropic 2D material for electronics.
36 MATERIALS SCIENCE↗
Improved noise performance from the next-generation buried-channel p-MOSFET SiSeROs
The Single electron Sensitive Read Out (SiSeRO) is a novel on-chip charge detector output stage for charge-coupled device (CCD) image sensors. Developed at MIT Lincoln Laboratory, this technology uses a p-MOSFET transistor with a depleted internal gate beneath the transistor channel. The transistor source-drain current is modulated by the transfer of charge into the internal gate. At Stanford, we have developed a readout module based on the drain current of the on-chip transistor to characterize the device. In our earlier work, we characterized a number of first prototype SiSeROs with the MOSFET transistor channels at the surface layer. An equivalent noise charge (ENC) of around 15 electrons root mean square (RMS) was obtained. In this work, we examine the first buried-channel SiSeRO. Here we have achieved substantially improved noise performance of around 4.5 electrons root mean square (RMS) and a full width half maximum (FWHM) energy resolution of 132 eV at 5.9 keV, for a readout speed of 625 kpixel/s. We also discuss how digital filtering techniques can be used to further improve the SiSeRO noise performance. Additional measurements and device simulations will be essential to further mature the SiSeRO technology. This new device class presents an exciting new technology for the next-generation astronomical X-ray telescopes requiring fast, low-noise, radiation-hard megapixel imagers with moderate spectroscopic resolution.
79 ASTRONOMY AND ASTROPHYSICS↗