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NASA NTRS2008

Technology Developments in Radiation-Hardened Electronics for Space Environments

The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS, Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches. System level applications for the RHESE technology products are discussed.

Keys, Andrew S.↗
NASA NTRS2008

A GPS Receiver for Lunar Missions

Beginning with the launch of the Lunar Reconnaissance Orbiter (LRO) in October of 2008, NASA will once again begin its quest to land humans on the Moon. This effort will require the development of new spacecraft which will safely transport people from the Earth to the Moon and back again, as well as robotic probes tagged with science, re-supply, and communication duties. In addition to the next-generation spacecraft currently under construction, including the Orion capsule, NASA is also investigating and developing cutting edge navigation sensors which will allow for autonomous state estimation in low Earth orbit (LEO) and cislunar space. Such instruments could provide an extra layer of redundancy in avionics systems and reduce the reliance on support and on the Deep Space Network (DSN). One such sensor is the weak-signal Global Positioning System (GPS) receiver "Navigator" being developed at NASA's Goddard Space Flight Center (GSFC). At the heart of the Navigator is a Field Programmable Gate Array (FPGA) based acquisition engine. This engine allows for the rapid acquisition/reacquisition of strong GPS signals, enabling the receiver to quickly recover from outages due to blocked satellites or atmospheric entry. Additionally, the acquisition algorithm provides significantly lower sensitivities than a conventional space-based GPS receiver, permitting it to acquire satellites well above the GPS constellation. This paper assesses the performance of the Navigator receiver based upon three of the major flight regimes of a manned lunar mission: Earth ascent, cislunar navigation, and entry. Representative trajectories for each of these segments were provided by NASA. The Navigator receiver was connected to a Spirent GPS signal generator, to allow for the collection of real-time, hardware-in-the-loop results for each phase of the flight. For each of the flight segments, the Navigator was tested on its ability to acquire and track GPS satellites under the dynamical environment unique to that trajectory.

Bamford, William A.↗
NASA NTRS2007

Risk Reduction for Use of Complex Devices in Space Projects

We present guidel!nes to reduce risk to an acceptable level when using complex devices in space applications. Application to Virtex 4 Field Programmable Gate Array (FPGA) on Express Logistic Carrier (ELC) project is presented.

Berg, Melanie↗
NASA NTRS2008

Considerations for IC and Component Selection for Space Systems

This viewgraph presentation addresses the integrated cycling and component selection technologies for aerospace systems. The topics include: 1) Semiconductors: The Evolution of ICs - Availability and Technology; 2) IC Selection Requirements - three fields of thought, "The Good", "The Bad" and "The Ugly"; 3) Reliability and Radiation; 4) Radiation Perspective-Four methods of selecting ICs for space systems, Guaranteed hardness, historical ground-based radiation data, historical flight usage, and unknown assurance; 5) Understanding Risk, including risk trade space and ASICs and FPGA sample selection criteria.

LaBel, Kenneth A.↗
NASA NTRS2008

Using Pipelined XNOR Logic to Reduce SEU Risks in State Machines

Single-event upsets (SEUs) pose great threats to avionic systems state machine control logic, which are frequently used to control sequence of events and to qualify protocols. The risks of SEUs manifest in two ways: (a) the state machine s state information is changed, causing the state machine to unexpectedly transition to another state; (b) due to the asynchronous nature of SEU, the state machine's state registers become metastable, consequently causing any combinational logic associated with the metastable registers to malfunction temporarily. Effect (a) can be mitigated with methods such as triplemodular redundancy (TMR). However, effect (b) cannot be eliminated and can degrade the effectiveness of any mitigation method of effect (a). Although there is no way to completely eliminate the risk of SEU-induced errors, the risk can be made very small by use of a combination of very fast state-machine logic and error-detection logic. Therefore, one goal of two main elements of the present method is to design the fastest state-machine logic circuitry by basing it on the fastest generic state-machine design, which is that of a one-hot state machine. The other of the two main design elements is to design fast error-detection logic circuitry and to optimize it for implementation in a field-programmable gate array (FPGA) architecture: In the resulting design, the one-hot state machine is fitted with a multiple-input XNOR gate for detection of illegal states. The XNOR gate is implemented with lookup tables and with pipelines for high speed. In this method, the task of designing all the logic must be performed manually because no currently available logic synthesis software tool can produce optimal solutions of design problems of this type. However, some assistance is provided by a script, written for this purpose in the Python language (an object-oriented interpretive computer language) to automatically generate hardware description language (HDL) code from state-transition rules.

Le, Martin↗
NASA NTRS2008

Digital Phase Meter for a Laser Heterodyne Interferometer

The Digital Phase Meter is based on a modified phase-locked loop. When phase alignment between the reference input and the phase-shifted metrological input is achieved, the loop locks and the phase shift of the digital phase shifter equals the phase difference that one seeks to measure. This digital phase meter is being developed for incorporation into a laser heterodyne interferometer in a metrological apparatus, but could also be adapted to other uses. Relative to prior phase meters of similar capability, including digital ones, this digital phase meter is smaller, less complex, and less expensive. The phase meter has been constructed and tested in the form of a field-programmable gate array (FPGA).

Loya, Frank↗
NASA NTRS2008

Replication of Space-Shuttle Computers in FPGAs and ASICs

A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.

Ferguson, Roscoe C.↗
NASA NTRS2009

NASA Tech Briefs, January 2009

Tech Briefs are short announcements of innovations originating from research and development activities of the National Aeronautics and Space Administration. They emphasize information considered likely to be transferable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. Topics covered include: The Radio Frequency Health Node Wireless Sensor System; Effects of Temperature on Polymer/Carbon Chemical Sensors; Small CO2 Sensors Operate at Lower Temperature; Tele-Supervised Adaptive Ocean Sensor Fleet; Synthesis of Submillimeter Radiation for Spectroscopy; 100-GHz Phase Switch/Mixer Containing a Slot-Line Transition; Generating Ka-Band Signals Using an X-Band Vector Modulator; SiC Optically Modulated Field-Effect Transistor; Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions; Metrology System for a Large, Somewhat Flexible Telescope; Economical Implementation of a Filter Engine in an FPGA; Improved Joining of Metal Components to Composite Structures; Machined Titanium Heat-Pipe Wick Structure; Gadolinia-Doped Ceria Cathodes for Electrolysis of CO2; Utilizing Ocean Thermal Energy in a Submarine Robot; Fuel-Cell Power Systems Incorporating Mg-Based H2 Generators; Alternative OTEC Scheme for a Submarine Robot; Sensitive, Rapid Detection of Bacterial Spores; Adenosine Monophosphate-Based Detection of Bacterial Spores; Silicon Microleaks for Inlets of Mass Spectrometers; CGH Figure Testing of Aspherical Mirrors in Cold Vacuums; Series-Coupled Pairs of Silica Microresonators; Precise Stabilization of the Optical Frequency of WGMRs; Formation Flying of Components of a Large Space Telescope; Laser Metrology Heterodyne Phase-Locked Loop; Spatial Modulation Improves Performance in CTIS; High-Performance Algorithm for Solving the Diagnosis Problem; Truncation Depth Rule-of-Thumb for Convolutional Codes; Efficient Method for Optimizing Placement of Sensors.

Source record↗
NASA NTRS2006

Temperature-adaptive Circuits on Reconfigurable Analog Arrays

This paper describes a new reconfigurable analog array (MA) architecture and integrated circuit (IC) used to map analog circuits that can adapt to extreme temperatures under programmable control. Algorithm-driven adaptation takes place on the RAA IC. The algorithms are implemented in a separate Field Programmable Gate Array (FPGA) IC, co-located with the RAA in the extreme temperature environment. The experiments demonstrate circuit adaptation over a wide temperature range, from extremely low temperature of -180 C to high 120 C.

self recovery↗
NASA NTRS2006

Single Event Effects Test Results for Advanced Field Programmable Gate Arrays

Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.

Field Programmable Gate Arrays↗
NASA NTRS2008

25th Space Simulation Conference. Environmental Testing: The Earth-Space Connection

Topics covered include: Methods of Helium Injection and Removal for Heat Transfer Augmentation; The ESA Large Space Simulator Mechanical Ground Support Equipment for Spacecraft Testing; Temperature Stability and Control Requirements for Thermal Vacuum/Thermal Balance Testing of the Aquarius Radiometer; The Liquid Nitrogen System for Chamber A: A Change from Original Forced Flow Design to a Natural Flow (Thermo Siphon) System; Return to Mercury: A Comparison of Solar Simulation and Flight Data for the MESSENGER Spacecraft; Floating Pressure Conversion and Equipment Upgrades of Two 3.5kw, 20k, Helium Refrigerators; Affect of Air Leakage into a Thermal-Vacuum Chamber on Helium Refrigeration Heat Load; Special ISO Class 6 Cleanroom for the Lunar Reconnaissance Orbiter (LRO) Project; A State-of-the-Art Contamination Effects Research and Test Facility Martian Dust Simulator; Cleanroom Design Practices and Their Influence on Particle Counts; Extra Terrestrial Environmental Chamber Design; Contamination Sources Effects Analysis (CSEA) - A Tool to Balance Cost/Schedule While Managing Facility Availability; SES and Acoustics at GSFC; HST Super Lightweight Interchangeable Carrier (SLIC) Static Test; Virtual Shaker Testing: Simulation Technology Improves Vibration Test Performance; Estimating Shock Spectra: Extensions beyond GEVS; Structural Dynamic Analysis of a Spacecraft Multi-DOF Shaker Table; Direct Field Acoustic Testing; Manufacture of Cryoshroud Surfaces for Space Simulation Chambers; The New LOTIS Test Facility; Thermal Vacuum Control Systems Options for Test Facilities; Extremely High Vacuum Chamber for Low Outgassing Processing at NASA Goddard; Precision Cleaning - Path to Premier; The New Anechoic Shielded Chambers Designed for Space and Commercial Applications at LIT; Extraction of Thermal Performance Values from Samples in the Lunar Dust Adhesion Bell Jar; Thermal (Silicon Diode) Data Acquisition System; Aquarius's Instrument Science Data System (ISDS) Automated to Acquire, Process, Trend Data and Produce Radiometric System Assessment Reports; Exhaustive Thresholds and Resistance Checkpoints; Reconfigurable HIL Testing of Earth Satellites; FPGA Control System for the Automated Test of MicroShutters; Ongoing Capabilities and Developments of Re-Entry Plasma Ground Tests at EADS-ASTRIUM; Operationally Responsive Space Standard Bus Battery Thermal Balance Testing and Heat Dissipation Analysis; Galileo - The Serial-Production AIT Challenge; The Space Systems Environmental Test Facility Database (SSETFD), Website Development Status; Simulated Reentry Heating by Torching; Micro-Vibration Measurements on Thermally Loaded Multi-Layer Insulation Samples in Vacuum; High Temperature Life Testing of 80Ni-20Cr Wire in a Simulated Mars Atmosphere for the Sample Analysis at Mars (SAM) Instrument Suit Gas Processing System (GPS) Carbon Dioxide Scrubber; The Planning and Implementation of Test Facility Improvements; and Development of a Silicon Carbide Molecular Beam Nozzle for Simulation Planetary Flybys and Low-Earth Orbit.

Packard, Edward↗
NASA NTRS2009

NASA Tech Briefs, May 2009

Topics covered include: Valve-"Health"-Monitoring System; Microstrip Antenna for Remote Sensing of Soil Moisture and Sea Surface Salinity; Biomedical Wireless Ambulatory Crew Monitor; Wireless Avionics Packet to Support Fault Tolerance for Flight Applications; Aerobot Autonomy Architecture; Submillimeter Confocal Imaging Active Module; Traveling-Wave Maser for 32 GHz; System Synchronizes Recordings from Separated Video Cameras; Piecewise-Planar Parabolic Reflectarray Antenna; Reducing Interference in ATC Voice Communication; EOS MLS Level 1B Data Processing, Version 2.2; Auto-Generated Semantic Processing Services; Geospatial Authentication; Maneuver Automation Software; Event Driven Messaging with Role-Based Subscriptions; Estimating Relative Positions of Outer-Space Structures; Fabricating PFPE Membranes for Capillary Electrophoresis; Linear Actuator Has Long Stroke and High Resolution; Installing a Test Tap on a Metal Battery Case; Fabricating PFPE Membranes for Microfluidic Valves and Pumps; Room-Temperature-Cured Copolymers for Lithium Battery Gel Electrolytes; Catalysts for Efficient Production of Carbon Nanotubes; Amorphous Silk Fibroin Membranes for Separation of CO2; "Zero-Mass" Noninvasive Pressure Transducers; Radial-Electric-Field Piezoelectric Diaphragm Pumps; Ejector-Enhanced, Pulsed, Pressure-Gain Combustor; Suppressing Ghost Diffraction in E-Beam-Written Gratings; Target-Tracking Camera for a Metrology System; Polarimetric Imaging using Two Photoelastic Modulators; Miniature Wide-Angle Lens for Small-Pixel Electronic Camera; Modal Filters for Infrared Interferometry; Mo(3)Sb(7-x)Te(x) for Thermoelectric Power Generation; Two-Dimensional Quantum Model of a Nanotransistor; Scanning Miniature Microscopes without Lenses; Manipulating Neutral Atoms in Chip-Based Magnetic Traps; Expansion Compression Contacts for Thermoelectric Legs; Processing Electromyographic Signals to Recognize Words; Physical Principle for Generation of Randomness; DSN Beowulf Cluster-Based VLBI Correlator; Hybrid NN/SVM Computational System for Optimizing Designs; Criteria for Modeling in LES of Multicomponent Fuel Flow; Computerized Machine for Cutting Space Shuttle Thermal Tiles; Orbiting Depot and Reusable Lander for Lunar Transportation; FPGA-Based Networked Phasemeter for a Heterodyne Interferometer; Aquarius Digital Processing Unit; Three-Dimensional Optical Coherence Tomography; Benchtop Antigen Detection Technique using Nanofiltration and Fluorescent Dyes; Isolation of Precursor Cells from Waste Solid Fat Tissue; Identification of Bacteria and Determination of Biological Indicators; Further Development of Scaffolds for Regeneration of Nerves; Chemically Assisted Photocatalytic Oxidation System; Use of Atomic Oxygen for Increased Water Contact Angles of Various Polymers for Biomedical Applications; Crashworthy Seats Would Afford Superior Protection; Open-Access, Low-Magnetic-Field MRI System for Lung Research; Microfluidic Mixing Technology for a Universal Health Sensor; Microfluidic Extraction of Biomarkers using Water as Solvent; Microwell Arrays for Studying Many Individual Cells; Droplet-Based Production of Liposomes; and Identifying and Inactivating Bacterial Spores

Source record↗
NASA NTRS2009

Wireless Avionics Packet to Support Fault Tolerance for Flight Applications

In this protocol and packet format, data traffic is monitored by all network interfaces to determine the health of transmitter and subsystems. When failures are detected, the network inter face applies its recover y policies to provide continued service despite the presence of faults. The protocol, packet format, and inter face are independent of the data link technology used. The current demonstration system supports both commercial off-the-shelf wireless connections and wired Ethernet connections. Other technologies such as 1553 or serial data links can be used for the network backbone. The Wireless Avionics packet is divided into three parts: a header, a data payload, and a checksum. The header has the following components: magic number, version, quality of service, time to live, sending transceiver, function code, payload length, source Application Data Interface (ADI) address, destination ADI address, sending node address, target node address, and a sequence number. The magic number is used to identify WAV packets, and allows the packet format to be updated in the future. The quality of service field allows routing decisions to be made based on this value and can be used to route critical management data over a dedicated channel. The time to live value is used to discard misrouted packets while the source transceiver is updated at each hop. This information is used to monitor the health of each transceiver in the network. To identify the packet type, the function code is used. Besides having a regular data packet, the system supports diagnostic packets for fault detection and isolation. The payload length specifies the number of data bytes in the payload, and this supports variable-length packets in the network. The source ADI is the address of the originating interface. This can be used by the destination application to identify the originating source of the packet where the address consists of a subnet, subsystem class within the subnet, a subsystem unit, and the local ADI number. The destination ADI is used to route the packet to its ultimate destination. At each hop, the sending interface uses the destination address to determine the next node for the data. The sending node is the node address of the interface that is broadcasting the packet. This field is used to determine the health of the subsystem that is sending the packet. In the case of a packet that traverses several intermediate nodes, it may be the node address of the intermediate node. The target node is the node address of the next hop for the packet. It may be an intermediate node, or the final destination for the packet. The sequence number is used to identify duplicate packets. Because each interface has multiple transceivers, the same packet will appear at both receivers. The sequence number allows the interface to correlate the reception and forward a single, unique packet for additional processing. The subnet field allows data traffic to be partitioned into segregated local networks to support large networks while keeping each subnet at a manageable size. This also keeps the routing table small enough so routing can be done by a simple table lookup in an FPGA device. The subsystem class identifies members of a set of redundant subsystems, and, in a hot standby configuration, all members of the subsystem class will receive the data packets. Only the active subsystem will generate data traffic. Specific units in a class of redundant units can be identified and, if the hot standby configuration is not used, packets will be directed to a specific subsystem unit.

Block, Gary L.↗
NASA NTRS2008

GPS Metric Tracking Unit

As Global Positioning Satellite (GPS) applications become more prevalent for land- and air-based vehicles, GPS applications for space vehicles will also increase. The Applied Technology Directorate of Kennedy Space Center (KSC) has developed a lightweight, low-cost GPS Metric Tracking Unit (GMTU), the first of two steps in developing a lightweight, low-cost Space-Based Tracking and Command Subsystem (STACS) designed to meet Range Safety's link margin and latency requirements for vehicle command and telemetry data. The goals of STACS are to improve Range Safety operations and expand tracking capabilities for space vehicles. STACS will track the vehicle, receive commands, and send telemetry data through the space-based asset, which will dramatically reduce dependence on ground-based assets. The other step was the Low-Cost Tracking and Data Relay Satellite System (TDRSS) Transceiver (LCT2), developed by the Wallops Flight Facility (WFF), which allows the vehicle to communicate with a geosynchronous relay satellite. Although the GMTU and LCT2 were independently implemented and tested, the design collaboration of KSC and WFF engineers allowed GMTU and LCT2 to be integrated into one enclosure, leading to the final STACS. In operation, GMTU needs only a radio frequency (RF) input from a GPS antenna and outputs position and velocity data to the vehicle through a serial or pulse code modulation (PCM) interface. GMTU includes one commercial GPS receiver board and a custom board, the Command and Telemetry Processor (CTP) developed by KSC. The CTP design is based on a field-programmable gate array (FPGA) with embedded processors to support GPS functions.

Source record↗
NASA NTRS2009

NASA Tech Briefs, August 2009

Topics covered include: Aligning a Receiving Antenna Array to Reduce Interference; Collecting Ground Samples for Balloon-Borne Instruments; Tethered Pyrotechnic Apparatus for Acquiring a Ground Sample; Enhanced Video-Oculography System; Joint Carrier-Phase Synchronization and LDPC Decoding; Dual-Polarization, Sideband-Separating, Balanced Receiver for 1.5 THz Modular Battery Charge Controller; Efficient Multiplexer FPGA Block Structures Based on G4FETs; VLSI Microsystem for Rapid Bioinformatic Pattern Recognition; Low-Noise Amplifier for 100 to 180 GHz; Improved Fabrication of Ceramic Matrix Composite/Foam Core Integrated Structures; Inert Welding/Brazing Gas Filters and Dryers; Fabricating Copper Nanotubes by Electrodeposition; Reducing Aerodynamic Drag on Empty Open Cargo Vehicles; Rotary Percussive Auto-Gopher for Deep Drilling and Sampling; More About Reconfigurable Exploratory Robotic Vehicles; Thermostatic Valves Containing Silicone-Oil Actuators; Improving Heat Flux Performance of Flat Surface in Spray-Cooling Systems; Treating Fibrous Insulation to Reduce Thermal Conductivity; Silica-Aerogel Composites Opacified with La(sub0.7)Sr(sub0.3)MnO3; Cyclic Oxidation Behavior of CuCrAl Cold-Sprayed Coatings for Reusable Launch Vehicles; Ceramic Fiber Structures for Cryogenic Load-Bearing Applications; Elastomer Reinforced with Carbon Nanotubes; Biologically Inspired Purification and Dispersion of SWCNTs; A Technique for Adjusting Eigenfrequencies of WGM Resonators; Low-Pressure, Field-Ionizing Mass Spectrometer; Modifying Operating Cycles to Increase Stability in a LITS; Chamber for Simulating Martian and Terrestrial Environments; Algorithm for Detecting a Bright Spot in an Image; Extreme Programming: Maestro Style; Adaptive Behavior for Mobile Robots; Protocol for Communication Networking for Formation Flying; Planning Complex Sequences Using Compressed Representations; and Self-Supervised Learning of Terrain Traversability from Proprioceptive Sensors.

Source record↗
NASA NTRS2009

XML Translator for Interface Descriptions

A computer program defines an XML schema for specifying the interface to a generic FPGA from the perspective of software that will interact with the device. This XML interface description is then translated into header files for C, Verilog, and VHDL. User interface definition input is checked via both the provided XML schema and the translator module to ensure consistency and accuracy. Currently, programming used on both sides of an interface is inconsistent. This makes it hard to find and fix errors. By using a common schema, both sides are forced to use the same structure by using the same framework and toolset. This makes for easy identification of problems, which leads to the ability to formulate a solution. The toolset contains constants that allow a programmer to use each register, and to access each field in the register. Once programming is complete, the translator is run as part of the make process, which ensures that whenever an interface is changed, all of the code that uses the header files describing it is recompiled.

Boroson, Elizabeth R.↗
NASA NTRS2009

Solder Joint Health Monitoring Testbed System

The density and pin count for Field Programmable Gate Arrays (FPGAs) has been increasing, and has exceeded current methods of solder joint inspection, making early detection of failures more problematic. These failures are a concern for both flight safety and maintenance in commercial aviation. Ridgetop Group, Inc. has developed a method for detecting solder joint failures in real time. The NASA Dryden Flight Research Center is developing a set of boards to test this method in ground environmental and accelerated testing as well as flight test on a Dryden F-15 or F-18 research aircraft. In addition to detecting intermittent and total solder joint failures, environmental data on the boards, such as temperature and vibration, will be collected and time-correlated to aircraft state data. This paper details the technical approach involved in the detection process, and describes the design process and products to date for Dryden s FPGA failure detection boards.

Delaney, Michael M.↗
NASA NTRS2009

Solder Joint Health Monitoring Testbed

A method of monitoring the health of selected solder joints, called SJ-BIST, has been developed by Ridgetop Group Inc. under a Small Business Innovative Research (SBIR) contract. The primary goal of this research program is to test and validate this method in a flight environment using realistically seeded faults in selected solder joints. An additional objective is to gather environmental data for future development of physics-based and data-driven prognostics algorithms. A test board is being designed using a Xilinx FPGA. These boards will be tested both in flight and on the ground using a shaker table and an altitude chamber.

Delaney, Michael M.↗