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Pressure responsive switching device exhibits high sensitivity but is extremely rugged and resistant to large amplitude shock and velocity loading. This snap-action, single pole-double throw switch operates over a wide temperature range.
Device consists of hollow tube node of oxidation-resistant sulfonated fluorocarbon polymer. Tube absorbs moisture from air passing across inner and outer surfaces, causing change in polymer conductance. Change is related to change in water content in gas sample.
Electrical measurements complement or replace fast cinematography. Electronic system measures microsecond time intervals between impacts of projectiles on ceramic tiles and fracture tiles. Used in research on ceramics and ceramic-based composite materials such as armor. Hardness and low density of ceramics enable them to disintegrate projectiles more efficiently than metals. Projectile approaches ceramic tile specimen. Penetrating foil squares of triggering device activate display and recording instruments. As ceramic and resistive film break oscilloscope plots increase in electrical resistance of film.
Several demonstrated resonant tunneling devices including oscillators, mixers, multiplexers, and a variable negative resistance are discussed. Techniques of the millimeter/submillimeter regime are also discussed.
Modern electronic systems are vulnerable to transient and they now provide safety critical functions such as full authority digital electronic control (FADEC) units for fly by wire aircraft. Of the traditional suppression technologies available diodes have gained the wider acceptance, however, they lack the current handling capacity to meet existing threat levels. The development of high speed fold back devices where, at a specified voltage, the off state resistance switches to a very low on state one has provided the equivalent to a semiconductor spark gap. The size of the technology enables it to be integrated into connectors of interconnection cables. To illustrate the performance the technology was developed to meet the Lightning Protection requirements for FADEC units within aeroengines. Work was also carried out to study switching behavior with the waveform 5, the 500 us, 10 kA pulse applied to cable assemblies. This test enabled all the switches in a connector to be fired simultaneously.
The effects of irradiating Ga(0.47)In(0.53)As p-i-n junctions with 1 MeV electrons were measured using Deep Level Transient Spectroscopy (DLTS) and both dark and illuminated (1 sun, air mass zero (AM0)) current-voltage (I-V) measurements. The I-V measurements were made over the range 100K less than T less than 350K. Temperature coefficients of the Ga(0.47)In(0.53)As photovoltaic parameters are presented which follow the same general behavior as other solar cell materials (e.g. Si and GaAs). Fits of the dark I-V data to the two term diode equation before irradiation were satisfactory, yielding an estimated band-gap energy of 0.79 eV. The recombination component of the dark current was found to increase linearly with fluence. DLTS detected two radiation-induced defect levels one shallow (E(sub c)-0.10 eV) and one near mid-gap (E(sub c)-0.29 eV), and it is the near mid-gap level which is expected to be the cause of the dark current increase. The radiation-induced degradation of the open circuit voltage is shown to be accurately predicted from the dark I-V measurements. The degradation of the open circuit voltage dominated the radiation response of the photovoltaic parameters while the short circuit current was only moderately degraded. This behavior is qualitatively explained in terms of the base thickness and dopant level. Appropriate changes in the device structure are suggested which should increase the radiation resistance. Isochronal thermal annealing induced recovery in the photovoltaic parameters at approximately 400K, coinciding with an annealing stage of the near mid-gap defect level.
Plasma-enhanced chemical vapor deposition (PECVD) and high-throughput manufacturing techniques for integrating single, aligned carbon nanotubes (CNTs) into novel 3D nanoscale architectures have been developed. First, the PECVD growth technique ensures excellent alignment of the tubes, since the tubes align in the direction of the electric field in the plasma as they are growing. Second, the tubes generated with this technique are all metallic, so their chirality is predetermined, which is important for electronic applications. Third, a wafer-scale manufacturing process was developed that is high-throughput and low-cost, and yet enables the integration of just single, aligned tubes with nanoscale 3D architectures with unprecedented placement accuracy and does not rely on e-beam lithography. Such techniques should lend themselves to the integration of PECVD grown tubes for applications ranging from interconnects, nanoelectromechanical systems (NEMS), sensors, bioprobes, or other 3D electronic devices. Chemically amplified polyhydroxystyrene-resin-based deep UV resists were used in conjunction with excimer laser-based (lambda = 248 nm) step-and-repeat lithography to form Ni catalyst dots = 300 nm in diameter that nucleated single, vertically aligned tubes with high yield using dc PECVD growth. This is the first time such chemically amplified resists have been used, resulting in the nucleation of single, vertically aligned tubes. In addition, novel 3D nanoscale architectures have been created using topdown techniques that integrate single, vertically aligned tubes. These were enabled by implementing techniques that use deep-UV chemically amplified resists for small-feature-size resolution; optical lithography units that allow unprecedented control over layer-to-layer registration; and ICP (inductively coupled plasma) etching techniques that result in near-vertical, high-aspect-ratio, 3D nanoscale architectures, in conjunction with the use of materials that are structurally and chemically compatible with the high-temperature synthesis of the PECVD-grown tubes. The techniques offer a wafer-scale process solution for integrating single PECVD-grown nanotubes into novel architectures that should accelerate their integration in 3D electronics in general. NASA can directly benefit from this technology for its extreme-environment planetary missions. Current Si transistors are inherently more susceptible to high radiation, and do not tolerate extremes in temperature. These novel 3D nanoscale architectures can form the basis for NEMS switches that are inherently less susceptible to radiation or to thermal extremes.
The topics include: Pattern Generator for Bench Test of Digital Boards; 670-GHz Down- and Up-Converting HEMT-Based Mixers; Lidar Electro-Optic Beam Switch with a Liquid Crystal Variable Retarder; Feedback Augmented Sub-Ranging (FASR) Quantizer; Real-Time Distributed Embedded Oscillator Operating Frequency Monitoring; Software Modules for the Proximity-1 Space Link Interleaved Time Synchronization (PITS) Protocol; Description and User Instructions for the Quaternion to Orbit v3 Software; AdapChem; Mars Relay Lander and Orbiter Overflight Profile Estimation; Extended Testability Analysis Tool; Interactive 3D Mars Visualization; Rapid Diagnostics of Onboard Sequences; MER Telemetry Processor; pyam: Python Implementation of YaM; Process for Patterning Indium for Bump Bonding; Archway for Radiation and Micrometeorite Occurrence Resistance; 4D Light Field Imaging System Using Programmable Aperture; Device and Container for Reheating and Sterilization; Radio Frequency Plasma Discharge Lamps for Use as Stable Calibration Light Sources; Membrane Shell Reflector Segment Antenna; High-Speed Transport of Fluid Drops and Solid Particles via Surface Acoustic Waves; Compact Autonomous Hemispheric Vision System; A Distributive, Non-Destructive, Real-Time Approach to Snowpack Monitoring; Wideband Single-Crystal Transducer for Bone Characterization; Numerical Simulation of Rocket Exhaust Interaction With Lunar Soil; Motion Imagery and Robotics Application (MIRA): Standards-Based Robotics; Particle Filtering for Model-Based Anomaly Detection in Sensor Networks; Ka-band Digitally Beamformed Airborne Radar Using SweepSAR Technique; Composite With In Situ Plenums; Multi-Beam Approach for Accelerating Alignment and Calibration of HyspIRI-Like Imaging Spectrometers; JWST Lifting System; Next-Generation Tumbleweed Rover; Pneumatic System for Concentration of Micrometer-Size Lunar Soil.
A set of convenient thermoelectric device solutions have been derived in order to capture a number of factors which are previously only resolved with numerical techniques. The concise conversion efficiency equations derived from governing equations provide intuitive and straight-forward design guidelines. These guidelines allow for better device design without requiring detailed numerical modeling. The analytical modeling accounts for factors such as i) variable temperature boundary conditions, ii) lateral heat transfer, iii) temperature variable material properties, and iv) transient operation. New dimensionless parameters, similar to the figure of merit, are introduced including the device design factor, fin factor, thermal diffusivity factor, and inductance factor. These new device factors allow for the straight-forward description of phenomenon generally only captured with numerical work otherwise. As an example a device design factor of 0.38, which accounts for thermal resistance of the hot and cold shoes, can be used to calculate a conversion efficiency of 2.28 while the ideal conversion efficiency based on figure of merit alone would be 6.15. Likewise an ideal couple with efficiency of 6.15 will be reduced to 5.33 when lateral heat is accounted for with a fin factor of 1.0.
Extremely high sensitivity detectors, such as silicon bolometers are required in many NASA missions for detection of photons from the x-ray to the far infrared regions. Typically, these detectors are cooled to well below the liquid helium (LHe) temperature (4.2 K) to achieve the maximum detection performance. As photoconductors, they are generally operated with a load resistor and a pre-set bias voltage, which is then coupled to the input gate of a source-follower Field Effect Transistor (FET) circuit. It is imperative that the detector system signal to noise performance be limited by the noise of the detector and not by the noise of the external components. The load resistor value is selected to optimize the detector performance. These two criteria tend to be contradictory in that these detectors require load resistors in the hundreds of megaohms, which leads to a higher Johnson noise. Additionally, the physical size of the resistor must be small for device integration as required by such missions as the NASA High Resolution Airborne Wide-Band Camera (HAWC) instrument and the Submillimeter High Angular Resolution Camera (SHARC) for the Caltech Submillimeter Observatory (CSO). We have designed, fabricated and characterized thin film resistors using a CrSi/TiW/Al metal system on optical quality quartz substrates. The resistor values range from 100 megaohms to over 650 megaohms and are Johnson noise limited at LHe temperatures. The resistor film is sputtered with a sheet resistance ranging from 300 ohms to 1600 ohms and the processing sequence developed for these devices allows for chemically fine tuning the sheet resistance in-situ. The wafer fabrication process was of sufficiently high yield (>80%) providing clusters of good resistors for integrated multiple detector channels, a very important feature in the assembly of these two instruments.
A device for producing a stream of vapor for wind tunnel airflow visualization is described. An electrically conductive heating tube is used to resistively heat a vapor producing liquid. The heating and delivery systems are integrated to allow the device to present a small cross section to the air flow, thereby reducing disturbances due to the device. The simplicity of the design allows for inexpensive implementation and construction. The design is readily scaled for use in various wind tunnel applications. The device may also find uses in manufacturing, producing a vapor for deposition on a substrate.
To understand the limitation of maximizing the switching speed of SiC low current discrete devices and high current power modules in hard switching applications, double pulse tests are conducted and the testing results are analyzed. For power modules, the switching speed is generally limited by the parasitics rather than the gate drive capability. For the discrete SiC device, the conventional voltage source gate drive (VSG) is not sufficient to maximize the switching speed even if the external gate resistance is minimized. The limitation of existing current source gate drives (CSG) are analyzed, and a CSG dedicated for SiC discrete devices is proposed, which can provide constant current during the switching transient regardless of the high Miller voltage and large internal gate resistance. Compared with the conventional VSG, the proposed CSG achieves 67% faster turnon time and 50% turn-off time, and 68% reduction in switching loss at full load condition.
Several sets of N-I-P sola cells were fabricated from high resistivity silicon to test the effectiveness of various methods for hardening these devices against radiation. Different substrate materials were used to provide information on the effects of dopant concentration, silicon type, and the presence of oxygen. In some cells, P-type float-zone refined silicon of 800, 8000 and 15,000 omega-cm resistivity was used to provide a basis for studying resistivity and purity effects. In other cells, N-type silicon (approximately 800 omega-cm) was used to allow a comparison of dopant type. Oxygen-rich, crucible-grown, silicon (approximately 100 omega-cm, p-type) will provide information on purity effects and defect gettering. Lithium was introduced into different types of silicon to determine if mobile ions can reduce radiation induced defects in high resistivity material. Thin cells (2 mil) were fabricated to study the effects of cell thickness and carrier injection on radiation damage. The electrical characteristics of the different sets of cells were measured, analyzed, and compared prior to shipment of the cells to NASA/Lewis for irradiation.
A particular phenomenon of the SNS Josephson junction was investigated; i.e., control by a current entering the normal region and leaving through one of the superconducting regions. The effect of the control current on the junction was found to be dependent upon the ration of the resistances of the two halves of the N layer. A low frequency, lumped, nonlinear model was proposed to describe the electrical characteristics of the device, and a method was developed to plot the dynamic junction resistance as a function of junction current. The effective thermal noise temperature of the sample was determined. Small signal linearized analysis of the device suggests its use as an impedance transformer, although geometric limitations must be overcome. Linear approximation indicates that it is reciprocal and no power gain is possible. It is felt that, with suitable metallurgical and geometrical improvements, the device has promise to become a superconducting transistor.
System-on-a-chip (SOC) processes are under intense development for high-speed, high frequency transceiver circuitry. As frequencies, data rates, and circuit complexity increases, the need for substrates that enable high-speed analog operation, low-power digital circuitry, and excellent isolation between devices becomes increasingly critical. SiGe/Si modulation doped field effect transistors (MODFETs) with high carrier mobilities are currently under development to meet the active RF device needs. However, as the substrate normally used is Si, the low-to-modest substrate resistivity causes large losses in the passive elements required for a complete high frequency circuit. These losses are projected to become increasingly troublesome as device frequencies progress to the Ku-band (12 - 18 GHz) and beyond. Sapphire is an excellent substrate for high frequency SOC designs because it supports excellent both active and passive RF device performance, as well as low-power digital operations. We are developing high electron mobility SiGe/Si transistor structures on r-plane sapphire, using either in-situ grown n-MODFET structures or ion-implanted high electron mobility transistor (HEMT) structures. Advantages of the MODFET structures include high electron mobilities at all temperatures (relative to ion-implanted HEMT structures), with mobility continuously improving to cryogenic temperatures. We have measured electron mobilities over 1,200 and 13,000 sq cm/V-sec at room temperature and 0.25 K, respectively in MODFET structures. The electron carrier densities were 1.6 and 1.33 x 10(exp 12)/sq cm at room and liquid helium temperature, respectively, denoting excellent carrier confinement. Using this technique, we have observed electron mobilities as high as 900 sq cm/V-sec at room temperature at a carrier density of 1.3 x 10(exp 12)/sq cm. The temperature dependence of mobility for both the MODFET and HEMT structures provides insights into the mechanisms that allow for enhanced electron mobility as well as the processes that limit mobility, and will be presented.
We will present our results on tapered-edge-geometry SNS weak link fabricated from c-axis oriented base-, counterelectrode and normal layers using a variety of processing conditions. To date, we have employed a variety of different normal materials (Co-doped YBCO, Y-doped PBCO, Ca-doped PBCO). We have been examining the junction fabrication process in detail and we will present our methods. In particular, we have been examining both epitaxial and non-epitaxial milling mask overlayers and we will present a comparison of both methods. These devices behave similar to the expectations of the resisively shunted junction model and conventional SNS proximity effect models but with some differences which will be discussed. We will present the detailed systematics of our junctions including device parameters versus temperature, rf and dc magnetic response for the various processing conditions.
An amplifier developed under a Small Business Innovation Research (SBIR) contract will have applications for both satellite and terrestrial communications. This power amplifier uses an innovative series bias arrangement of active devices to achieve over 40-percent efficiency at Ka-band frequencies with an output power of 0.66 W. The amplifier is fabricated on a 2.0- by 3.8-square millimeter chip through the use of Monolithic Microwave Integrated Circuit (MMIC) technology, and it uses state-of-the-art, Pseudomorphic High-Electron-Mobility Transistor (PHEMT) devices. Although the performance of the MMIC chip depends on these high-performance devices, the real innovations here are a unique series bias scheme, which results in a high-voltage chip supply, and careful design of the on-chip planar output stage combiner. This design concept has ramifications beyond the chip itself because it opens up the possibility of operation directly from a satellite power bus (usually 28 V) without a dc-dc converter. This will dramatically increase the overall system efficiency. Conventional microwave power amplifier designs utilize many devices all connected in parallel from the bias supply. This results in a low-bias voltage, typically 5 V, and a high bias current. With this configuration, substantial I(sup 2) R losses (current squared times resistance) may arise in the system bias-distribution network. By placing the devices in a series bias configuration, the total current is reduced, leading to reduced distribution losses. Careful design of the on-chip planar output stage power combiner is also important in minimizing losses. Using these concepts, a two-stage amplifier was designed for operation at 33 GHz and fabricated in a standard MMIC foundry process with 0.20-m PHEMT devices. Using a 20-V bias supply, the amplifier achieved efficiencies of over 40 percent with an output power of 0.66 W and a 16-dB gain over a 2-GHz bandwidth centered at 33 GHz. With a 28-V bias, a power level of 1.1 W was achieved with a 12-dB gain and a 36-percent efficiency. This represents the best reported combination of power and efficiency at this frequency. In addition to delivering excellent power and gain, this Ka-band MMIC power amplifier has an efficiency that is 10 percent greater than existing designs. The unique design offers an excellent match for spacecraft applications since the amplifier supply voltage is closely matched to the typical value of spacecraft bus voltage. These amplifiers may be used alone in applications of 1 W or less, or several may be combined or used in an array to produce moderate power, Ka-band transmitters with minimal power combining and less thermal stress owing to the combination of excellent efficiency and power output. The higher voltage operation of this design may also save mass and power because the dc-dc power converter is replaced with a simpler voltage regulator.
Waterflow tests of a heritage Space Shuttle Main Engine pogo suppressor were performed to experimentally quantify the resistance and inertance provided by the suppressor. Measurements of dynamic pressure and flow rate in response to pulsing flow were made throughout the test loop. A unique system identification methodology combined all sensor measurements with a one-dimensional perturbational flow model of the complete water flow loop to spatially translate physical measurements to the device under test. Multiple techniques were then employed to extract the effective resistance and inertance for the pogo suppressor. Parameters such as steady flow rate, perturbational flow rate magnitude, and pulse frequency were investigated to assess their influence on the behavior of the pogo suppressor dynamic response. These results support validation of the RS-25 pogo suppressor performance for use on the Space Launch System Core Stage.