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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 397 records · Page 22

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NASA NTRS1977

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Gosney, W. M.↗

NASA NTRS1978

Binary to binary coded decimal converter

A binary coded input signal is converted to a binary coded decimal signal having N decades by employing N four bit shift registers. The bits of the input signal are sequentially supplied, in order, to the least significant position of the register for the units decade, with the most significant bit of the input signal being applied to the units register first. Each of the registers includes a right shift-parallel load mode control input terminal. In response to the sum of the values stored in each register and the binary value 0011 being less than the binary value 1000, the mode control input terminal is activated to shift the register contents one bit to the right. In response to the sum being greater than 1000, the mode control input terminal is activated to load the sum into the register.

Miller, A. J.↗

NASA NTRS1978

Optimal sampling and quantization of synthetic aperture radar signals

Some theoretical and experimental results on optimal sampling and quantization of synthetic aperture radar (SAR) signals are presented. It includes a description of a derived theoretical relationship between the pixel signal to noise ratio of processed SAR images and the number of quantization bits per sampled signal, assuming homogeneous extended targets. With this relationship known, a solution may be realized for the problem of optimal allocation of a fixed data bit-volume (for specified surface area and resolution criterion) between the number of samples and the number of bits per sample. The results indicate that to achieve the best possible image quality for a fixed bit rate and a given resolution criterion, one should quantize individual samples coarsely and thereby maximize the number of multiple looks. The theoretical results are then compared with simulation results obtained by processing aircraft SAR data.

Wu, C.↗

NASA NTRS1978

A wide bandwidth CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. CCD shift register memories (8K bit) were used to construct a feasibility model 128 K-bit buffer memory system. Serial data that can have rates between 150 kHz and 4.0 MHz can be stored in 4K-bit, randomly-accessible memory blocks. Peak power dissipation during a data transfer is less than 7 W, while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. System expansion to accommodate parallel inputs or a greater number of memory blocks can be performed in a modular fashion. Since the control logic does not increase proportionally to increase in memory capacity, the power requirements per bit of storage can be reduced significantly in a larger system.

Siemens, K.↗

NASA NTRS1978

An iterative algorithm for decoding block codes transmitted over a memoryless channel

An algorithm was developed which optimally decodes a block code for minimum probability of symbol error in an iterative manner. The initial estimate is made by looking at each bit independently and is improved by considering bits related to it through the parity check equations. The dependent bits are considered in order of interesting probability of error. Since the computation proceeds in a systematic way with the bits having the greatest effect being used first, the algorithm approaches the optimum estimate after only a fraction of the parity check equations were used.

Greenberger, H. J.↗

NASA NTRS1980

Shuttle orbiter Ku-band radar/communications system design evaluation. Ku band bent-pipe channel performance evaluation

Because of difficulties with the bit detector of the SPA mode 1 channel 3 input port, a new bit synchronizer was required. The two prime candidate designs are described and analyzed. The selected design is a modification of one which utilizes a phase frequency detector to track the received data clock frequency and a mid-bit transition point sample detector to generate a bit timing error (phase error) signal to control the relative phase between the local clock and the local data stream. The model used to calculate the effects of cable attenuation and rise time degradation is discussed.

Holmes, J. K.↗

NASA NTRS1980

The Jet Propulsion Laboratory/California Institute of Technology block 2 VLBI processor

A multistation, multichannel cross correlation processor using the 250 k bit to 4 M bit recording format is discussed. The design is modular, using bit sliced microprocessors to perform the routine calculations for phase and delay on a per station basis, as well as for fractional bit shift correction and Fourier transformation of the correlation coefficients on a per baseline basis.

Rogtad, D. H.↗

NASA NTRS1979

Minimizing pattern effects in semiconductor lasers at high rate pulse modulation

This paper deals with analytical and experimental work related to modulation of a semiconductor laser used in high bit rate communication. The approach is based upon minimizing the charge storage effect by a proper choice of the area of the modulating pulses and the bias current. The concept of using additional current pulses to probe for variations in electron density between pulses is investigated. The primary limitation on bit rate is found to be the ability to generate laser drive pulses free of ringing or similar transients. This and the 300 ps pulsewidth, an experimental constraint, limit the bit rate to about 1 Gbit/s. However, by using this approach it appears that bit rates considerably higher than 2 Gbits/s could be reached with sufficiently accurate control of drive pulse shape. It is found that the laser bias and the current pulse area had to be controlled within 1 percent and 10 percent, respectively.

Torphammar, P.↗

NASA NTRS1980

A generalized formulation of minimum shift keying modulation

The modulator structure consisting of a single-input two-output sequential transducer whose output sequences control the modulated signal in the manner s(t) = x(i)p(t) + y(i)q(t) is considered. Here, iT is less than or equal to t, which is less than iT + T, where T is the modulation bit duration and where x(i) and y(i) take values in /+1, -1, 0/. The behavior of a sequential transducer is characterized by means of a 'trellis'. It is shown that, provided only that the 'carriers' p(t) and q(t) have the same energy in every bit interval, the optimum demodulator for the additive white Gaussian noise channel need process the received signal over only two bit intervals in making each data bit decision. It is demonstrated that particular choices of the sequential transducer yield differential minimum shift keying and differential staggered quadriphase shift keying. Possible generalizations of this approach are discussed.

Massey, J. L.↗

NASA NTRS1981

Video framerate, resolution and grayscale tradeoffs for undersea telemanipulator

The product of Frame Rate (F) in frames per second, Resolution (R) in total pixels and grayscale in bits (G) equals the transmission band rate in bits per second. Thus for a fixed channel capacity there are tradeoffs between F, R and G in the actual sampling of the picture for a particular manual control task in the present case remote undersea manipulation. A manipulator was used in the MASTER/SLAVE mode to study these tradeoffs. Images were systematically degraded from 28 frames per second, 128 x 128 pixels and 16 levels (4 bits) grayscale, with various FRG combinations constructed from a real-time digitized (charge-injection) video camera. It was found that frame rate, resolution and grayscale could be independently reduced without preventing the operator from accomplishing his/her task. Threshold points were found beyond which degradation would prevent any successful performance. A general conclusion is that a well trained operator can perform familiar remote manipulator tasks with a considerably degrade picture, down to 50 K bits/ sec.

Ranadive, V.↗

NASA NTRS1981

Performance of quadrature overlapped raised-cosine modulation over nonlinear satellite channels

This paper considers the performance evaluation of Staggered Quadrature Overlapped Raised Cosine (SQORC) signal transmission through wideband nonlinear satellite channels in the presence of uplink and downlink additive Gaussian noise. Expressions for the bit error rate are derived for a general transponder model with AM-AM and AM-PM conversion. It is shown that the bit error rate of SQORC is one-half of the sum of the bit error rate of MSK at 2/3 of the uplink signal-to-noise ratio and the bit error rate of Quadriphase Phase-Shift Keying QPSK at 4/3 of the uplink signal-to-noise ratio, whereas the spectrum of SQROC is the product of MSK and QPSK spectra. Numerical results are presented for a transponder which is modelled as a hard limiter.

Divsalar, D.↗

NASA NTRS1983

Massively parallel processor computer

An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array is described. It comprises a large number (e.g., 16,384 in a 128 x 128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered parallel data, including spatial translation by shifting or sliding of bits vertically or horizontally to neighboring processing elements.

Fung, L. W.↗

NASA NTRS1985

Digital Ratiometer

Small, low-cost comparator with 24-bit-precision yields ratio signal from pair of analog or digital input signals. Arithmetic logic chips (bit-slice) sample two 24-bit analog-to-digital converters approximately once every millisecond and accumulate them in two 24-bit registers. Approach readily modified to arbitrary precision.

Beer, R.↗

NASA NTRS1984

Navier-Stokes Simulation of Homogeneous Turbulence on the CYBER 205

A computer code which solves the Navier-Stokes equations for three dimensional, time-dependent, homogenous turbulence has been written for the CYBER 205. The code has options for both 64-bit and 32-bit arithmetic. With 32-bit computation, mesh sizes up to 64 (3) are contained within core of a 2 million 64-bit word memory. Computer speed timing runs were made for various vector lengths up to 6144. With this code, speeds a little over 100 Mflops have been achieved on a 2-pipe CYBER 205. Several problems encountered in the coding are discussed.

Wu, C. T.↗

NASA NTRS1984

Postprocessing for the UCLA climate model

Postprocessing programs written to analyze the results of a general circulation model are described. The model history data is interpolated to pressure surfaces, converted from 64-bit Cyber words to 32 bit IBM words, and transferred to tape for further analysis. The time average program reads the interpolation output tape and produces 15-day time averages. The model outputs a very detailed record for selected grid points. This data is sent to a tape in Cyber full words. The conversion program changes the format of the tape from 64 bit Cyber words to 32 bit IBM words, processing a month of data at a time. The grid-point history sorting program inputs the converted grid point history tape and sorts it by time. The end product is a tape with a time history of each field for every point. After the PBP data has been stored, it can be plotted. The plotting package is flexible, and allows the choice of fields and grid points. The one-dimensional fields are plotted as functions of time, and a daily summary is also produced. For the two-dimensional fields, time-height cross sections and daily summaries are produced. The model plotting package produces plots for all fields on the time average and pressure tapes. These plots include world maps, polar projections, zonal means, vectors, streamlines, and latitude-height plots.

Abeles, J.↗

NASA NTRS1986

Optimum Cyclic Redundancy Codes for Noisy Channels

Capabilities and limitations of cyclic redundancy codes (CRC's) for detecting transmission errors in data sent over relatively noisy channels (e.g., voice-grade telephone lines or very-high-density storage media) discussed in 16-page report. Due to prevalent use of bytes in multiples of 8 bits data transmission, report primarily concerned with cases in which both block length and number of redundant bits (check bits for use in error detection) included in each block are multiples of 8 bits.

Posner, E. C.↗

NASA NTRS1984

The undetected error probability for shortened hamming codes

Hamming or shortened Hamming codes are widely used for error detection in data communications. For example, the CCITT (International Telegraph and Telephone Consultative Committee) recommendation X.25 for packet-switched data networks adopts a distance-4 cyclic Hamming code with 16 parity-check bits for error detection. The natural length of this code is n = 2(15)-1 = 32,767. In practice the length of a data packet is no more than a few thousand bits which is much shorter than the natural length of the code. Consequently, a shortened version of thecode is used. Often the length of a data packet varies, say from a few hundred bits to a few thousand bits, hence the code must be shortened by various degrees. Shortening affects the performance of the code. The error-detection performance of shortened Hamming codes, particularly the codes obtained from the distance-4 Hamming codes adopted by CCITT recommendation X.25, is investigated. A method for computing the probability of an undetected error is presented.

Costello, D. J., Jr.↗

NASA NTRS1984

A high-speed digital signal processor for atmospheric radar, part 7.3A

The Model SP-320 device is a monolithic realization of a complex general purpose signal processor, incorporating such features as a 32-bit ALU, a 16-bit x 16-bit combinatorial multiplier, and a 16-bit barrel shifter. The SP-320 is designed to operate as a slave processor to a host general purpose computer in applications such as coherent integration of a radar return signal in multiple ranges, or dedicated FFT processing. Presently available is an I/O module conforming to the Intel Multichannel interface standard; other I/O modules will be designed to meet specific user requirements. The main processor board includes input and output FIFO (First In First Out) memories, both with depths of 4096 W, to permit asynchronous operation between the source of data and the host computer. This design permits burst data rates in excess of 5 MW/s.

Brosnahan, J. W.↗