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At least 397 records · Page 22

All sources NASA NTRS DOE OSTI

NASA NTRS1995

RISC Processors and High Performance Computing

In this tutorial, we will discuss top five current RISC microprocessors: The IBM Power2, which is used in the IBM RS6000/590 workstation and in the IBM SP2 parallel supercomputer, the DEC Alpha, which is in the DEC Alpha workstation and in the Cray T3D; the MIPS R8000, which is used in the SGI Power Challenge; the HP PA-RISC 7100, which is used in the HP 700 series workstations and in the Convex Exemplar; and the Cray proprietary processor, which is used in the new Cray J916. The architecture of these microprocessors will first be presented. The effective performance of these processors will then be compared, both by citing standard benchmarks and also in the context of implementing a real applications. In the process, different programming models such as data parallel (CM Fortran and HPF) and message passing (PVM and MPI) will be introduced and compared. The latest NAS Parallel Benchmark (NPB) absolute performance and performance per dollar figures will be presented. The next generation of the NP13 will also be described. The tutorial will conclude with a discussion of general trends in the field of high performance computing, including likely future developments in hardware and software technology, and the relative roles of vector supercomputers tightly coupled parallel computers, and clusters of workstations. This tutorial will provide a unique cross-machine comparison not available elsewhere.

Saini, Subhash↗

NASA NTRS1995

High Performance Parallel Computational Nanotechnology

At a recent press conference, NASA Administrator Dan Goldin encouraged NASA Ames Research Center to take a lead role in promoting research and development of advanced, high-performance computer technology, including nanotechnology. Manufacturers of leading-edge microprocessors currently perform large-scale simulations in the design and verification of semiconductor devices and microprocessors. Recently, the need for this intensive simulation and modeling analysis has greatly increased, due in part to the ever-increasing complexity of these devices, as well as the lessons of experiences such as the Pentium fiasco. Simulation, modeling, testing, and validation will be even more important for designing molecular computers because of the complex specification of millions of atoms, thousands of assembly steps, as well as the simulation and modeling needed to ensure reliable, robust and efficient fabrication of the molecular devices. The software for this capacity does not exist today, but it can be extrapolated from the software currently used in molecular modeling for other applications: semi-empirical methods, ab initio methods, self-consistent field methods, Hartree-Fock methods, molecular mechanics; and simulation methods for diamondoid structures. In as much as it seems clear that the application of such methods in nanotechnology will require powerful, highly powerful systems, this talk will discuss techniques and issues for performing these types of computations on parallel systems. We will describe system design issues (memory, I/O, mass storage, operating system requirements, special user interface issues, interconnects, bandwidths, and programming languages) involved in parallel methods for scalable classical, semiclassical, quantum, molecular mechanics, and continuum models; molecular nanotechnology computer-aided designs (NanoCAD) techniques; visualization using virtual reality techniques of structural models and assembly sequences; software required to control mini robotic manipulators for positional control; scalable numerical algorithms for reliability, verifications and testability. There appears no fundamental obstacle to simulating molecular compilers and molecular computers on high performance parallel computers, just as the Boeing 777 was simulated on a computer before manufacturing it.

Saini, Subhash↗

NASA NTRS2003

Experimental Verification of Electric Drive Technologies Based on Artificial Intelligence Tools

A laboratory implementation of a fuzzy logic-tracking controller using a low cost Motorola MC68HC11E9 microprocessor is described in this report. The objective is to design the most optimal yet practical controller that can be implemented and marketed, and which gives respectable performance, even when the system loads, inertia and parameters are varying. A distinguishing feature of this work is the by-product goal of developing a marketable, simple, functional and low cost controller. Additionally, real-time nonlinearities are not ignored, and a mathematical model is not required. A number of components have been designed, built and tested individually, and in various combinations of hardware and software segments. These components have been integrated with a brushless motor to constitute the drive system. A microprocessor-based FLC is incorporated to provide robust speed and position control. Design objectives that are difficult to express mathematically can be easily incorporated in a fuzzy logic-based controller by linguistic information (in the form of fuzzy IF-THEN rules). The theory and design are tested in the laboratory using a hardware setup. Several test cases have been conducted to confirm the effectiveness of the proposed controller. The results indicate excellent tracking performance for both speed and position trajectories. For the purpose of comparison, a bang-bang controller has been tested. The fuzzy logic controller performs significantly better than the traditional bang-bang controller. The bang-bang controller has been shown to be relatively inaccurate and lacking in robustness. Description of the implementation hardware system is also given.

Rubaai, Ahmed↗

NASA NTRS2003

Field Programmable Gate Array for Implementation of Redundant Advanced Digital Feedback Control

The goal of this effort was to develop a digital motor controller using field programmable gate arrays (FPGAs). This is a more rugged approach than a conventional microprocessor digital controller. FPGAs typically have higher radiation (rad) tolerance than both the microprocessor and memory required for a conventional digital controller. Furthermore, FPGAs can typically operate at higher speeds. (While speed is usually not an issue for motor controllers, it can be for other system controllers.) Other than motor power, only a 3.3-V digital power supply was used in the controller; no analog bias supplies were used. Since most of the circuit was implemented in the FPGA, no additional parts were needed other than the power transistors to drive the motor. The benefits that FPGAs provide over conventional designs-lower power and fewer parts-allow for smaller packaging and reduced weight and cost.

King, K. D.↗

NASA NTRS2004

Single Event Effects in Highly Scaled Devices for Space Applications

This paper discusses single-event upset (SEU) in memories and microprocessors that are the "drivers" of highly scaled commercial integrated circuits. Despite the decrease in critical charge that occurs for highly scaled CMOS devices, recent test data has shown that SEU rates are actually somewhat lower for scaled devices compared to older devices with larger feature size. Hard errors, which are increasingly important for memories, are discussed along with conventional soft errors. Functional errors in memories and microprocessors are particularly significant, and tend to dominate the response of highly scaled devices from an application standpoint. Predictions for future devices are made using the Semiconductor Industry Roadmap along with recent modeling and radiation test results.

microelectronics↗

NASA NTRS1988

Programmable control means for providing safe and controlled medication infusion

An implantable programmable infusion pump (IPIP) is disclosed and generally includes: a fluid reservoir filled with selected medication; a pump for causing a precise volumetric dosage of medication to be withdrawn from the reservoir and delivered to the appropriate site within the body; and, a control means for actuating the pump in a safe and programmable manner. The control means includes a microprocessor, a permanent memory containing a series of fixed software instructions, and a memory for storing prescription schedules, dosage limits and other data. The microprocessor actuates the pump in accordance with programmable prescription parameters and dosage limits stored in the memory. A communication link allows the control means to be remotely programmed. The control means incorporates a running integral dosage limit and other safety features which prevent an inadvertent or intentional medication overdose. The control means also monitors the pump and fluid handling system and provides an alert if any improper or potentially unsafe operation is detected.

Fischell, Robert E.↗

NASA NTRS1985

Portable instant display and analysis reflectance spectrometer

A portable analysis spectrometer (10) for field mineral identification is coupled to a microprocessor (11) and memory (12) through a bus (13) and A/D converter (14) to display (16) a spectrum of reflected radiation in a band selected by an adjustable band spectrometer (20) and filter (23). A detector array (21) provides output signals at spaced frequencies within the selected spectrometer band which are simultaneously converted to digital form for display. The spectrum displayed is compared with a collection of spectra for known minerals. That collection is stored in memory and selectively displayed with the measured spectrum, or stored in a separate portfolio. In either case, visual comparison is made. Alternatively, the microprocessor may use an algorithm to make the comparisons in search for the best match of the measured spectrum with one of the stored spectra to identify the mineral in the target area.

Goetz, Alexander F. H.↗

NASA NTRS1997

Portable light source unit for simulating fires having an adjustable aperture

A portable, hand held light source unit is employed to check operation of fire detectors, such as hydrogen fire detectors. The unit emits radiation in a narrow band of wavelengths which are generated by the type of fire to be tested, but not by other light sources such as the sun or incandescent lamps. The unit can test fire detectors at different distances, and of different sensitivities. The intensity of the radiation emitted by the unit is adjustable for this purpose by means of a rotatable disk having a plurality of different sized apertures for selective placement between the light source and an output lens. The disk can also be rotated to a calibration position which causes a microprocessor circuit in the unit to initiate a calibration procedure. During this procedure, the lamp intensity is measured by a photodetector contained within the unit, and the microprocessor adjusts the lamp current to insure that its intensity remains within a preset range of values. A green and a red LED are mounted on the unit which indicate to an operator whether the calibration is successful, as well as the condition of the unit's battery power supply.

Youngquist, Robert C.↗

NASA NTRS2009

Lithium Ion Battery (LIB) Charger: Spacesuit Battery Charger Design with 2-Fault Tolerance to Catastrophic Hazards

Charger design that is 2-fault tolerant to catastrophic has been achieved for the Spacesuit Li-ion Battery with key features. Power supply control circuit and 2 microprocessors independently control against overcharge. 3 microprocessor control against undercharge (false positive: Go for EVA) conditions. 2 independent channels provide functional redundancy. Capable of charge balancing cell banks in series. Cell manufacturing and performance uniformity is excellent with both designs. Once a few outliers are removed, LV cells are slightly more uniform than MoliJ cells. If cell balance feature of charger is ever invoked, it will be an indication of a significant degradation issue, not a nominal condition.

Darcy, Eric↗

NASA NTRS2009

Airborne Antenna System for Minimum-Cycle-Slip GPS Reception

A system that includes a Global Positioning System (GPS) antenna and associated apparatus for keeping the antenna aimed upward has been developed for use aboard a remote-sensing-survey airplane. The purpose served by the system is to enable minimum- cycle-slip reception of GPS signals used in precise computation of the trajectory of the airplane, without having to restrict the airplane to maneuvers that increase the flight time needed to perform a survey. Cycle slip signifies loss of continuous track of the phase of a signal. Minimum-cycle-slip reception is desirable because maintaining constant track of the phase of the carrier signal from each available GPS satellite is necessary for surveying to centimeter or subcentimeter precision. Even a loss of signal for as short a time as a nanosecond can cause cycle slip. Cycle slips degrade the quality and precision of survey data acquired during a flight. The two principal causes of cycle slip are weakness of signals and multipath propagation. Heretofore, it has been standard practice to mount a GPS antenna rigidly on top of an airplane, and the radiation pattern of the antenna is typically hemispherical, so that all GPS satellites above the horizon are viewed by the antenna during level flight. When the airplane must be banked for a turn or other maneuver, the reception hemisphere becomes correspondingly tilted; hence, the antenna no longer views satellites that may still be above the Earth horizon but are now below the equatorial plane of the tilted reception hemisphere. Moreover, part of the reception hemisphere (typically, on the inside of a turn) becomes pointed toward ground, with a consequent increase in received noise and, therefore, degradation of GPS measurements. To minimize the likelihood of loss of signal and cycle slip, bank angles of remote-sensing survey airplanes have generally been limited to 10 or less, resulting in skidding or slipping uncoordinated turns. An airplane must be banked in order to make a coordinated turn. For small-radius, short-time coordinated turns, it is necessary to employ banks as steep as 45 , and turns involving such banks are times and for confining airplanes as closely as possible to areas to be surveyed. The idea underlying the design is that if the antenna can be kept properly aimed, then the incidence of cycle slips caused by loss or weakness of signals can be minimized. The system includes an articulating GPS antenna and associated electronic circuitry mounted under a radome atop an airplane. The electronic circuitry includes a microprocessor-based interface-circuit-and-data-translation module. The system receives data on the current attitude of the airplane from the inertial navigation system of the airplane. The microprocessor decodes the attitude data and uses them to compute commands for the GPS-antenna-articulating mechanism to tilt the antenna, relative to the airplane, in opposition to the roll or bank of the airplane to keep the antenna pointed toward the zenith. The system was tested aboard the hurricane- hunting airplane of the National Oceanic and Atmospheric Administration (NOAA) [see figure] during an 11-hour flight to observe the landfall of Hurricane Bret in late summer of 1999. No bank-angle restrictions were imposed during the flight. Post-flight analysis of the GPS trajectory data revealed that no cycle slip had occurred.considered normal maneuvers. These steep banks are highly desirable for minimizing flight

Wright, C. Wayne↗

NASA NTRS2009

Radiation-hardened fast acquisition/weak signal tracking system and method

A global positioning system (GPS) receiver and method of acquiring and tracking GPS signals comprises an antenna adapted to receive GPS signals; an analog radio frequency device operatively connected to the antenna and adapted to convert the GPS signals from an analog format to a digital format; a plurality of GPS signal tracking correlators operatively connected to the analog RF device; a GPS signal acquisition component operatively connected to the analog RF device and the plurality of GPS signal tracking correlators, wherein the GPS signal acquisition component is adapted to calculate a maximum vector on a databit correlation grid; and a microprocessor operatively connected to the plurality of GPS signal tracking correlators and the GPS signal acquisition component, wherein the microprocessor is adapted to compare the maximum vector with a predetermined correlation threshold to allow the GPS signal to be fully acquired and tracked.

Winternitz, Luke↗

NASA NTRS2012

High-Altitude MMIC Sounding Radiometer for the Global Hawk Unmanned Aerial Vehicle

Microwave imaging radiometers operating in the 50-183 GHz range for retrieving atmospheric temperature and water vapor profiles from airborne platforms have been limited in the spatial scales of atmospheric structures that are resolved not because of antenna aperture size, but because of high receiver noise masking the small variations that occur on small spatial scales. Atmospheric variability on short spatial and temporal scales (second/ km scale) is completely unresolved by existing microwave profilers. The solution was to integrate JPL-designed, high-frequency, low-noise-amplifier (LNA) technology into the High-Altitude MMIC Sounding Radiometer (HAMSR), which is an airborne microwave sounding radiometer, to lower the system noise by an order of magnitude to enable the instrument to resolve atmospheric variability on small spatial and temporal scales. HAMSR has eight sounding channels near the 60-GHz oxygen line complex, ten channels near the 118.75-GHz oxygen line, and seven channels near the 183.31-GHz water vapor line. The HAMSR receiver system consists of three heterodyne spectrometers covering the three bands. The antenna system consists of two back-to-back reflectors that rotate together at a programmable scan rate via a stepper motor. A single full rotation includes the swath below the aircraft followed by observations of ambient (roughly 0 C in flight) and heated (70 C) blackbody calibration targets located at the top of the rotation. A field-programmable gate array (FPGA) is used to read the digitized radiometer counts and receive the reflector position from the scan motor encoder, which are then sent to a microprocessor and packed into data files. The microprocessor additionally reads telemetry data from 40 onboard housekeeping channels (containing instrument temperatures), and receives packets from an onboard navigation unit, which provides GPS time and position as well as independent attitude information (e.g., heading, roll, pitch, and yaw). The raw data files are accessed through an Ethernet port. The HAMSR data rate is relatively low at 75 kbps, allowing for real-time access over the Global Hawk high-data-rate downlink. Once on the ground, the raw data are unpacked and processed through two levels of processing. The Level 1 product contains geo-located, time-stamped, calibrated brightness temperatures for the Earth scan. These data are then input to a lD variational retrieval algorithm to produce temperature, water vapor, and cloud liquid water profiles, as well as several derived products such as potential temperature and relative humidity.

Brown, Shannon T.↗

NASA NTRS2012

Flexible Architecture for FPGAs in Embedded Systems

Commonly, field-programmable gate arrays (FPGAs) being developed in cPCI embedded systems include the bus interface in the FPGA. This complicates the development because the interface is complicated and requires a lot of development time and FPGA resources. In addition, flight qualification requires a substantial amount of time be devoted to just this interface. Another complication of putting the cPCI interface into the FPGA being developed is that configuration information loaded into the device by the cPCI microprocessor is lost when a new bit file is loaded, requiring cumbersome operations to return the system to an operational state. Finally, SRAM-based FPGAs are typically programmed via specialized cables and software, with programming files being loaded either directly into the FPGA, or into PROM devices. This can be cumbersome when doing FPGA development in an embedded environment, and does not have an easy path to flight. Currently, FPGAs used in space applications are usually programmed via multiple space-qualified PROM devices that are physically large and require extra circuitry (typically including a separate one-time programmable FPGA) to enable them to be used for this application. This technology adds a cPCI interface device with a simple, flexible, high-performance backend interface supporting multiple backend FPGAs. It includes a mechanism for programming the FPGAs directly via the microprocessor in the embedded system, eliminating specialized hardware, software, and PROM devices and their associated circuitry. It has a direct path to flight, and no extra hardware and minimal software are required to support reprogramming in flight. The device added is currently a small FPGA, but an advantage of this technology is that the design of the device does not change, regardless of the application in which it is being used. This means that it needs to be qualified for flight only once, and is suitable for one-time programmable devices or an application specific integrated circuit (ASIC). An application programming interface (API) further reduces the development time needed to use the interface device in a system.

Clark, Duane I.↗

NASA NTRS2016

Advanced EVA Suit Camera System Development Project

The National Aeronautics and Space Administration (NASA) at the Johnson Space Center (JSC) is developing a new extra-vehicular activity (EVA) suit known as the Advanced EVA Z2 Suit. All of the improvements to the EVA Suit provide the opportunity to update the technology of the video imagery. My summer internship project involved improving the video streaming capabilities of the cameras that will be used on the Z2 Suit for data acquisition. To accomplish this, I familiarized myself with the architecture of the camera that is currently being tested to be able to make improvements on the design. Because there is a lot of benefit to saving space, power, and weight on the EVA suit, my job was to use Altium Design to start designing a much smaller and simplified interface board for the camera's microprocessor and external components. This involved checking datasheets of various components and checking signal connections to ensure that this architecture could be used for both the Z2 suit and potentially other future projects. The Orion spacecraft is a specific project that may benefit from this condensed camera interface design. The camera's physical placement on the suit also needed to be determined and tested so that image resolution can be maximized. Many of the options of the camera placement may be tested along with other future suit testing. There are multiple teams that work on different parts of the suit, so the camera's placement could directly affect their research or design. For this reason, a big part of my project was initiating contact with other branches and setting up multiple meetings to learn more about the pros and cons of the potential camera placements we are analyzing. Collaboration with the multiple teams working on the Advanced EVA Z2 Suit is absolutely necessary and these comparisons will be used as further progress is made for the overall suit design. This prototype will not be finished in time for the scheduled Z2 Suit testing, so my time was also spent creating a case for the original interface board that is already being used. This design is being done by use of Creo 2. Due to time constraints, I may not be able to complete the 3-D printing portion of this design, but I was able to use my knowledge of the interface board and Altium Design to help in the task. As a side project, I assisted another intern in selecting and programming a microprocessor to control linear actuators. These linear actuators will be used to move various increments of polyethylene for controlled radiation testing. For this, we began the software portion of the project using the Arduino's coding environment to control an Arduino Due and H-Bridge components. Along with the obvious learning of computer programs such as Altium Design and Creo 2, I also acquired more skills with networking and collaborating with others, being able to multi-task because of responsibilities to work on various projects, and how to set realistic goals in the work place. Like many internship projects, this project will be continued and improved, so I also had the chance to improve my organization and communication skills as I documented all of my meetings and research. As a result of my internship at JSC, I desire to continue a career with NASA, whether that be through another internship or possibly a co-op. I am excited to return to my university and continue my education in electrical engineering because of all of my experiences at JSC.

Mock, Kyla↗

NASA NTRS1993

Computer Electromagnetics and Supercomputer Architecture

The dramatic increase in performance over the last decade for microporcessor computations is compared with that for the supercomputer computations. This performance, the projected performance, and a number of other issues such as cost and the inherent pysical limitations in curent supercomputer technology have naturally led to parallel supercomputers and ensemble of interconnected microprocessors.

Electromagnetics Microprocessors Computers↗

NASA NTRS2023

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗

DOE OSTI2018

High-precision control of tracked field robots in the presence of unknown traction coefficients

Accurate steering through crop rows that avoids crop damage is one of the most important tasks for agricultural robots utilized in various field operations, such as monitoring, mechanical weeding, or spraying. In practice, varying soil conditions can result in off-track navigation due to unknown traction coefficients so that it can cause crop damage. To address this problem, this work presents the development, application, and experimental results of a real-time receding horizon estimation and control (RHEC) framework applied to a fully autonomous mobile robotic platform to increase its steering accuracy. Recent advances in cheap and fast microprocessors, as well as advances in solution methods for nonlinear optimization problems, have made nonlinear receding horizon control (RHC) and receding horizon estimation (RHE) methods suitable for field robots that require high-frequency (milliseconds) updates. A real-time RHEC framework is developed and applied to a fully autonomous mobile robotic platform designed by the authors for in-field phenotyping applications in sorghum fields. Nonlinear RHE is used to estimate constrained states and parameters, and nonlinear RHC is designed based on an adaptive system model that contains time-varying parameters. The capabilities of the real-time RHEC framework are verified experimentally, and the results show an accurate tracking performance on a bumpy and wet soil field. Finally, the mean values of the Euclidean error and required computation time of the RHEC framework are equal to 0.0423 m and 0.88 ms, respectively.

42 ENGINEERING↗

DOE OSTI2018

Porting DMRG++ Scientific Application to OpenPOWER

With the rapidly changing microprocessor designs and architectural diversity (multi-cores, many-cores, accelerators) for the next generation HPC systems, scientific applications must adapt to the hardware, to exploit the different types of parallelism and resources available in the architecture. To get the benefit of all the in-node hardware threads, it is important to use a single programming model to map and coordinate the available work to the different heterogeneous execution units in the node (e.g., multi-core hardware threads (latency optimized), accelerators (bandwidth optimized), etc.).Our goal is to show that we can manage the node complexity of these systems by using OpenMP for in-node parallelization by exploiting different “programming styles” supported by OpenMP 4.5 to program CPU cores and accelerators. Finding out the suitable programming-style (e.g., SPMD style, multi-level tasks, accelerator programming, nested parallelism, or a combination of these) using the latest features of OpenMP to maximize performance and achieve performance portability across heterogeneous and homogeneous systems is still an open research problem.We developed a mini-application, Kronecker Product (KP), from the original DMRG++ application (sparse matrix algebra) computational motif to experiment with different OpenMP programming styles on an OpenPOWER architecture and present their results in this paper.

Chatterjee, Ronnie↗