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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 397 records · Page 22
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NASA NTRS2012

Design and Operation of the Planetary In-Situ Capillary Electrophoresis System (PISCES)

The PISCES instrument is a portable, miniature, modular instrument designed to analyze organic molecular signatures of life. PISCES uses microcapillary electrophoresis (μCE) with laser-induced fluorescence detection (LIFD) to analyze fluorescently-labeled analytes prepared on a multi-layer microfluidic chip. As a modular instrument composed of five independently functioning units, each module can be easily detached from the system and used for subsystem testing in different environments, e.g. low temperature. The pneumatic module contains mechanical and electrical components necessary to control pneumatically-actuated valves for on-chip sample processing. A prototype LabVIEW program and two custom printed circuit boards (PCBs) operate the pneumatics module using an Arduino microcontroller, and a tentative design for the module’s housing has been developed. The high-voltage module contains circuitry required to apply varying electrical potentials to the electrophoretic channel of the microdevice. Work is currently being done to design the circuit and PCB for this module in collaboration with our SBIR partners at Los Gatos Research. The optical electronics module contains the spectrometer, laser, and laser power supply. The mounting components for the electronics and housing for the module have been designed, assembled, and tested. The optical module contains optical components to focus the laser to a 20μm spot in the center of the electrophoretic channel.The housing for this module has been designed and assembled with the aligned optical components inside.

Willis, Peter A.↗
NASA NTRS1978

Indium antimonide infrared CCD linear imaging arrays with on-chip preprocessing

A description is presented of the fabrication of a new InSb CCD chip based on an improved process which eliminates the limitations inherent with the earlier techniques. This process includes planar junction formation and an aluminum and SiO2 material system which is amenable to state-of-the-art chemical and plasma delineation techniques. Further, the new chip integrates for the first time in monolithic format InSb IR detectors with an InSb CCD. The reported experiments represent the first operation of an InSb infrared CCD array. In addition to fuller characterization of the 20-element charge-coupled infrared imaging device, several factors which influence device performance are currently being addressed. These include surface state density, the CCD output circuit, and storage time (dark current).

Thom, R. D.↗
NASA NTRS2013

NASA Tech Briefs, January 2013

Topics include: Single-Photon-Sensitive HgCdTe Avalanche Photodiode Detector; Surface-Enhanced Raman Scattering Using Silica Whispering-Gallery Mode Resonators; 3D Hail Size Distribution Interpolation/Extrapolation Algorithm; Color-Changing Sensors for Detecting the Presence of Hypergolic Fuels; Artificial Intelligence Software for Assessing Postural Stability; Transformers: Shape-Changing Space Systems Built with Robotic Textiles; Fibrillar Adhesive for Climbing Robots; Using Pre-Melted Phase Change Material to Keep Payloads in Space Warm for Hours without Power; Development of a Centrifugal Technique for the Microbial Bioburden Analysis of Freon (CFC-11); Microwave Sinterator Freeform Additive Construction System (MS-FACS); DSP/FPGA Design for a High-Speed Programmable S-Band Space Transceiver; On-Chip Power-Combining for High-Power Schottky Diode-Based Frequency Multipliers; FPGA Vision Data Architecture; Memory Circuit Fault Simulator; Ultra-Compact Transputer-Based Controller for High-Level, Multi-Axis Coordination; Regolith Advanced Surface Systems Operations Robot Excavator; Magnetically Actuated Seal; Hybrid Electrostatic/Flextensional Mirror for Lightweight, Large-Aperture, and Cryogenic Space Telescopes; System for Contributing and Discovering Derived Mission and Science Data; Remote Viewer for Maritime Robotics Software; Stackfile Database; Reachability Maps for In Situ Operations; JPL Space Telecommunications Radio System Operating Environment; RFI-SIM: RFI Simulation Package; ION Configuration Editor; Dtest Testing Software; IMPaCT - Integration of Missions, Programs, and Core Technologies; Integrated Systems Health Management (ISHM) Toolkit; Wind-Driven Wireless Networked System of Mobile Sensors for Mars Exploration; In Situ Solid Particle Generator; Analysis of the Effects of Streamwise Lift Distribution on Sonic Boom Signature; Rad-Tolerant, Thermally Stable, High-Speed Fiber-Optic Network for Harsh Environments; Towed Subsurface Optical Communications Buoy; High-Collection-Efficiency Fluorescence Detection Cell; Ultra-Compact, Superconducting Spectrometer-on-a-Chip at Submillimeter Wavelengths; UV Resonant Raman Spectrometer with Multi-Line Laser Excitation; Medicine Delivery Device with Integrated Sterilization and Detection; Ionospheric Simulation System for Satellite Observations and Global Assimilative Model Experiments - ISOGAME; Airborne Tomographic Swath Ice Sounding Processing System; flexplan: Mission Planning System for the Lunar Reconnaissance Orbiter; Estimating Torque Imparted on Spacecraft Using Telemetry; PowderSim: Lagrangian Discrete and Mesh-Free Continuum Simulation Code for Cohesive Soils; Multiple-Frame Detection of Subpixel Targets in Thermal Image Sequences; Metric Learning to Enhance Hyperspectral Image Segmentation; Basic Operational Robotics Instructional System; Sheet Membrane Spacesuit Water Membrane Evaporator; Advanced Materials and Manufacturing for Low-Cost, High-Performance Liquid Rocket Combustion Chambers; Motor Qualification for Long-Duration Mars Missions.

Source record↗
NASA NTRS2006

Using Existing NASA Satellites as Orbiting Testbeds to Accelerate Technology Infusion into Future Missions

One of the shared problems for new space mission developers is that it is extremely difficult to infuse new technology into new missions unless that technology has been flight validated. Therefore, the issue is that new technology is required to fly on a successful mission for flight validation. We have been experimenting with new technology on existing satellites by retrofitting primarily the flight software while the missions are on-orbit to experiment with new operations concepts. Experiments have been using Earth Observing 1 (EO-1), which is part of the New Millennium Program at NASA. EO-1 finished its prime mission one year after its launch on November 21,2000. From November 21,2001 until the present, EO-1 has been used in parallel with additional science data gathering to test out various sensor web concepts. Similarly, the Cosmic Hot Interstellar Plasma Spectrometer (CHIPS) satellite was also a one year mission flown by the University of Berkeley, sponsored by NASA and whose prime mission ended August 30,2005. Presently, CHIPS is being used to experiment with a seamless space to ground interface by installing Core Flight System (cFS), a "plug-and-play" architecture developed by the Flight Software Branch at NASA/GSFC on top of the existing space-to-ground Internet Protocol (IP) interface that CHIPS implemented. For example, one targeted experiment is to connect CHIPS to a rover via this interface and the Internet, and trigger autonomous actions on CHIPS, the rover or both. Thus far, having satellites to experiment with new concepts has turned out to be an inexpensive way to infuse new technology for future missions. Relevant experiences thus far and future plans will be discussed in this presentation.

Mandl, Daniel↗
NASA NTRS2010

SEU/SET Tolerant Phase-Locked Loops

The phase-locked loop (PLL) is an old and widely used circuit for frequency and phase demodulation, carrier and clock recovery, and frequency synthesis [1]. Its implementations range from discrete components to fully integrated circuits and even to firmware or software. Often the PLL is a highly critical component of a system, as for example when it is used to derive the on-chip clock, but as of this writing no definitive single-event upset (SET)/single-event transient (SET) tolerant PLL circuit has been described. This chapter hopes to rectify that situation, at least in regard to PLLs that are used to generate clocks. Older literature on fault-tolerant PLLs deals with detection of a hard failure, which is recovered by replacement, repair, or manual restart of discrete component systems. Several patents exist along these lines (6349391, 6272647, and 7089442). A newer approach is to harden the parts of a PLL system, to one degree or another, such as by using a voltage-based charge pump or a triple modular redundant (TMR) voted voltage-controlled oscillator (VCO). A more comprehensive approach is to harden by triplication and voting (TMR) all the digital pieces (primarily the divider) of a frequency synthesis PLL, but this still leaves room for errors in the VCO and the loop filter. Instead of hardening or voting pieces of a system, such as a frequency synthesis system (i.e., clock multiplier), we will show how the entire system can be voted. There are two main ways of doing this, each with advantages and drawbacks. We will show how each has advantages in certain areas, depending on the lock acquisition and tracking characteristics of the PLL. Because of this dependency on PLL characteristics, we will briefly revisit the theory of PLLs. But first we will describe the characteristics of voters and their correct application, as some literature does not follow the voting procedure that guarantees elimination of errors. Additionally, we will find that voting clocks is a bit trickier than voting data where an infallible clock is assumed. It is our job here to produce (or recover) that assumed infallible clock!

Shuler, Robert L., Jr.↗
NASA NTRS1968

Small, low power analog-to-digital converter

A small, low-power, high-speed, 8-bit analog-to-digital converter using silicon chip integrated circuits is suitable for use in airborne test data systems. The successive approximation method of analog-to-digital conversion is used to generate the digital output.

Dunn, R. D.↗
NASA NTRS1980

Study of sample drilling techniques for Mars sample return missions

To demonstrate the feasibility of acquiring various surface samples for a Mars sample return mission the following tasks were performed: (1) design of a Mars rover-mounted drill system capable of acquiring crystalline rock cores; prediction of performance, mass, and power requirements for various size systems, and the generation of engineering drawings; (2) performance of simulated permafrost coring tests using a residual Apollo lunar surface drill, (3) design of a rock breaker system which can be used to produce small samples of rock chips from rocks which are too large to return to Earth, but too small to be cored with the Rover-mounted drill; (4)design of sample containers for the selected regolith cores, rock cores, and small particulate or rock samples; and (5) design of sample handling and transfer techniques which will be required through all phase of sample acquisition, processing, and stowage on-board the Earth return vehicle. A preliminary design of a light-weight Rover-mounted sampling scoop was also developed.

Mitchell, D. C.↗
NASA NTRS1990

VLSI Reed-Solomon Encoder With Interleaver

Size, weight, and susceptibility to burst errors reduced. Encoding system built on single very-large-scale integrated (VLSI) circuit chip produces (255,223) Reed-Solomon (RS) code with programmable interleaving up to depth of 5. (225,223) RS encoder includes new remainder-and-interleaver unit providing programmable interleaving of code words. Remainder-and-interleaver unit contains shift registers and modulo-2 adders. Signals on "turn" and "no-turn" lines control depth of interleaving. Based on E. R. Berlekamp's bit-serial multiplication algorithm for (225,223) RS encoder over Galois Field (2 to the 8th power).

Hsu, In-Shek↗
NASA NTRS1989

A programmable image compression system

A programmable image compression system which has the necessary flexibility to address diverse imaging needs is described. It can compress and expand single frame video images (monochrome or color) as well as documents and graphics (black and white or color) for archival or transmission applications. Through software control, the compression mode can be set for lossless or controlled quality coding; the image size and bit depth can be varied; and the image source and destination devices can be readily changed. Despite the large combination of image data types, image sources, and algorithms, the system provides a simple consistent interface to the programmer. This system (OPTIPAC) is based on the TITMS320C25 digital signal processing (DSP) chip and has been implemented as a co-processor board for an IBM PC-AT compatible computer. The underlying philosophy can readily be applied to different hardware platforms. By using multiple DSP chips or incorporating algorithm specific chips, the compression and expansion times can be significantly reduced to meet performance requirements.

Farrelle, Paul M.↗
NASA NTRS1991

High resolution decoding of Multi-Anode Microchannel Array detectors

The Multi-Anode Microchannel Array (MAMA) is a photon counting detector which utilizes a photocathode for photon to electron conversion, a microchannel plate (MCP) for signal amplification and a proximity focused anode array for position sensitivity. The detector electronics decode the position of an event through coincidence discrimination. The decoding algorithm which associates a given event with the appropriate pixel is determined by the geometry of the array. A new algorithm incorporated into a CMOS Application Specific Integrated Circuit (ASIC) decoder which improves the pixel spatial resolution is described. The new algorithm does not degrade the detector throughput and does not require any modifications to the detector tube. The standard MAMA detector has a pixel size of 25 x 25 square microns, but with the new decoder circuit the pixel size is reduced to 12.5 x 12.5 square microns. We have built the first set of decode electronics utilizing the new ASIC chips and report here on the first imaging tests of this system.

Kasle, David B.↗
NASA NTRS2001

Updated Electronic Testbed System

As we continue to advance in exploring space frontiers, technology must also advance. The need for faster data recovery and data processing is crucial. In this, the less equipment used, and lighter that equipment is, the better. Because integrated circuits become more sensitive in high altitude, experimental verification and quantification is required. The Center for Applied Radiation Research (CARR) at Prairie View A&M University was awarded a grant by NASA to participate in the NASA ER-2 Flight Program, the APEX balloon flight program, and the Student Launch Program. These programs are to test anomalous errors in integrated circuits due to single event effects (SEE). CARR had already begun experiments characterizing the SEE behavior of high speed and high density SRAM's. The research center built a error testing system using a PC-104 computer unit, an Iomega Zip drive for storage, a test board with the components under test, and a latchup detection and reset unit. A test program was written to continuously monitor a stored data pattern in the SRAM chip and record errors. The devices under test were eight 4Mbit memory chips totaling 4Mbytes of memory. CARR was successful at obtaining data using the Electronic TestBed System (EBS) in various NASA ER-2 test flights. These series of high altitude flights of up to 70,000 feet, were effective at yielding the conditions which single event effects usually occur. However, the data received from the series of flights indicated one error per twenty-four hours. Because flight test time is very expensive, the initial design proved not to be cost effective. The need for orders of magnitude with more memory became essential. Therefore, a project which could test more memory within a given time was created. The goal of this project was not only to test more memory within a given time, but also to have a system with a faster processing speed, and which used less peripherals. This paper will describe procedures used to build an updated Electronic Testbed System.

Brewer, Kevin L.↗
NASA NTRS2008

Performance of High Temperature Operational Amplifier, Type LM2904WH, under Extreme Temperatures

Operation of electronic parts and circuits under extreme temperatures is anticipated in NASA space exploration missions as well as terrestrial applications. Exposure of electronics to extreme temperatures and wide-range thermal swings greatly affects their performance via induced changes in the semiconductor material properties, packaging and interconnects, or due to incompatibility issues between interfaces that result from thermal expansion/contraction mismatch. Electronics that are designed to withstand operation and perform efficiently in extreme temperatures would mitigate risks for failure due to thermal stresses and, therefore, improve system reliability. In addition, they contribute to reducing system size and weight, simplifying its design, and reducing development cost through the elimination of otherwise required thermal control elements for proper ambient operation. A large DC voltage gain (100 dB) operational amplifier with a maximum junction temperature of 150 C was recently introduced by STMicroelectronics [1]. This LM2904WH chip comes in a plastic package and is designed specifically for automotive and industrial control systems. It operates from a single power supply over a wide range of voltages, and it consists of two independent, high gain, internally frequency compensated operational amplifiers. Table I shows some of the device manufacturer s specifications.

Patterson, Richard↗
NASA NTRS1972

Development of chip passivated monolithic complementary MISFET circuits with beam leads

The results are presented of a program to demonstrate the processes for fabricating complementary MISFET beam-leaded circuits, which, potentially, are comparable in quality to available bipolar beam-lead chips that use silicon nitride passivation in conjunction with a platinum-titanium-gold metal system. Materials and techniques, different from the bipolar case, were used in order to be more compatible with the special requirements of fully passivated complementary MISFET devices. Two types of circuits were designed and fabricated, a D-flip-flop and a three-input NOR/NAND gate. Fifty beam-leaded chips of each type were constructed. A quality and reliability assurance program was performed to identify failure mechanisms. Sample tests and inspections (including destructive) were developed to measure the physical characteristics of the circuits.

Ragonese, L. J.↗
NASA NTRS1987

A VLSI single chip (255,223) Reed-Solomon encoder with interleaver

A single-chip implementation of a Reed-Solomon encoder with interleaving capability is described. The code used was adapted by the CCSDS (Consulative Committee on Space Data Systems). It forms the outer code of the NASA standard concatenated coding system which includes a convolutional inner code of rate 1/2 and constraint length 7. The architecture, leading to this single VLSI chip design, makes use of a bit-serial finite field multiplication algorithm due to E.R. Berlekamp.

Hsu, I. S.↗
NASA NTRS1986

A one-megapixel image acquisition and processing system for solar oscillation studies

The 1-Mpixel image acquisition and processing system that has been installed at the Mt. Wilson observatory as part of the development effort for the NASA/ESA Solar Oscillations Imager Experiment of the projected Heliospheric Observatory mission is discussed. The system encompasses a high speed CCD camera with a 1024 x 1024-pixel virtual phase chip array, yielding a readout rate of about 800,000 pixels/sec; this allows the entire Mpixel array to be read out in just over 1 sec. The camera is interfaced with a floating point array processor that integrates several successive exposures from the CCD camera and differences selected pairs of integrated images. The system is currently being used to record and difference narrowband images of the sun.

Rhodes, Edward J., Jr.↗
NASA NTRS2004

Qualification and Reliability for MEMS and IC Packages

Advanced IC electronic packages are moving toward miniaturization from two key different approaches, front and back-end processes, each with their own challenges. Successful use of more of the back-end process front-end, e.g. microelectromechanical systems (MEMS) Wafer Level Package (WLP), enable reducing size and cost. Use of direct flip chip die is the most efficient approach if and when the issues of know good die and board/assembly are resolved. Wafer level package solve the issue of known good die by enabling package test, but it has its own limitation, e.g., the I/O limitation, additional cost, and reliability. From the back-end approach, system-in-a-package (SIAP/SIP) development is a response to an increasing demand for package and die integration of different functions into one unit to reduce size and cost and improve functionality. MEMS add another challenging dimension to electronic packaging since they include moving mechanical elements. Conventional qualification and reliability need to be modified and expanded in most cases in order to detect new unknown failures. This paper will review four standards that already released or being developed that specifically address the issues on qualification and reliability of assembled packages. Exposures to thermal cycles, monotonic bend test, mechanical shock and drop are covered in these specifications. Finally, mechanical and thermal cycle qualification data generated for MEMS accelerometer will be presented. The MEMS was an element of an inertial measurement unit (IMU) qualified for NASA Mars Exploration Rovers (MERs), Spirit and Opportunity that successfully is currently roaring the Martian surface

inertial measurement unit↗