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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 415 records · Page 23
All sourcesNASA NTRSDOE OSTI
NASA NTRS2007

TMS for Instantiating a Knowledge Base With Incomplete Data

A computer program that belongs to the class known among software experts as output truth-maintenance-systems (output TMSs) has been devised as one of a number of software tools for reducing the size of the knowledge base that must be searched during execution of artificial- intelligence software of the rule-based inference-engine type in a case in which data are missing. This program determines whether the consequences of activation of two or more rules can be combined without causing a logical inconsistency. For example, in a case involving hypothetical scenarios that could lead to turning a given device on or off, the program determines whether a scenario involving a given combination of rules could lead to turning the device both on and off at the same time, in which case that combination of rules would not be included in the scenario.

James, Mark↗
NASA NTRS2007

My Rewarding Summer Research Experience at NASA

My summer research experience at the Kennedy Space Center has been a truly rewarding one. As an electrical engineering student at the University of South Florida, I was blessed with a beneficial opportunity to gain valuable knowledge in my career, and also apply it through working at NASA. One of my inspirations in becoming an engineer is to work at NASA someday, and I was very excited and honored to have this opportunity. My goal in this internship was to strengthen my preparation in becoming an engineer by learning new material, acquiring skills by practicing what I learned, and discovering the expectations of engineering work at NASA. Through this summer research, I was able to learn new computer programs and perform various tasks that gave me experience and skills as an engineer. My primary job was to conduct work on the Constellation Test article, which is a simulation model of the Crew Launch Vehicle (CLV) tanking system. This is a prototype of a launch facility and an Ares I Vehicle, which God willing will transport astronauts to the moon. Construction of the CLV is in progress and a test launch is anticipated for 2010. Moreover, the Test Article serves as a demonstration too, training test bed, and may be expanded for new simulation of launch system elements, which could be applied to real life operations. The test article is operated and run by a Programmable Logic Controller (PLC), which is a digital computer that is used to control all forms of machinery such as those in manufacturing buildings and other industries. PLCs are different than other computers because of the physical protection they have against damaging environmental conditions that would destroy other computers. Also, PLCs are equipped with lots of input and output connections that allow extensive amounts of commands to be executed, which would normally require many computers to do. Therefore, PLCs are small, rugged, and extremely powerful tools that may continue to be employed at NASA. Furthermore, in order to conduct productive work on the Test Article, I needed to learn the computer program called RS Logics 5000.

Aviles, Andres↗
NASA NTRS1970

AUTOFLOW enhancements for documentation and maintenance of scientific applications

The use of the AUTOFLOW system is discussed in terms of improving automated documentation. Flowcharts produced by AUTOFLOW are considered to be much more meaningful than those produced manually in that they are accurate, present complete references between all transfer points, and graphically portray the logical flow by automatic rearrangement of those segments of the program that interact.

Goetz, M. A.↗
NASA NTRS1975

SSME structural computer program development: BOPACE programmer manual

The programming manual for the two-dimensional Boeing Plastic Analysis Capability for Engines (BOPACE) program written in FORTRAN IV is presented. The BOPACE flow logic is summarized along with subroutines and input/output files. Emphasis is placed on linear equation solver routines written as an independent package.

Source record↗
NASA NTRS1995

The background and theory of integrated risk management

While all good managers have always considered risk in their decision making, only recently have formal programs to do so been introduced. This report covers the logical structure behind the formulation of an integrated risk management plan (IRM). Included in the report are factors forcing the development of a formal plan to consider risk, the basic objective or purpose of an IRM, and desirable traits of such a plan. The report moves on to a discussion of background issues, seeks to formalize some definitions, and then discusses required information on threats. The report concludes with the steps for an IRM.

Hunsucker, John L.↗
DOE OSTI2020

FPDetect: Efficient Reasoning About Stencil Programs Using Selective Direct Evaluation

We present FPDetect, a low-overhead approach for detecting logical errors and soft errors affecting stencil computations without generating false positives. We develop an offline analysis that tightly estimates the number of floating-point bits preserved across stencil applications. This estimate rigorously bounds the values expected in the data space of the computation. Violations of this bound can be attributed with certainty to errors. FPDetect helps synthesize error detectors customized for user-specified levels of accuracy and coverage. FPDetect also enables overhead reduction techniques based on deploying these detectors coarsely in space and time. Experimental evaluations demonstrate the practicality of our approach.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2002

Simulation Model of A Ferroelectric Field Effect Transistor

An electronic simulation model has been developed of a ferroelectric field effect transistor (FFET). This model can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The model uses a previously developed algorithm that incorporates partial polarization as a basis for the design. The model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current has values matching actual FFET's, which were measured experimentally. The input and output resistance in the model is similar to that of the FFET. The model is valid for all frequencies below RF levels. A variety of different ferroelectric material characteristics can be modeled. The model can be used to design circuits using FFET'S with standard electrical simulation packages. The circuit can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The model is a drop in library that integrates seamlessly into a SPICE simulation. A comparison is made between the model and experimental data measured from an actual FFET.

MacLeod, Todd C.↗
NASA NTRS2001

Electronic Model of a Ferroelectric Field Effect Transistor

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.

MacLeod, Todd C.↗
NASA NTRS1975

Design of automatic startup and shutdown logic for a Brayton-cycle 2- to 15-kilowatt engine

The NASA Lewis Research Center is conducting a closed-Brayton-cycle power conversion system technology program in which a complete power system (engine) has been designed and demonstrated. This report discusses the design of automatic startup and shutdown logic circuits as a modification to the control system presently used in this demonstration engine. This modification was primarily intended to make starting the engine as simple and safe as possible and to allow the engine to be run unattended. In the modified configuration the engine is started by turning the control console power on and pushing the start button after preheating the gas loop. No other operator action is required to effect a complete startup. Shutdown, if one is required, is also effected by a simple stop button. The automatic startup and shutdown of the engine have been successfully and purposefully demonstrated more than 50 times at the Lewis Research Center during 10,000 hours of unattended operation. The net effect of this modification is an engine that can be safely started and stopped by relatively untrained personnel. The approach lends itself directly to remote unattended operation.

Vrancik, J. E.↗
DOE OSTI2023

Modbus RTU for Embedded Cyber Secure Inverter Controller

The Modbus communication protocol is a widely adopted communication standard in industrial control systems. This communication protocol is known for being reliable and straightforward to implement while being versatile in terms of its operating parameters while supporting multiple formats over various hardware infrastructures and architectures. Many intelligent devices such as Programmable Logic Controllers (PLCs), Human-Machine Interfaces (HMIs), Internet-of-Things (IoT), and various Operational Technologies (OT) utilize Modbus for their communication systems. These types of systems must communicate with each other through a standardized and central communication process. To support the integration of these modular systems, a Field-Programmable Gate Array (FPGA) can act as an embedded central routing fabric for this communication to take place. Embedded systems are versatile enough to interface with various devices and systems to accomplish various goals. Additionally, embedded systems require relatively small physical designs to minimize the required resources to facilitate the intended application by providing low-level system access. This minimization of system resources goes hand in hand with reducing the financial cost of a proposed solution or system. As remotely collaborating researchers often use FPGAs to prototype designs that are required to have a method for data transmission among systems, it is imperative to provide a baseline standard for communications among devices and systems. A typical method of implementing the Modbus RTU communication protocol in an embedded environment is using integrated logic architectures within the FPGA called “Intellectual Property (IP) cores.” IP cores can be designed using integrated logic or circuit designs to function as an embedded processor. These IP cores can then perform the required computational actions to support the Modbus RTU communication protocol by utilizing high-level programming languages such as the C programming language. The hardware description language of Very High-Speed Integrated Circuit Hardware Description Language (VHDL) allows for the control of real hardware at the logic gate and signal level. These logic gates and signals can be designed and controlled to perform desired actions based on the system design. Programming an FPGA using VHDL allows an individual to access the lowest abstraction level of the system during FPGA development. This level of abstraction is referred to as the register-transfer level (RTL), which gives access to manipulating values and variables at the register level. This register-level manipulation provides precision over creating the logical circuit within the FPGA, thus minimizing the required code to perform desired operations. The Modbus RTU communication protocol can be implemented within an FPGA using VHDL programming to establish a standardized and embedded serial communication pathway. This implementation provides a standardized communication protocol to streamline research efforts among researchers, thus increasing the efficiency of research efforts. Additionally, this Modbus RTU implementation requires fewer resources when compared to typical communication protocol implementations that utilize an IP core, reducing the hardware requirement for effective research efforts.

communication↗
NASA NTRS1972

Shuttle on-orbit rendezvous targeting: Circular orbits

The strategy and logic used in a space shuttle on-orbit rendezvous targeting program are described. The program generates ascent targeting conditions for boost to insertion into an intermediate parking orbit, and generates on-orbit targeting and timeline bases for each maneuver to effect rendezvous with a space station. Time of launch is determined so as to eliminate any plane change, and all work was performed for a near-circular space station orbit.

Bentley, E. L.↗
NASA NTRS1974

Program manual for the Shuttle Electric Power System analysis computer program (SEPS), volume 1 of program documentation

The Shuttle Electric Power System (SEPS) computer program is considered in terms of the program manual, programmer guide, and program utilization. The main objective is to provide the information necessary to interpret and use the routines comprising the SEPS program. Subroutine descriptions including the name, purpose, method, variable definitions, and logic flow are presented.

Bains, R. W.↗
NASA NTRS1984

Thermoelectric Integrated Membrane Evaporation Subsystem operational improvements

A three-man preprototype Thermoelectric Integrated Membrane Evaporation Subsystem (TIMES) has been developed to provide high quality water recovery from waste fluids on extended duration space flights. In the most recent effort, a number of improvements have been made to simplify subsystem operation and increase performance. These modifications include changes to the hollow fiber membrane evaporator, the condensing section of the thermoelectric heat pump, and the electronic controller logic and display. This paper describes the results of the test program that was conducted to evaluate the implemented improvements. In addition, an advanced design concept is discussed that will provide lower electrical power consumption, greater water production capacity, lower weight, and a smaller package than the present subsystem configuration.

Dehner, G. F.↗
NASA NTRS1986

DEC Ada interface to Screen Management Guidelines (SMG)

DEC's Screen Management Guidelines are the Run-Time Library procedures that perform terminal-independent screen management functions on a VT100-class terminal. These procedures assist users in designing, composing, and keeping track of complex images on a video screen. There are three fundamental elements in the screen management model: the pasteboard, the virtual display, and the virtual keyboard. The pasteboard is like a two-dimensional area on which a user places and manipulates screen displays. The virtual display is a rectangular part of the terminal screen to which a program writes data with procedure calls. The virtual keyboard is a logical structure for input operation associated with a physical keyboard. SMG can be called by all major VAX languages. Through Ada, predefined language Pragmas are used to interface with SMG. These features and elements of SMG are briefly discussed.

Laomanachareon, Somsak↗
NASA NTRS1998

An Object-Oriented Interface to the CCSDS Ground Telecommand Services

The Telecommand Data Routing and Channel Services defined by the Consultative Committee for Space Data Systems (CCSDS) are flexible enough to support a myriad of commanding models. Because the standard is so broad, the traditional approach has been to implement only the portion of the standard needed by the particular spacecraft being tested/operated. Tasked with providing Telecommand Services for an entire class of spacecraft, where each spacecraft may choose any valid CCSDS commanding model, NASA Code 584 designed a common architecture capable of handling the full CCSDS protocol. The solution uses another CCSDS standard - the Standard Formatted Data Unit (SFDU) as the interface to the Telecommand Services. SFDUs provide a consistent way of labelling data objects, as well as allowing data objects to encapsulate other data objects. The resulting interface is: - Flexible: The full Data Routing and Channel Services are available via a single interface. The client (i.e. the command source) may enter commands at any layer within the protocol stack, specify any of the data aggregation or segmentation methods, and dynamically set any configuration parameter defined in the standard. - Object-oriented: Each object specifies both the data and the actions to be performed with the data. An object may contain other objects. - Expandable: New capabilities are added by defining new objects. Objects pass thru the protocol layers until they reach the applicable layer. The resulting design is: - Modular: The logic for each protocol layer is contained in a separate Application Program Interface (API). The objects used for the external interface are also used for communication between layers. - Distributable: The design can be split along any layer boundary for distribution across multiple machines. The objects ensure data consistency across platforms. This paper describes the SFDU-based interface and the resulting protocol implementation. The implementation is currently used by NASA (National Aeronautics and Space Administration) for integration & test of the microwave Anisotropy Probe (MAP) and Earth observer-I (EO-l) spacecraft. It will be used for post-launch operations of these spacecraft as well as the Imager for Magnetopause to Aurora Global Exploration (IMAGE) spacecraft.

Ray, Timothy Joseph↗
NASA NTRS1982

Step-oriented pipeline data processing system

Architecture for step-oriented pipeline data processing is disclosed utilizing a plurality of cascaded modules, each module including a programmable general purpose processor and a read/write random access memory. The memory of each module, shared with the next module in cascade serves as an output memory for the processor and the input memory for the next processor. An additional memory is provided to serve as the input memory of the first module, and each module is provided with a memory, which may be a read-out memory, to store a program for the processor. Each module is further provided with a logic network for resolving a potential memory sharing conflict by awarding priority to the processor of the module.

Castleman, Kenneth R.↗
NASA NTRS2011

Source Lines Counter (SLiC) Version 4.0

Source Lines Counter (SLiC) is a software utility designed to measure software source code size using logical source statements and other common measures for 22 of the programming languages commonly used at NASA and the aerospace industry. Such metrics can be used in a wide variety of applications, from parametric cost estimation to software defect analysis. SLiC has a variety of unique features such as automatic code search, automatic file detection, hierarchical directory totals, and spreadsheet-compatible output. SLiC was written for extensibility; new programming language support can be added with minimal effort in a short amount of time. SLiC runs on a variety of platforms including UNIX, Windows, and Mac OSX. Its straightforward command-line interface allows for customization and incorporation into the software build process for tracking development metrics. T

Monson, Erik W.↗