Adaptive gate biasing - a new solution for body-driven current mirrors
A new body-driven current mirror that utilizes an adaptive gate bias to provide accurate operation over a wide range of bias currents is presented.
current mirror↗
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Use of Field Programmable Gate Array Technology in Future Space Avionics
Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.
Ferguson, Roscoe C.↗
Experimental Analysis of Proton-Induced Displacement and Ionization Damage Using Gate-Controlled Lateral PNP Bipolar Transistors
The electrical characteristics of proton-irradiated bipolar transistors are affected by ionization damage to the insulating oxide and displacement damage to the semiconductor bulk. While both types of damage degrade the transistor, it is important to understand the mechanisms individually and to be able to analyze them separately. In this paper, a method for analyzing the effects of ionization and displacement damage using gate-controlled lateral PNP bipolar junction transistors is described. This technique allows the effects of oxide charge, surface recombination velocity, and bulk traps to be measured independently.
Ball, D. R.↗
InGaAsP Avalanche Photodetectors for Non-Gated 1.06 micrometer Photon-Counting Receivers
The efficient detection of single photons at 1.06 micron is of considerable interest for lidar/ladar systems designed for remote sensing an d ranging as well as for free-space optical transmission in photon-st arved applications. However, silicon-based single photon avalanche diodes (SPADs) used at shorter wavelengths have very low single photon d etection efficiency (approximately 1 - 2%) at 1.06 micron, and InP/In GaAs SPADs designed for telecommunications wavelengths near 1.5 micro n exhibit high dark count rates that generally inhibit non-gated (free-running) operation. To bridge this "single photon detection gap" for wavelengths just beyond 1 micron, we have developed high performance , large area (80 - 200 micron diameter) InP-based InGaAsP quaternary absorber SPADs optimized for operation at 1.06 micron and based on a highly reliable planar geometry avalanche photodiode structure. We wil l show that dark count rates are sufficiently low to allow for non-ga ted operation while achieving detection efficiencies far surpassing t hose found for Si SPADs. At a detection efficiency of 10%, 80 micron diameter devices exhibit dark count rates below 1000 Hz and count rate s of at least 3 MHz when operated at -40 C. Significantly higher dete ction efficiencies (30 - 50%) are achievable with acceptable tradeoff s in dark count rate. In this paper, we will also discuss performance modeling for these devices and compare their behavior with longer wav elength InP-based InGaAs ternary absorber SPADs fabricated on a relat ed device design platform.
Itzler, Mark A.↗
Initial Single Event Effects Testing of the Xilinx Virtex-4 Field Programmable Gate Array
We present initial results for the thin epitaxial Xilinx Virtex-4 Fie ld Programmable Gate Array (FPGA), and compare to previous results ob tained for the Virtex-II and Virtex-II Pro. The data presented was a cquired through a consortium based effort with the common goal of pr oviding the space community with data and mitigation methods for the use of Xilinx FPGAs in space.
single event effects↗
Active pixel sensor pixel having a photodetector whose output is coupled to an output transistor gate
An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.
Fossum, Eric R.↗
Evaluation of the Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Array
The current implementation of the Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays (TRIGA) is equipped with CFDP protocol and CCSDS Telemetry and Telecommand framing schemes to replace the CPU intensive software counterpart implementation for reliable deep space communication. We present the hardware/software co-design methodology used to accomplish high data rate throughput. The hardware CFDP protocol stack implementation is then compared against the two recent flight implementations. The results from our experiments show that TRIGA offers more than 3 orders of magnitude throughput improvement with less than one-tenth of the power consumption.
protocol processing hardware↗
Demonstration of a Sub-Millimeter Wave Integrated Circuit (S-MMIC) using InP HEMT with a 35-nm Gate
In this paper, we present two single stage MMIC amplifiers with the first demonstrating a measured S21 gain of 3-dB at 280-GHz and the second demonstrating 2.5-dB gain at 300- GHz, which is the threshold of the sub-millimeter wave regime. The high-frequency operation is enabled by a high-speed InP HEMT with a 35-nm gate. This is the first demonstrated S21 gain at sub-millimeter wave frequencies in a MMIC.
millimeter - wave↗
Dual-Input AND Gate From Single-Channel Thin-Film FET
A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.
Miranda, F. A.↗
Fabrication of Gate-Electrode Integrated Carbon-Nanotube Bundle Field Emitters
A continuing effort to develop carbon-nanotube-based field emitters (cold cathodes) as high-current-density electron sources has yielded an optimized device design and a fabrication scheme to implement the design. One major element of the device design is to use a planar array of bundles of carbon nanotubes as the field-emission tips and to optimize the critical dimensions of the array (principally, heights of bundles and distances between them) to obtain high area-averaged current density and high reliability over a long operational lifetime a concept that was discussed in more detail in Arrays of Bundles of Carbon Nanotubes as Field Emitters (NPO-40817), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 58. Another major element of the design is to configure the gate electrodes (anodes used to extract, accelerate, and/or focus electrons) as a ring that overhangs a recess wherein the bundles of nanotubes are located, such that by virtue of the proximity between the ring and the bundles, a relatively low applied potential suffices to generate the large electric field needed for emission of electrons.
Toda, Risaku↗
Systems and methods for detecting a failure event in a field programmable gate array
An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.
Ng, Tak-Kwong↗
Universal programmable logic gate and routing method
An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.
Fijany, Amir↗
Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets
An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.
Ng, Tak-kwong↗
Time-Gating Processes in Intra-Cavity Mode-Locking Devices Like Saturable Absorbers and Kerr Cells
Photons are non-interacting entities. Light beams do not interfere by themselves. Light beams constituting different laser modes (frequencies) are not capable of re-arranging their energies from extended time-domain to ultra-short time-domain by themselves without the aid of light-matter interactions with suitable intra-cavity devices. In this paper we will discuss the time-gating properties of intra-cavity "mode-locking" devices that actually help generate a regular train of high energy wave packets.
Prasad, Narasimha↗
Evaluation of Fairchild's Gate Drive Optocoupler, Type FOD3150, Under Wide Temperature Operation
An optocoupler is a semiconductor device that is used to transfer a signal between different parts of a circuit that need to be electrically isolated from one another - for example, where a high voltage is to be switched with a low voltage control signal. Optocouplers often can be used in place of relays. These optocouplers utilize an infrared LED (light emitting diode) and a photodetector such as a silicon controlled rectifier or photosensitive silicon diode for the transfer of the electronic signal between components of a circuit by means of a short optical transmission channel. For maximum coupling, the wave-length responses of the LED and the detector should be very similar. In switch-mode power supply applications, optocouplers offer advantages over transformers by virtue of simpler circuit design, reduced weight, and DC coupling capability. The effects of extreme temperature exposure and thermal cycling on the performance of a commercial-off-the-shelf (COTS) optocoupler, Fairchild FOD3150, were evaluated in this work. This 1.0 A output current, high noise immunity gate drive optocoupler utilizes an aluminum gallium arsenide (AlGaAs) LED, is capable of driving most 800V/20A IGBT/MOSFETs, and is suited for fast switching in motor control inverter applications and high performance power systems. Some of the specifications of the isolator chip are listed. The device was evaluated in terms of output response, output rise (t(sub r)) and fall times (t(sub f)), and propagation delays (using a 50% level between input and output during low to high (t(sub PLH)) and high to low (t(sub PLH)) transitions). The output supply current was also obtained. These parameters were recorded at various test temperatures between -190 C and +110 C.
Patterson, Richard↗
Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays
We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilins Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.
error rate calculations↗
High precision electric gate for time-of-flight ion mass spectrometers
A time-of-flight mass spectrometer having a chamber with electrodes to generate an electric field in the chamber and electric gating for allowing ions with a predetermined mass and velocity into the electric field. The design uses a row of very thin parallel aligned wires that are pulsed in sequence so the ion can pass through the gap of two parallel plates, which are biased to prevent passage of the ion. This design by itself can provide a high mass resolution capability and a very precise start pulse for an ion mass spectrometer. Furthermore, the ion will only pass through the chamber if it is within a wire diameter of the first wire when it is pulsed and has the right speed so it is near all other wires when they are pulsed.
Sittler, Edward C.↗
Operation of a New Half-Bridge Gate Driver for Enhancement - Mode GaN FETs, Type LM5113, Over a Wide Temperature Range
A new commercial-off-the-shelf (COTS) gate driver designed to drive both the high-side and the low-side enhancement-mode GaN FETs, National Semiconductor's type LM5113, was evaluated for operation at temperatures beyond its recommended specified limits of -40 C to +125 C. The effects of limited thermal cycling under the extended test temperature, which ranged from -194 C to +150 C, on the operation of this chip as well as restart capability at the extreme cryogenic and hot temperatures were also investigated. The driver circuit was able to maintain good operation throughout the entire test regime between -194 C and +150 C without undergoing any major changes in its outputs signals and characteristics. The limited thermal cycling performed on the device also had no effect on its performance, and the driver chip was able to successfully restart at each of the extreme temperatures of -194 C and +150 C. The plastic packaging of this device was also not affected by either the short extreme temperature exposure or the limited thermal cycling. These preliminary results indicate that this new commercial-off-the-shelf (COTS) halfbridge eGaN FET driver integrated circuit has the potential for use in space exploration missions under extreme temperature environments. Further testing is planned under long-term cycling to assess the reliability of these parts and to determine their suitability for extended use in the harsh environments of space.
Patterson, Richard↗