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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Integrated data processor-operation controller for stellar TV photometer systems in spaceborne observatory, considering limited channel transmission capacity
LSI 4-bit complementary speed /COS/ MOS parallel processor array
Monolithic COS/MOS large scale parallel processor array
Data processor having multiple sections activated at different times by selective power coupling to sections
Application of domain tip logic in designing associative processors for spaceborne use
Development and characteristics of onboard processor system
On-line closed loop processor for reducing topside ionograms to electron density profiles
Data compression processor for monitoring analog signals by sampling procedure
Exponential downweighting of past data in single stage, weighted least squares trajectory processor for coasting spacecraft
Data processor with plural register stages for selectively interconnecting with each other to effect multiplicity of operations
Design, development, and characteristics of modular spaceborne data processors for space shuttle applications
Nimbus 4 satellite telemetry information processor with data sampling and formatting flexibility
Sequential processor performance prediction error with linear method from Monte Carlo cycle analysis of Apollo 14 early rendezvous profile
A PDP-15 interface was developed for the CAMAC instrumentation standard which implements the features of both the addressable I/0 bus and the single cycle data channel. The data channel section forms an independent I/0 processor which executes programs stored in core. Programs consist of CAMAC commands plus special control characters and commands.
The support software package is described which exists for the advanced on-board processor (AOP) being developed as a general purpose stored program digital computer, with an 18-bit word.
A stored program computer and its application on OAO is considered. The parallel computer has a memory capacity of 16,384 words of 18 bits each, one central processor unit, two 4096 word memory units, and one input/output unit. The I/O has no direct data connection with the CPU so that all data flow between these two units must pass through memory by way of the memory data bus. The primary functions of the onboard computer are auxiliary command storage, spacecraft monitoring and malfunction reporting, data compression and status summary, and possible performance of emergency corrective action.
A feasibility study was made of the application of silicon-controlled, rectifier series, resonant inverter, power conditioning technology to electric propulsion power processing operating from a 200 to 400 Vdc solar array bus. A power system block diagram was generated to meet the electrical requirements of a 20 CM hollow cathode, mercury bombardment, ion engine. The SCR series resonant inverter was developed as a primary means of power switching and conversion, and the analog signal-to-discrete-time-interval converter control system was applied to achieve good regulation. A complete breadboard was designed, fabricated, and tested with a resistive load bank, and critical power processor areas relating to efficiency, weight, and part count were identified.