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At least 433 records · Page 24

A decentralized software bus based on IP multicas ting

We describe decentralized reconfigurable implementation of a conference management system based on the low-level Internet Protocol (IP) multicasting protocol. IP multicasting allows low-cost, world-wide, two-way transmission of data between large numbers of conferencing participants through the Multicasting Backbone (MBone). Each conference is structured as a software bus -- a messaging system that provides a run-time interconnection model that acts as a separate agent (i.e., the bus) for routing, queuing, and delivering messages between distributed programs. Unlike the client-server interconnection model, the software bus model provides a level of indirection that enhances the flexibility and reconfigurability of a distributed system. Current software bus implementations like POLYLITH, however, rely on a centralized bus process and point-to-point protocols (i.e., TCP/IP) to route, queue, and deliver messages. We implement a software bus called the MULTIBUS that relies on a separate process only for routing and uses a reliable IP multicasting protocol for delivery of messages. The use of multicasting means that interconnections are independent of IP machine addresses. This approach allows reconfiguration of bus participants during system execution without notifying other participants of new IP addresses. The use of IP multicasting also permits an economy of scale in the number of participants. We describe the MULITIBUS protocol elements and show how our implementation performs better than centralized bus implementations.

Callahan, John R.↗

InP tunnel junction for InGaAs/InP tandem solar cells

Chemical beam epitaxy (CBE) has been shown to allow the growth of high quality materials with reproducible complex compositional and doping profiles. The main advantage of CBE compared to metalorganic chemical vapor deposition (MOCVD), the most popular technique for InP-based photovoltaic device fabrication, is the ability to grow high purity epilayers at much lower temperatures (450-530 C). We have previously shown that CBE is perfectly suited toward the fabrication of complex photovoltaic devices such as InP/InGaAs monolithically integrated tandem solar cells, because its low process temperature preserves the electrical characteristics of the InGaAs tunnel junction commonly used as an ohmic interconnect. In this work using CBE for the fabrication of optically transparent (with respect to the bottom cell) InP tunnel diodes is demonstrated. Epitaxial growth were performed in a Riber CBE 32 system using PH3 and TMIn as III and V precursors. Solid Be (p-type) and Si (n-type) have been used as doping sources, allowing doping levels up to 2 x 10(exp -19)/cu cm and 1 x 10(exp -19)/cu cm for n and p type respectively. The InP tunnel junction characteristics and the influence of the growth's conditions (temperature, growth rate) over its performance have been carefully investigated. InP p(++)/n(++) tunnel junction with peak current densities up to 1600 A/sq cm and maximum specific resistivities (V(sub p)/I(sub p) - peak voltage to peak current ratio) in the range of 10(exp -4) Omega-sq cm were obtained. The obtained peak current densities exceed the highest results previously reported for their lattice matched counterparts, In(0.53)Ga( 0.47)As and should allow the realization of improved minimal absorption losses in the interconnect InP/InGaAs tandem devices for Space applications. Owing to the low process temperature required for the top cell, these devices exhibit almost no degradation of its characteristics after the growth of subsequent thick InP layer suggesting minimal doping cross diffusion in the narrow space-charge region (approximately 1-5 nm) of the device. The fabrication of tandem devices using InP tunnel diodes as interconnect is in progress and will be reported at the conference.

Vilela, M. F.↗

High-voltage space-plasma interactions measured on the PASP Plus test arrays

The Photovoltaic Array Space Power Plus Diagnostics (PASP Plus) experiment was developed by the Air Force's Phillips Laboratory with support from NASA's Lewis Research Center. It was launched on the Advanced Photovoltaic and Electronics EXperiments (APEX) satellite on August 3, 1994 into a 70 degree inclination, 363 km by 2550 km elliptical orbit. This orbit allows the investigation of space plasma effects on high-voltage operation (leakage current at positive voltages and arcing at negative voltages) in the perigee region. PASP Plus is testing twelve solar arrays. There are four planar Si arrays: an old standard type (used as a reference), the large-cell Space Station Freedom (SSF) array, a thin 'APSA' array, and an amorphous Si array. Next are three GaAs on Ge planar arrays and three new material planar arrays, including InP and two multijunction types. Finally, there are two concentrator arrays: a reflective-focusing Mini-Cassegrainian and a Fresnel-lens focusing Mini-Dome. PASP Plus's diagnostic sensors include: Langmuir probe to measure plasma density, an electrostatic analyzer (ESA) to measure the 30 eV to 30 KeV electron/ion spectra and determine vehicle negative potential during positive biasing, and a transient pulse monitor (TPM) to characterize the arcs that occur during the negative biasing. Through positive biasing of its test arrays, PASP Plus investigated the snapover phenomenon, which took place over the range of +100 to +300 V. It was found that array configurations where the interconnects are shielded from the space plasma (i.e., the concentrators or arrays with 'wrap-through' connectors) have lower leakage current. The concentrators exhibited negligible leakage current over the whole range up to +500 V. In the case of two similar GaAs on Ge arrays, the one with 'wrap-through' connectors had lower leakage current than the one with conventional interconnects. Through negative biasing, PASP Plus investigated the arcing rates of its test arrays. The standard Si array, with its old construction (exposed rough-surface interconnects), arced significantly over a wide voltage and plasma-density range. The other arrays arced at very low rates, mostly at voltages greater than -350 V and plasma densities near or greater than 10(exp 5)/cm(exp -3). AS expected according to theory, arcing was more prevalent when array temperatures were cold (based on biasing in eclipse).

Guidice, Donald A.↗

Advanced packaging for Integrated Micro-Instruments

The relationship between packaging, microelectronics, and micro-electrical-mechanical systems (MEMS) is an important one, particularly when the edges of performance boundaries are pressed, as in the case of miniaturized systems. Packaging is a sort of physical backbone that enables the maximum performance of these systems to be realized, and the penalties imposed by conventional packing approaches is particularly limiting for MEMS devices. As such, advanced packaging approaches, such as multi-chip modules (MCM's) have been touted as a true means of electronic 'enablement' for a variety of application domains. Realizing an optimum system of packaging, however, in not as simple as replacing a set of single chip packages with a substrate of interconnections. Research at Phillips Laboratory has turned up a number of integrating options in the two- and three-dimensional rending of miniature systems with physical interconnection structures with intrinsically high performance. Not only do these structures motivate the redesign of integrated circuits (IC's) for lower power, but they possess interesting features that provide a framework for the direct integration of MEMS devices. Cost remains a barrier to the application of MEMS devices, even in space systems. Several innovations are suggested that will result in lower cost and more rapid cycle time. First, the novelty of a 'constant floor plan' MCM which encapsulates a variety of commonly used components into a stockable, easily customized assembly is discussed. Next, the use of low-cost substrates is examined. The anticipated advent of ultra-high density interconnect (UHDI) is suggested as the limit argument of advanced packaging. Finally, the concept of a heterogeneous 3-D MCM system is outlined that allows for the combination of different compatible packaging approaches into a uniformly dense structure that could also include MEMS-based sensors.

Lyke, James L.↗

Scalable Performance Environments for Parallel Systems

As parallel systems expand in size and complexity, the absence of performance tools for these parallel systems exacerbates the already difficult problems of application program and system software performance tuning. Moreover, given the pace of technological change, we can no longer afford to develop ad hoc, one-of-a-kind performance instrumentation software; we need scalable, portable performance analysis tools. We describe an environment prototype based on the lessons learned from two previous generations of performance data analysis software. Our environment prototype contains a set of performance data transformation modules that can be interconnected in user-specified ways. It is the responsibility of the environment infrastructure to hide details of module interconnection and data sharing. The environment is written in C++ with the graphical displays based on X windows and the Motif toolkit. It allows users to interconnect and configure modules graphically to form an acyclic, directed data analysis graph. Performance trace data are represented in a self-documenting stream format that includes internal definitions of data types, sizes, and names. The environment prototype supports the use of head-mounted displays and sonic data presentation in addition to the traditional use of visual techniques.

Reed, Daniel A.↗

Balancing Contention and Synchronization on the Intel Paragon

The Intel Paragon is a mesh-connected distributed memory parallel computer. It uses an oblivious and deterministic message routing algorithm: this permits us to develop highly optimized schedules for frequently needed communication patterns. The complete exchange is one such pattern. Several approaches are available for carrying it out on the mesh. We study an algorithm developed by Scott. This algorithm assumes that a communication link can carry one message at a time and that a node can only transmit one message at a time. It requires global synchronization to enforce a schedule of transmissions. Unfortunately global synchronization has substantial overhead on the Paragon. At the same time the powerful interconnection mechanism of this machine permits 2 or 3 messages to share a communication link with minor overhead. It can also overlap multiple message transmission from the same node to some extent. We develop a generalization of Scott's algorithm that executes complete exchange with a prescribed contention. Schedules that incur greater contention require fewer synchronization steps. This permits us to tradeoff contention against synchronization overhead. We describe the performance of this algorithm and compare it with Scott's original algorithm as well as with a naive algorithm that does not take interconnection structure into account. The Bounded contention algorithm is always better than Scott's algorithm and outperforms the naive algorithm for all but the smallest message sizes. The naive algorithm fails to work on meshes larger than 12 x 12. These results show that due consideration of processor interconnect and machine performance parameters is necessary to obtain peak performance from the Paragon and its successor mesh machines.

Bokhari, Shahid H.↗

Metal-Silicate Segregation in Deforming Dunitic Rocks: Applications to Core Formation in Europa and Ganymede

Core formation is an important event in the evolution of a planetary body, affecting both the geochemical and geophysical properties of the body. Metal-silicate segregation could have proceeded either by settling of liquid metal through a magma ocean or by percolation of liquid metal through a solid silicate mantle. Percolation of metallic melt had previously been excluded as a viable segregation mechanism because metallic melts do not form an interconnected network under hydrostatic conditions, except at high melt fraction (>5 vol%), due to the high dihedral angle between metals and silicates (>60 ). Without an interconnected network, porous flow of metallic melt is impossible, leaving the magma ocean scenario as the only mechanism to form the core. Moment-of-inertia measurements of Europa and Ganymede from the Galileo probe indicate that they are differentiated. This evidence suggests that a method for segregating metals and silicates at temperatures low enough to retain volatile compounds must exist. We have investigated the effect of deformation on the distribution of metallic melts in silicates. We have deformed samples of olivine + 5-9 vol% Fe-S to strains of 2.5 in simple shear and find that the metallic melt segregates into melt-rich planes oriented at 20 to the shear plane. These metallic melt-rich bands are similar in structure to the silicate melt-rich bands reported by Holtzman, indicating that deformation can interconnect isolated metallic melt pockets and allow porous flow of non-wetting melts. Such a core formation process could have occurred in the jovian satellites.

Hustoft, J. W.↗

Applications of SPICE for modeling miniaturized biomedical sensor systems

This paper proposes a model for a miniaturized signal conditioning system for biopotential and ion-selective electrode arrays. The system consists of three main components: sensors, interconnections, and signal conditioning chip. The model for this system is based on SPICE. Transmission-line based equivalent circuits are used to represent the sensors, lumped resistance-capacitance circuits describe the interconnections, and a model for the signal conditioning chip is extracted from its layout. A system for measurements of biopotentials and ionic activities can be miniaturized and optimized for cardiovascular applications based on the development of an integrated SPICE system model of its electrochemical, interconnection, and electronic components.

Microelectrodes↗

Truss structure design

An integrally formed three-dimensional truss structure, including molds and methods for production of same, containing outer top and bottom plane surfaces thereof comprising interconnected rod segments integrally formed at their points of intersection on the outer top and bottom surfaces, the top and bottom surfaces also integrally joined together through additional interconnected rod segments passing through an integrally formed intersection, wherein the additional interconnected rod segments passing through the integrally formed intersection form a three-dimensional continuous array of triangles.

Daily, Carl S.↗

Vibration isolation mounting system

A system is disclosed for mounting a vibration producing device onto a spacecraft structure and also for isolating the vibration forces thereof from the structure. The system includes a mount on which the device is securely mounted and inner and outer rings. The rings and mount are concentrically positioned. The system includes a base (secured to the structure) and a set of links which are interconnected by a set of torsion bars which allow and resist relative rotational movement therebetween. The set of links are also rotatably connected to a set of brackets which are rigidly connected to the outer ring. Damped leaf springs interconnect the inner and outer rings and the mount allow relative translational movement therebetween in X and Y directions. The links, brackets and base are interconnected and configured so that they allow and resist translational movement of the device in the Z direction so that in combination with the springs they provide absorption of vibrational energy produced by the device in all three dimensions while providing rotational stiffness about all three axes to prevent undesired rotational motions.

Carter, Sam D.↗

High conductance ohmic junction for monolithic semiconductor devices

In order to increase the efficiency of solar cells, a monolithic stacked device is constructed comprising a plurality of solar sub-cells adjusted for different bands of radiation. The interconnection between these sub-cells has been a significant technical problem. The invention provides an interconnection which is a thin layer of high ohmic conductance material formed between the sub-cells. Such a layer tends to form beads which serve as a shorting interconnect while passing a large fraction of the radiation to the lower sub-cells and permitting lattice-matching between the sub-cells to be preserved.

Lewis, Carol R.↗

Method of making a high conductance ohmic junction for monolithic semiconductor devices

In order to increase the efficiency of solar cells, a monolithic stacked device is constructed comprising a plurality of solar sub-cells adjusted for different bands of radiation. The interconnection between these sub-cells has been a significant technical problem. The invention provides an interconnection which is a thin layer of high ohmic conductance material formed between the sub-cells. Such a layer tends to form beads which serve as a shorting interconnect while passing a large fraction of the radiation to the lower sub-cells and permitting lattice-matching between the sub-cells to be preserved.

Lewis, Carol R.↗

Computationally efficient modeling and simulation of large scale systems

A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X.sup.1 and at least one other matrix, with first equation including X.sup.1Y, X.sup.1A, and X.sup.1P, and the second equation including X.sup.1A and X.sup.1P.

Jain, Jitesh↗

Computationally efficient modeling and simulation of large scale systems

A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X.sup.-1 and at least one other matrix, with first equation including X.sup.-1Y, X.sup.-1A, and X.sup.-1P, and the second equation including X.sup.-1A and X.sup.-1P.

Jain, Jitesh↗

Fully Printed, Flexible, Phased Array Antenna for Lunar Surface Communication

NASAs future exploration missions focus on the manned exploration of the Moon, Mars, and beyond, which will rely heavily on the development of a reliable communications infrastructure from planetary surface-to-surface, surface-to-orbit, and back to Earth. Flexible antennas are highly desired in many scenarios. Active phased array antennas (active PAAs) with distributed control and processing electronics at the surface of an antenna aperture offer numerous advantages for radar communications. Large-area active PAAs on flexible substrates are of particular interest in NASA s space radars due to their efficient inflatable package that can be rolled up during transportation and deployed in space. Such an inflatable package significantly reduces stowage volume and mass. Because of these performance and packaging advantages, large-area inflatable active PAAs are highly desired in NASA s surface-to-orbit and surface-to-relay communications. To address the issues of flexible electronics, a room-temperature printing process of active phased-array antennas on a flexible Kapton substrate was developed. Field effect transistors (FETs) based on carbon nanotubes (CNTs), with many unique physical properties, were successfully proved feasible for the PAA system. This innovation is a new type of fully inkjet-printable, two-dimensional, high-frequency PAA on a flexible substrate at room temperature. The designed electronic circuit components, such as the FET switches in the phase shifter, metal interconnection lines, microstrip transmission lines, etc., are all printed using a special inkjet printer. Using the developed technology, entire 1x4, 2x2, and 4x4 PAA systems were developed, packaged, and demonstrated at 5.3 GHz. Several key solutions are addressed in this work to solve the fabrication issues. The source/drain contact is developed using droplets of silver ink printed on the source/drain areas prior to applying CNT thin-film. The wet silver ink droplets allow the silver to wet the CNT thin-film area and enable good contact with the source and drain contact after annealing. A passivation layer to protect the device channel is developed by bonding a thin Kapton film on top of the device channel. This film is also used as the media for transferring the aligned CNT thin-film on the device substrate. A simple and cost-effective technique to form multilayer metal interconnections on flexible substrate is developed and demonstrated. Contact vias are formed on the second substrate prior to bonding on the first substrate. Inkjet printing is used to fill the silver ink into the via structure. The printed silver ink penetrates through the vias to contact with the contact pads on the bottom layer. It is then annealed to form a good connection. One-dimensional and two-dimensional PAAs were fabricated and characterized. In these circuits, multilayer metal interconnects were used to make a complete PAA system.

Subbaraman, Harish↗

Computationally Efficient Modeling and Simulation of Large Scale Systems

A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, including a processor, and a memory, the processor configured to perform obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure, the element values for each matrix including inductance L and inverse capacitance P, obtaining an adjacency matrix A associated with the interconnect structure, storing the matrices X, Y, and A in the memory, and performing numerical integration to solve first and second equations.

Jain, Jitesh↗

Interfacing Space Communications and Navigation Network Simulation with Distributed System Integration Laboratories (DSIL)

NASA's planned Lunar missions will involve multiple NASA centers where each participating center has a specific role and specialization. In this vision, the Constellation program (CxP)'s Distributed System Integration Laboratories (DSIL) architecture consist of multiple System Integration Labs (SILs), with simulators, emulators, testlabs and control centers interacting with each other over a broadband network to perform test and verification for mission scenarios. To support the end-to-end simulation and emulation effort of NASA' exploration initiatives, different NASA centers are interconnected to participate in distributed simulations. Currently, DSIL has interconnections among the following NASA centers: Johnson Space Center (JSC), Kennedy Space Center (KSC), Marshall Space Flight Center (MSFC) and Jet Propulsion Laboratory (JPL). Through interconnections and interactions among different NASA centers, critical resources and data can be shared, while independent simulations can be performed simultaneously at different NASA locations, to effectively utilize the simulation and emulation capabilities at each center. Furthermore, the development of DSIL can maximally leverage the existing project simulation and testing plans. In this work, we describe the specific role and development activities at JPL for Space Communications and Navigation Network (SCaN) simulator using the Multi-mission Advanced Communications Hybrid Environment for Test and Evaluation (MACHETE) tool to simulate communications effects among mission assets. Using MACHETE, different space network configurations among spacecrafts and ground systems of various parameter sets can be simulated. Data that is necessary for tracking, navigation, and guidance of spacecrafts such as Crew Exploration Vehicle (CEV), Crew Launch Vehicle (CLV), and Lunar Relay Satellite (LRS) and orbit calculation data are disseminated to different NASA centers and updated periodically using the High Level Architecture (HLA). In addition, the performance of DSIL under different traffic loads with different mix of data and priorities are evaluated.

Traffic Measuring and Monitoring↗

Progress Towards Prolonged Deployment of SiC JFET-R ICs Into Previously Inaccessible Hostile Environments

This invited presentation describes demonstration of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. SiC junction field effect transistor-resistor (JFET-R) ICs with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient [1], 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber [2], and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes [3]. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C T-span) without significant change in signal (input /output) or power supply voltages [4]. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards this end, the processing that forms the SiC JFETs and resistors (without interconnect) for the NASA Glenn “Generation 12” design prototype JFET-R ICs was conducted at GE Research. Once the COVID-delayed IC interconnect and bond pad fabrication processing on these wafers is completed at NASA Glenn, the resulting chips will be packaged and oven-tested [5]. It is expected that further technology transfer to complete commercial production will lower investment and risk barriers to useful application deployment. For NASA, an initial high-value deployment is opening the Venus surface to extended missions for robotic scientific exploration.

Silicon Carbide↗