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NASA NTRS2001

Development of an Innovative Algorithm for Aerodynamics-Structure Interaction Using Lattice Boltzmann Method

The lattice Boltzmann equation (LBE) is a kinetic formulation which offers an alternative computational method capable of solving fluid dynamics for various systems. Major advantages of the method are owing to the fact that the solution for the particle distribution functions is explicit, easy to implement, and the algorithm is natural to parallelize. In this final report, we summarize the works accomplished in the past three years. Since most works have been published, the technical details can be found in the literature. Brief summary will be provided in this report. In this project, a second-order accurate treatment of boundary condition in the LBE method is developed for a curved boundary and tested successfully in various 2-D and 3-D configurations. To evaluate the aerodynamic force on a body in the context of LBE method, several force evaluation schemes have been investigated. A simple momentum exchange method is shown to give reliable and accurate values for the force on a body in both 2-D and 3-D cases. Various 3-D LBE models have been assessed in terms of efficiency, accuracy, and robustness. In general, accurate 3-D results can be obtained using LBE methods. The 3-D 19-bit model is found to be the best one among the 15-bit, 19-bit, and 27-bit LBE models. To achieve desired grid resolution and to accommodate the far field boundary conditions in aerodynamics computations, a multi-block LBE method is developed by dividing the flow field into various blocks each having constant lattice spacing. Substantial contribution to the LBE method is also made through the development of a new, generalized lattice Boltzmann equation constructed in the moment space in order to improve the computational stability, detailed theoretical analysis on the stability, dispersion, and dissipation characteristics of the LBE method, and computational studies of high Reynolds number flows with singular gradients. Finally, a finite difference-based lattice Boltzmann method is developed for inviscid compressible flows.

Mei, Ren-Wei↗

NASA NTRS2003

Improving TCP Network Performance by Detecting and Reacting to Packet Reordering

There are many factors governing the performance of TCP-basec applications traversing satellite channels. The end-to-end performance of TCP is known to be degraded by the reordering, delay, noise and asymmetry inherent in geosynchronous systems. This result has been largely based on experiments that evaluate the performance of TCP in single flow tests. While single flow tests are useful for deriving information on the theoretical behavior of TCP and allow for easy diagnosis of problems they do not represent a broad range of realistic situations and therefore cannot be used to authoritatively comment on performance issues. The experiments discussed in this report test TCP s performance in a more dynamic environment with competing traffic flows from hundreds of TCP connections running simultaneously across the satellite channel. Another aspect we investigate is TCP's reaction to bit errors on satellite channels. TCP interprets loss as a sign of network congestion. This causes TCP to reduce its transmission rate leading to reduced performance when loss is due to corruption. We allowed the bit error rate on our satellite channel to vary widely and tested the performance of TCP as a function of these bit error rates. Our results show that the average performance of TCP on satellite channels is good even under conditions of loss as high as bit error rates of 10(exp -5)

Kruse, Hans↗

NASA NTRS2004

Design of Timer Circuit for Dynamic Data System

The Branch That I work in is in the Aero Electronic Test Branch, which is part of the Research and Testing Division. The Aero Electronic Test Branch deals with electronic control and instrumentation systems. This branch supports the research and test study of wind tunnels such as the l0x10,9x15, and 8x6. Wind tunnels are used in research to test certain parts of a jet, plane, shuttle or any other flying object in certain test conditions. My assignment is to design a programmable trigger circuit on a 19 standard rack mount that will allow the circuit to latch and hold for a predefined amount of time entered by the user when receiving a signal. It should then re-arm itself within 0.25 seconds after the time is finished. The time should be able to be seen on a display showing the time entered. The time range has to be from 0-600 seconds in 0.01 second increments (600.00). From the information given, counters will be needed to design and build this circuit. A counter, in it s simplest form, is a group of flip flops that can temporarily store bits of information put into the circuit. They can be constructed in many different ways, such as in 4 flip flops (4-bit counter) or 8 flip flops and even higher. Counters are usually cascaded with other counters to reach higher bits, such as 16 or 24 bit counters. The application in which I will use the counters will be to count down from any programmable number that I input either by a keyboard or a thumbwheel. Also, I will use counters that will be used specifically as a frequency divider to divide the pulses that enter the circuit through an input signal from a crystal clock. The pulses will need to be divided so that it will function as a 100Hz clock putting out 100 pulses per second. A switch will be used to load my inputs in and more than likely a button also so that I can stop and hold the count at any point of time. I will use 5 BCD up/down programmable counters, and a certain amount (depending on what kind of "divide by N" counter I use) of frequency dividing counters for the assignment. After the design is carefully made, a task order will be written and then given to the manufacturer to create a rack mount circuit board that will match my specifications given. The applications in which this design will be used for is in the use of the six-component balance signal conditioner for measurement and electronic system control. It can be used as a timer system for the balance signal conditioner in which it does numerous tests for the Wind tunnel research, in which a preset time can be set for how long it performs its tests. Specifically, my design should be applied to the balance signal conditioner used for the 8x6 wind tunnel research. Hopefully this design should aid in more efficient research for the 8x6 wind tunnel.

Young, Nathaniel, III↗

NASA NTRS1997

High precision computing with charge domain devices and a pseudo-spectral method therefor

The present invention enhances the bit resolution of a CCD/CID MVM processor by storing each bit of each matrix element as a separate CCD charge packet. The bits of each input vector are separately multiplied by each bit of each matrix element in massive parallelism and the resulting products are combined appropriately to synthesize the correct product. In another aspect of the invention, such arrays are employed in a pseudo-spectral method of the invention, in which partial differential equations are solved by expressing each derivative analytically as matrices, and the state function is updated at each computation cycle by multiplying it by the matrices. The matrices are treated as synaptic arrays of a neural network and the state function vector elements are treated as neurons. In a further aspect of the invention, moving target detection is performed by driving the soliton equation with a vector of detector outputs. The neural architecture consists of two synaptic arrays corresponding to the two differential terms of the soliton-equation and an adder connected to the output thereof and to the output of the detector array to drive the soliton equation.

Barhen, Jacob↗

NASA NTRS2006

Design of a Multi-Level/Analog Ferroelectric Memory Device

Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

MacLeod, Todd C.↗

NASA NTRS1989

Digital signal processor and processing method for GPS receivers

A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P.sub.1, and P.sub.2 channels on the L.sub.1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.

Thomas, Jr., Jess B.↗

NASA NTRS2008

Scheme for Quantum Computing Immune to Decoherence

A constructive scheme has been devised to enable mapping of any quantum computation into a spintronic circuit in which the computation is encoded in a basis that is, in principle, immune to quantum decoherence. The scheme is implemented by an algorithm that utilizes multiple physical spins to encode each logical bit in such a way that collective errors affecting all the physical spins do not disturb the logical bit. The scheme is expected to be of use to experimenters working on spintronic implementations of quantum logic. Spintronic computing devices use quantum-mechanical spins (typically, electron spins) to encode logical bits. Bits thus encoded (denoted qubits) are potentially susceptible to errors caused by noise and decoherence. The traditional model of quantum computation is based partly on the assumption that each qubit is implemented by use of a single two-state quantum system, such as an electron or other spin-1.2 particle. It can be surprisingly difficult to achieve certain gate operations . most notably, those of arbitrary 1-qubit gates . in spintronic hardware according to this model. However, ironically, certain 2-qubit interactions (in particular, spin-spin exchange interactions) can be achieved relatively easily in spintronic hardware. Therefore, it would be fortunate if it were possible to implement any 1-qubit gate by use of a spin-spin exchange interaction. While such a direct representation is not possible, it is possible to achieve an arbitrary 1-qubit gate indirectly by means of a sequence of four spin-spin exchange interactions, which could be implemented by use of four exchange gates. Accordingly, the present scheme provides for mapping any 1-qubit gate in the logical basis into an equivalent sequence of at most four spin-spin exchange interactions in the physical (encoded) basis. The complexity of the mathematical derivation of the scheme from basic quantum principles precludes a description within this article; it must suffice to report that the derivation provides explicit constructions for finding the exchange couplings in the physical basis needed to implement any arbitrary 1-qubit gate. These constructions lead to spintronic encodings of quantum logic that are more efficient than those of a previously published scheme that utilizes a universal but fixed set of gates.

Williams, Colin↗

NASA NTRS2010

Mars Science Laboratory Drill

The Drill for the Mars Science Laboratory mission is a rotary-percussive sample acquisition device with an emphasis on toughness and robustness to handle the harsh environment on Mars. The unique challenges associated with autonomous drilling from a mobile robot are addressed. A highly compressed development schedule dictated a modular design architecture that satisfies the functional and load requirements while allowing independent development and testing of the Drill subassemblies. The Drill consists of four actuated mechanisms: a spindle that rotates the bit, a chuck that releases and engages bits, a novel voice-coil-based percussion mechanism that hammers the bit, and a linear translation mechanism. The Drill has three passive mechanisms: a replaceable bit assembly that acquires and collects sample, a contact sensor / stabilizer mechanism, and, lastly a flex harness service loop. This paper describes the various mechanisms that makeup the Drill and discusses the solutions to their unique design and development challenges.

Okon, Avi B.↗

NASA NTRS2010

Injecting Errors for Testing Built-In Test Software

Two algorithms have been conceived to enable automated, thorough testing of Built-in test (BIT) software. The first algorithm applies to BIT routines that define pass/fail criteria based on values of data read from such hardware devices as memories, input ports, or registers. This algorithm simulates effects of errors in a device under test by (1) intercepting data from the device and (2) performing AND operations between the data and the data mask specific to the device. This operation yields values not expected by the BIT routine. This algorithm entails very small, permanent instrumentation of the software under test (SUT) for performing the AND operations. The second algorithm applies to BIT programs that provide services to users application programs via commands or callable interfaces and requires a capability for test-driver software to read and write the memory used in execution of the SUT. This algorithm identifies all SUT code execution addresses where errors are to be injected, then temporarily replaces the code at those addresses with small test code sequences to inject latent severe errors, then determines whether, as desired, the SUT detects the errors and recovers

Gender, Thomas K.↗

NASA NTRS2010

Miniature Low-Mass Drill Actuated by Flextensional Piezo Stack

Recent experiments with a flextensional piezoelectric actuator have led to the development of a sampler with a bit that is designed to produce and capture a full set of sample forms including volatiles, powdered cuttings, and core fragments. The flextensional piezoelectric actuator is a part of a series of devices used to amplify the generated strain from piezoelectric actuators. Other examples include stacks, bimorphs, benders, and cantilevers. These devices combine geometric and resonance amplifications to produce large stroke at high power density. The operation of this sampler/drill was demonstrated using a 3x2x1-cm actuator weighing 12 g using power of about 10-W and a preload of about 10 N. A limestone block was drilled to a depth of about 1 cm in five minutes to produce powdered cuttings. It is generally hard to collect volatiles from random surface profiles found in rocks and sediment, powdered cuttings, and core fragments. Toward the end of collecting volatiles, the actuator and the bit are covered with bellows-shaped shrouds to prevent fines and other debris from reaching the analyzer. A tube with a miniature bellows (to provide flexibility) is connected to the bit and directs the flow of the volatiles to the analyzer. Another modality was conceived where the hose is connected to the bellows wall directly to allow the capture of volatiles generated both inside and outside the bit. A wide variety of commercial bellows used in the vacuum and microwave industries can be used to design the volatiles capture mechanism. The piezoelectric drilling mechanism can potentially be operated in a broad temperature range from about-200 to less than 450 C. The actuators used here are similar to the actuators that are currently baselined to fly as part of the inlet funnel shaking mechanism design of MSL (Mars Science Laboratory). The space qualification of these parts gives this drill a higher potential for inclusion in a future mission, especially when considering its characteristics of low mass, small size, low power, and low axial loads for sampling.

Sherrit, Stewart↗

NASA NTRS2005

Fastener Starter

The Fastener Starter is a creative solution to prevent the loss of small fasteners during their installation. This is the only currently available tool that can firmly grip and hold a single screw, bolt, nut, washer, spacer, or any combination of these parts. Other commercially available fastener starters are unable to accommodate a variety of parts simultaneously. The Fastener Starter is a more capable and easier tool to use than prior tools. Its compact size allows it to be used effectively in cramped, difficult-to-see locations. Its design also allows it to be used with or without handles and extenders in other difficult-to-reach locations. It provides better protection against cross threading and loss of fasteners and associated parts. The Fastener Starter is non-magnetic and does not off-gas, thus meeting flight hardware requirements. The Fastener Starter incorporates a combination of features of several commercially available tools, providing an improved means of installing small fasteners. The Fastener Starter includes a custom molded insert that can be removed easily and replaced with a conventional tool bit (e.g., a screwdriver or hex-driver bit). When used with the insert, the Fastener Starter prevents cross threading and damage to internal threaded holes. This is achieved by allowing the fastener to slip within the tool insert when used without a conventional tool bit. Alternatively, without the insert and with a tool bit, the Fastener Starter can torque a fastener. The Fastener Starter has a square recess hole that accepts a conventional square drive handle or extension to accommodate a variety of applications by providing flexibility in handle style and length.

Chandler, Faith↗

NASA NTRS2004

Serial-Turbo-Trellis-Coded Modulation with Rate-1 Inner Code

Serially concatenated turbo codes have been proposed to satisfy requirements for low bit- and word-error rates and for low (in comparison with related previous codes) complexity of coding and decoding algorithms and thus low complexity of coding and decoding circuitry. These codes are applicable to such high-level modulations as octonary phase-shift keying (8PSK) and 16-state quadrature amplitude modulation (16QAM); the signal product obtained by applying one of these codes to one of these modulations is denoted, generally, as serially concatenated trellis-coded modulation (SCTCM). These codes could be particularly beneficial for communication systems that must be designed and operated subject to limitations on bandwidth and power. Some background information is prerequisite to a meaningful summary of this development. Trellis-coded modulation (TCM) is now a well-established technique in digital communications. A turbo code combines binary component codes (which typically include trellis codes) with interleaving. A turbo code of the type that has been studied prior to this development is composed of parallel concatenated convolutional codes (PCCCs) implemented by two or more constituent systematic encoders joined through one or more interleavers. The input information bits feed the first encoder and, after having been scrambled by the interleaver, enter the second encoder. A code word of a parallel concatenated code consists of the input bits to the first encoder followed by the parity check bits of both encoders. The suboptimal iterative decoding structure for such a code is modular, and consists of a set of concatenated decoding modules one for each constituent code connected through an interleaver identical to the one in the encoder side. Each decoder performs weighted soft decoding of the input sequence. PCCCs yield very large coding gains at the cost of a reduction in the data rate and/or an increase in bandwidth.

Divsalar, Dariush↗

NASA NTRS2003

Capacitor-Chain Successive-Approximation ADC

A proposed successive-approximation analog-to-digital converter (ADC) would contain a capacitively terminated chain of identical capacitor cells. Like a conventional successive-approximation ADC containing a bank of binary-scaled capacitors, the proposed ADC would store an input voltage on a sample-and-hold capacitor and would digitize the stored input voltage by finding the closest match between this voltage and a capacitively generated sum of binary fractions of a reference voltage (Vref). However, the proposed capacitor-chain ADC would offer two major advantages over a conventional binary-scaled-capacitor ADC: (1) In a conventional ADC that digitizes to n bits, the largest capacitor (representing the most significant bit) must have 2(exp n-1) times as much capacitance, and hence, approximately 2(exp n-1) times as much area as does the smallest capacitor (representing the least significant bit), so that the total capacitor area must be 2(exp n) times that of the smallest capacitor. In the proposed capacitor-chain ADC, there would be three capacitors per cell, each approximately equal to the smallest capacitor in the conventional ADC, and there would be one cell per bit. Therefore, the total capacitor area would be only about 3(exp n) times that of the smallest capacitor. The net result would be that the proposed ADC could be considerably smaller than the conventional ADC. (2) Because of edge effects, parasitic capacitances, and manufacturing tolerances, it is difficult to make capacitor banks in which the values of capacitance are scaled by powers of 2 to the required precision. In contrast, because all the capacitors in the proposed ADC would be identical, the problem of precise binary scaling would not arise.

Cunningham, Thomas↗

NASA NTRS2011

Digital Interface Board to Control Phase and Amplitude of Four Channels

An increasing number of parts are designed with digital control interfaces, including phase shifters and variable attenuators. When designing an antenna array in which each antenna has independent amplitude and phase control, the number of digital control lines that must be set simultaneously can grow very large. Use of a parallel interface would require separate line drivers, more parts, and thus additional failure points. A convenient form of control where single-phase shifters or attenuators could be set or the whole set could be programmed with an update rate of 100 Hz is needed to solve this problem. A digital interface board with a field-programmable gate array (FPGA) can simultaneously control an essentially arbitrary number of digital control lines with a serial command interface requiring only three wires. A small set of short, high-level commands provides a simple programming interface for an external controller. Parity bits are used to validate the control commands. Output timing is controlled within the FPGA to allow for rapid update rates of the phase shifters and attenuators. This technology has been used to set and monitor eight 5-bit control signals via a serial UART (universal asynchronous receiver/transmitter) interface. The digital interface board controls the phase and amplitude of the signals for each element in the array. A host computer running Agilent VEE sends commands via serial UART connection to a Xilinx VirtexII FPGA. The commands are decoded, and either outputs are set or telemetry data is sent back to the host computer describing the status and the current phase and amplitude settings. This technology is an integral part of a closed-loop system in which the angle of arrival of an X-band uplink signal is detected and the appropriate phase shifts are applied to the Ka-band downlink signal to electronically steer the array back in the direction of the uplink signal. It will also be used in the non-beam-steering case to compensate for phase shift variations through power amplifiers. The digital interface board can be used to set four 5-bit phase shifters and four 5-bit attenuators and monitor their current settings. Additionally, it is useful outside of the closed-loop system for beamsteering alone. When the VEE program is started, it prompts the user to initialize variables (to zero) or skip initialization. After that, the program enters into a continuous loop waiting for the telemetry period to elapse or a button to be pushed. A telemetry request is sent when the telemetry period is elapsed (every five seconds). Pushing one of the set or reset buttons will send the appropriate command. When a command is sent, the interface status is returned, and the user will be notified by a pop-up window if any error has occurred. The program runs until the End Program button is depressed.

Smith, Amy E.↗

NASA NTRS2012

Single Piezo-Actuator Rotary-Hammering (SPaRH) Drill

The search for present or past life in the Universe is one of the most important objectives of NASA's exploration missions. Drills for subsurface sampling of rocks, ice and permafrost are an essential tool for astrobiology studies on other planets. Increasingly, it is recognized that drilling via a combination of rotation and hammering offers an efficient and effective rapid penetration mechanism. The rotation provides an intrinsic method for removal of cuttings from the borehole while the impact and shear forces aids in the fracturing of the penetrated medium. Conventional drills that use a single actuator are based on a complex mechanism with many parts and their use in future mission involves greater risk of failure and/or may require lubrication that can introduce contamination. In this paper, a compact drill is reported that uses a single piezoelectric actuator to produce hammering and rotation of the bit. A horn with asymmetric grooves was design to impart a longitudinal (hammering) and transverse force (rotation) to a keyed free mass. The drill requires low axial pre-load since the hammering-impacts fracture the rock under the bit kerf and rotate the bit to remove the powdered cuttings while augmenting the rock fracture via shear forces. The vibrations 'fluidize' the powdered cuttings inside the flutes reducing the friction with the auger surface. This action reduces the consumed power and heating of the drilled medium helping to preserve the pristine content of the acquired samples. The drill consists of an actuator that simultaneously impacts and rotates the bit by applying force and torque via a single piezoelectric stack actuator without the need for a gearbox or lever mechanism. This can reduce the development/fabrication cost and complexity. In this paper, the drill mechanism will be described and the test results will be reported and discussed.

ultrasonic impacts↗

NASA NTRS2012

Percussive Augmenter of Rotary Drills (PARoD)

Increasingly, NASA exploration mission objectives include sample acquisition tasks for in-situ analysis or for potential sample return to Earth. To address the requirements for samplers that could be operated at the conditions of the various bodies in the solar system, a piezoelectric actuated percussive sampling device was developed that requires low preload (as low as 10N) which is important for operation at low gravity. This device can be made as light as 400g, can be operated using low average power, and can drill rocks as hard as basalt. Significant improvement of the penetration rate was achieved by augmenting the hammering action by rotation and use of a fluted bit to provide effective cuttings removal. Generally, hammering is effective in fracturing drilled media while rotation of fluted bits is effective in cuttings removal. To benefit from these two actions, a novel configuration of a percussive mechanism was developed to produce an augmenter of rotary drills. The device was called Percussive Augmenter of Rotary Drills (PARoD). A breadboard PARoD was developed with a 6.4 mm (0.25 in) diameter bit and was demonstrated to increase the drilling rate of rotation alone by 1.5 to over 10 times. Further, a large PARoD breadboard with 50.8 mm diameter bit was developed and its tests are currently underway. This paper presents the design, analysis and preliminary test results of the percussive augmenter.

percussive augmenter↗

NASA NTRS2013

Microgravity Drill and Anchor System

This work is a method to drill into a rock surface regardless of the gravitational field or orientation. The required weight-on-bit (WOB) is supplied by a self-contained anchoring mechanism. The system includes a rotary percussive coring drill, forming a complete sampling instrument usable by robot or human. This method of in situ sample acquisition using micro - spine anchoring technology enables several NASA mission concepts not currently possible with existing technology, including sampling from consolidated rock on asteroids, providing a bolt network for astronauts visiting a near-Earth asteroid, and sampling from the ceilings or vertical walls of lava tubes and cliff faces on Mars. One of the most fundamental parameters of drilling is the WOB; essentially, the load applied to the bit that allows it to cut, creating a reaction force normal to the surface. In every drilling application, there is a minimum WOB that must be maintained for the system to function properly. In microgravity (asteroids and comets), even a small WOB could not be supported conventionally by the weight of the robot or astronaut. An anchoring mechanism would be needed to resist the reactions, or the robot or astronaut would push themselves off the surface and into space. The ability of the system to anchor itself to a surface creates potential applications that reach beyond use in low gravity. The use of these anchoring mechanisms as end effectors on climbing robots has the potential of vastly expanding the scope of what is considered accessible terrain. Further, because the drill is supported by its own anchor rather than by a robotic arm, the workspace is not constrained by the reach of such an arm. Yet, if the drill is on a robotic arm, it has the benefit of not reflecting the forces of drilling back to the arm s joints. Combining the drill with the anchoring feet will create a highly mobile, highly stable, and highly reliable system. The drilling system s anchor uses hundreds of microspine toes that independently find holes and ledges on a rock to create an anchor. Once the system is anchored, a linear translation mechanism moves the drill axially into the surface while maintaining the proper WOB. The linear translation mechanism is composed of a ball screw and stepper motor that can translate a carriage with high precision and applied load. The carriage slides along rails using self-aligning linear bearings that correct any axial misalignment caused by bending and torsion. The carriage then compresses a series of springs that simultaneously transmit the load to the drill along the bit axis and act as a suspension that compensates for the vibration caused by percussive drilling. The drill is a compacted, modified version of an off-the-shelf rotary percussive drill, which uses a custom carbide-tipped coring bit. By using rotary percussive drilling, the drill time is greatly reduced. The percussive action fractures the rock debris, which is removed during rotation. The final result is a 0.75-in. (.1.9- cm) diameter hole and a preserved 0.5- in. (.1.3-cm) diameter rock core. This work extends microspine technology, making it applicable to astronaut missions to asteroids and a host of robotic sampling concepts. At the time of this reporting, it is the first instrument to be demonstrated using microspine anchors, and is the first self-contained drill/anchor system to be demonstrated that is capable of drilling in inverted configurations and would be capable of drilling in microgravity.

Parness, Aaron↗

NASA NTRS2013

Soft Decision Analyzer

The Soft Decision Analyzer (SDA) is an instrument that combines hardware, firmware, and software to perform realtime closed-loop end-to-end statistical analysis of single- or dual- channel serial digital RF communications systems operating in very low signal-to-noise conditions. As an innovation, the unique SDA capabilities allow it to perform analysis of situations where the receiving communication system slips bits due to low signal-to-noise conditions or experiences constellation rotations resulting in channel polarity in versions or channel assignment swaps. SDA s closed-loop detection allows it to instrument a live system and correlate observations with frame, codeword, and packet losses, as well as Quality of Service (QoS) and Quality of Experience (QoE) events. The SDA s abilities are not confined to performing analysis in low signal-to-noise conditions. Its analysis provides in-depth insight of a communication system s receiver performance in a variety of operating conditions. The SDA incorporates two techniques for identifying slips. The first is an examination of content of the received data stream s relation to the transmitted data content and the second is a direct examination of the receiver s recovered clock signals relative to a reference. Both techniques provide benefits in different ways and allow the communication engineer evaluating test results increased confidence and understanding of receiver performance. Direct examination of data contents is performed by two different data techniques, power correlation or a modified Massey correlation, and can be applied to soft decision data widths 1 to 12 bits wide over a correlation depth ranging from 16 to 512 samples. The SDA detects receiver bit slips within a 4 bits window and can handle systems with up to four quadrants (QPSK, SQPSK, and BPSK systems). The SDA continuously monitors correlation results to characterize slips and quadrant change and is capable of performing analysis even when the receiver under test is subjected to conditions where its performance degrades to high error rates (30 percent or beyond). The design incorporates a number of features, such as watchdog triggers that permit the SDA system to recover from large receiver upsets automatically and continue accumulating performance analysis unaided by operator intervention. This accommodates tests that can last in the order of days in order to gain statistical confidence in results and is also useful for capturing snapshots of rare events.

Steele, Glen↗