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The development of a universal voice processor is discussed. The device is based on several circuit configurations using hybrid techniques to satisfy the electrical specifications. The steps taken during the design process are described. Circuit diagrams of the final design are presented. Mathematical models are included to support the theoretical aspects.
Program documentation was separated into two catagories: documentation for program use and documentation for program analysis, modification, or extension. The symbol scanner, flow chart production subsystem, decision table subsystem, and scan processor are also described.
The onboard data processor for OAO 3 flight applications executes instructions at the rate of 2 1/2 billion per day. The computer commands, processes data, and controls telemetry subsystem programs onboard the spacecraft.
A hybrid processor is described offering enough handling capacity and speed to process efficiently the large quantities of multispectral data that can be gathered by scanner systems such as MSDS, SKYLAB, ERTS, and ERIM M-7. Combinations of general-purpose and special-purpose hybrid computers were examined to include both analog and digital types as well as all-digital configurations. The current trend toward lower costs for medium-scale digital circuitry suggests that the all-digital approach may offer the better solution within the time frame of the next few years. The study recommends and defines such a hybrid digital computing system in which both special-purpose and general-purpose digital computers would be employed. The tasks of recognizing surface objects would be performed in a parallel, pipeline digital system while the tasks of control and monitoring would be handled by a medium-scale minicomputer system. A program to design and construct a small, prototype, all-digital system has been started.
A timing discriminator whose output is relatively insensitive to input pulse width and amplitude is described. The video-handling technique is known as slope reversal processing and is based on tapped delay line estimation methods. The concept, design, breadboard construction, and preliminary laboratory test results are reviewed. The processor system features (1) a peak input voltage dynamic range of 80x starting at 100 microvolts; (2) a four stage preamplifier/line-driver having a voltage gain of 2400x; (3) a tapped delay-line estimator implemented for slope reversal triggering by differential comparison; (4) a nominal plus or minus 2.5 nsec shift of the output trigger leading edge over the entire input voltage range, (5) up to 7 dB discrimination against pulse widths less than 35 nsec; and (6) up to one order of magnitude reduction in the false alarm rate compared to a constant fraction system.
This paper presents some thoughts on functional organization in cerebral tissue. 'Spontaneous' wave and unit firing are considered as essential phenomena in the handling of information. Various models are discussed which have been suggested to describe the pseudorandom behavior of brain cells, leading to a view of the brain as an information processor and its role in learning, memory, remembering and forgetting.
A study has been made on restoration of degraded images utilizing spatial filtering techniques in a coherent optical processor. This study differs from other coherent approaches in that the spatial filters employed contain only composite gratings that are quite simple to produce. A general method of synthesizing the appropriate composite gratings for linearly smeared as well as multiply exposed and out-of-focus images will be presented in some detail with experimental results. The extension of the method of synthesis to other types of degradation is briefly discussed.
Parallel data processor clock pulses are conditionally supplied to processing unit in response to relative values of binary bit of control source and binary bit derived on single lead. Use of single lead simplifies fabrication of large-scale integrated networks.
Processor is automatic and includes series of extraction tubes packed with fibrous absorbent material of large surface area. When introduced into these tubes, liquid test samples become completely absorbed by packing material as thin film.
Advanced On-board Processor the (AOP) uses large scale integration throughout and is the most advanced space qualified computer of its class in existence today. It was designed to satisfy most spacecraft requirements which are anticipated over the next several years. The AOP design utilizes custom metallized multigate arrays (CMMA) which have been designed specifically for this computer. This approach provides the most efficient use of circuits, reduces volume, weight, assembly costs and provides for a significant increase in reliability by the significant reduction in conventional circuit interconnections. The required 69 CMMA packages are assembled on a single multilayer printed circuit board which together with associated connectors constitutes the complete AOP. This approach also reduces conventional interconnections thus further reducing weight, volume and assembly costs.
Testing conducted to determine the feasibility of converting the 16/35/70 hi-speed processor to process Kodak film types 7381/7271 (16mm) and 5381/5271 (35mm) color negative films using Kodak ECP chemistry is described.
The DLG processor is a Univac 1100 series computer program designed to read, modify, manipulate, and replace symbolic images. DLG is controlled by a set of user supplied directives and operates from a data base of stratified information which can be merged with the symbolic images. Data bases can be constructed and maintained in the mass storage media using the DLG directive language.
A satellite borne extreme ultraviolet solar telescope makes use of CCD area arrays for both image readout and onboard data processing. The instrument is designed to view the inner solar corona in the wavelength band 170 - 630 A, and the output video stream may be selected by ground command to present the coronal scene, or the time-rate-of-change of the scene. Details of the CCD application to onboard image processing are described, and a discussion of the processor's potential for telemetry bandwidth compression is included. Optical coupling methods, data storage requirements, spatial and temporal resolution, and nonsymmetry of resolution (pitch) in the CCD are discussed.
The ILLIAC IV, a fourth generation multiprocessor using parallel processing hardware concepts, is operational at Moffett Field, California. Its capability to excel at matrix manipulation, makes the ILLIAC well suited for performing structural analyses using the finite element displacement method. The feasibility of modifying the NASTRAN (NASA structural analysis) computer program to make effective use of the ILLIAC IV was investigated. The characteristics are summarized of the ILLIAC and the ARPANET, a telecommunications network which spans the continent making the ILLIAC accessible to nearly all major industrial centers in the United States. Two distinct approaches are studied: retaining NASTRAN as it now operates on many of the host computers of the ARPANET to process the input and output while using the ILLIAC only for the major computational tasks, and installing NASTRAN to operate entirely in the ILLIAC environment. Though both alternatives offer similar and significant increases in computational speed over modern third generation processors, the full installation of NASTRAN on the ILLIAC is recommended. Specifications are presented for performing that task with manpower estimates and schedules to correspond.
Minimum hardware, reliable processor responds rapidly to changing requirements simply by changes in contents of programmable read-only memory. General purpose controller can transfer data onto and off of data bus, perform logic and arithmetic manipulations, and store pertinent data in small internal random-access memory.
A microprocessor navigation systems using the Omega process is discussed. Several methods for correcting incoming sky waves are presented along with the hardware design which depends on a microcomputer. The control program is discussed, and block diagrams of the Omega processor and interface systems are presented.
The design requirements are established for all external or interproject interfaces to the Network Interface Processor located in Building 30 at the Lyndon B. Johnson Space Center, Houston, Texas. In addition to external interfaces, software/hardware and special interfaces are also described.
Correlation clustering of 250,000 pixels are numerically classified in real time according to various image elements. Processor operates upon data supplied by Earth Resources Technology Satellite. Algorithmic signal manipulation is used to provide discrete control of individual image parameters.