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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 433 records · Page 24
All sourcesNASA NTRSDOE OSTI
NASA NTRS1981

High-efficiency thin-film GaAs solar cells, phase2

Thin GaAs epi-layers with good crystallographic quality were grown using a (100) Si-substrate on which a thin Ge epi-interlayer was grown by CVD from germane. Both antireflection-coated metal oxide semiconductor (AMOS) and n(+)/p homojunction structures were studied. The AMOS cells were fabricated on undoped-GaAs epi-layers deposited on bulk poly-Ge substrates using organo-metallic CVD film-growth, with the best achieved AM1 conversion efficiency being 9.1%. Both p-type and n(+)-type GaAs growth were optimized using 50 ppm dimethyl zinc and 1% hydrogen sulfide, respectively. A direct GaAs deposition method in fabricating ultra-thin top layer, epitaxial n(+)/p shallow homojunction solar cells on (100) GaAs substrates (without anodic thinning) was developed to produce large area (1 sq/cm) cells, with 19.4% AM1 conversion efficiency achieved. Additionally, an AM1 conversion efficiency of 18.4% (17.5% with 5% grid coverage) was achieved for a single crystal GaAs n(+)/p cell grown by OM-CVD on a Ge wafer.

Yeh, Y. C. M.↗
NASA NTRS1991

Silicon carbide, an emerging high temperature semiconductor

In recent years, the aerospace propulsion and space power communities have expressed a growing need for electronic devices that are capable of sustained high temperature operation. Applications for high temperature electronic devices include development instrumentation within engines, engine control, and condition monitoring systems, and power conditioning and control systems for space platforms and satellites. Other earth-based applications include deep-well drilling instrumentation, nuclear reactor instrumentation and control, and automotive sensors. To meet the needs of these applications, the High Temperature Electronics Program at the Lewis Research Center is developing silicon carbide (SiC) as a high temperature semiconductor material. Research is focussed on developing the crystal growth, characterization, and device fabrication technologies necessary to produce a family of silicon carbide electronic devices and integrated sensors. The progress made in developing silicon carbide is presented, and the challenges that lie ahead are discussed.

Matus, Lawrence G.↗
DOE OSTI2021

Computational Fermi Level Engineering and Doping-Type Conversion of Ga2O3 Via Three-Step Processing

Ga2O3 is being actively explored for power electronics, deep-ultraviolet optoelectronics, and other applications due to its ultra-wide bandgap and low projected fabrication cost of large-size and high-quality crystals. N-type doping of Ga2O3 can be achieved and tuned, but p-type doping faces fundamental obstacles due to deep character of acceptor levels and polaron transport of resulting holes. However, successful engineering of Ga2O3 based devices requires critical control of doping density, Fermi level position, and free carrier concentration, providing opportunities for predictive process simulation. We use first-principles defect theory and defect equilibrium calculations to simulate a 3-step growth-annealing-quench protocol for hydrogen assisted Mg doping in Ga2O3, taking into account the hydrogen-oxygen-water gas phase equilibrium. We predict type conversion to a net p-type regime following O-rich annealing after growth under reducing conditions in the presence of H2. This process is similar to the Mg acceptor activation by H removal in GaN. We show that there is an optimal temperature that maximizes the net acceptor density during the equilibrium annealing step for a given Mg doping level. Quenching of non-equilibrium annealed samples then results in a Fermi level EF below mid-gap down to about EV +1.5 eV, creating a significant number of uncompensated neutral MgGa0 acceptors. The resulting free hole concentration in quenched samples is very low (109 – 1012 cm-3) due to deep energy level of these Mg acceptors, but this type converted Ga2O3 material can create a significant built-in field in a p-n junction with an adjoining n-type material. Additionally, the electron concentration is greatly suppressed in such acceptor-doped Ga2O3, which could enable the use as a current blocking layer to fabricate normally-off (enhancement-mode) vertical Ga2O3 based metal-oxide-semiconductor field effect transistors (MOSFETs), and as a guard ring for edge termination in MOSFETs and Schottky barrier diodes (SBDs) with increased breakdown voltage.

CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS,M↗
DOE OSTI2023

Molecular Beam Epitaxy of Monocrystalline GaAs on Water-Soluble NaCl Thin Films

The goal of this project was to demonstrate the feasibility of employing an epitaxial NaCl thin film as a water-soluble release layer for III-V photovoltaic devices and GaAs substrate reuse. Over the course of this project efforts were focused on: 1) achieving crystalline NaCl thin films on GaAs (100) substrate, 2) exploring the growth parameters for subsequent GaAs on NaCl thin films in effort to improve crystallinity of the semiconductor layer, 3) deposition and removal of single crystalline solar cell devices from the parent substrate, and 4) improving morphology and reducing large scale defects in the removed layers to fabricate a working a solar cell device. There was no previous work on direct integration of GaAs/NaCl/GaAs heterostructures at the time of this study. We used molecular beam epitaxy (MBE) to deposit both the alkali halide salt and subsequent III-V material in the same chamber, with no vacuum break. Single crystalline GaAs films were achieved on NaCl layers through careful tuning of the growth parameters and exposure to the reflection high energy electron diffraction (RHEED) beam. Dissolution of the NaCl layer in water provided rapid release of the semiconductor layer from the substrate. Monocrystalline solar cells were grown on the III-V templates using MBE and dynamic hydride vapor phase epitaxy (HVPE). However, the extended time at elevated temperatures required for the cell growth resulted in large area defects from fusion of the semiconductor overlayer to the substrate, causing shorts in fabricated devices. By changing the way that the template layer was grown, the density of these defects could be reduced. Unfortunately, the defects were not reduced to a level allowing for fabrication of a working device.

14 SOLAR ENERGY↗
NASA NTRS1976

Fabrication of polycrystalline solar cells on low-cost substrates

A new method of producing p-n junction semiconductors for solar cells was described; the principal objective of this investigation is to reduce production costs significantly by depositing polycrystalline silicon on a relatively cheap substrate such as metallurgical-grade silicon, graphite, or steel. The silicon layer contains appropriate dopants, and the substrates are coated with a diffusion barrier of silica, borosilicate, phosphosilicate, or mixtures of these compounds.

Chu, T. L.↗
DOE OSTI2022

Fabrication of Nb3Sn by Magnetron Sputtering for Superconducting Radiofrequency Application

Particle accelerators are considered as an important device that has wide applications in cancer treatment, sterilizing waste, preserving foods, ion implantation in semiconductor industry, and in production of isotopes for medical applications. Superconducting radiofrequency (SRF) cavities are the building blocks of a linear particle accelerator. Current particle accelerators use niobium (Nb) superconductors as the sheet material to fabricate a single SRF cavity for particle acceleration. With better superconducting properties (critical temperature Tc ~ 18.3 K, superheating field Hsh~ 400 mT), Nb3Sn is considered a potential candidate in SRF technology. Magnetron sputtering is a promising deposition method to fabricate Nb3Sn thin films inside SRF cavities. Superconducting Nb3Sn films were fabricated on Nb and sapphire substrates by magnetron sputtering from a single stoichiometric Nb3Sn target, by multilayer sputtering of Nb and Sn followed by annealing, and by co-sputtering of Nb and Sn followed by annealing. The variation of morphological and superconducting properties was investigated for different substrate temperatures, annealing temperatures, annealing durations, and thicknesses. The film properties were characterized by X-ray diffraction (XRD), scanning electron microscopy (SEM), atomic force microscopy (AFM), and energy dispersive X-ray spectroscopy (EDS). The films had crystalline Nb3Sn structure without any presence of poor superconducting Nb6Sn5 and NbSn2 phases. The highest Tc of the films fabricated from the stoichiometric target, multilayer sputtering and co-sputtering were 17.44, 17.93, and 17.66 K respectively. Finally, a cylindrical sputter coater with two identical magnetrons was designed and commissioned to fabricate Nb3Sn films inside a 2.6 GHz SRF cavity. The magnetrons were installed facing opposite to each other in a custom designed vacuum chamber and multilayers of Nb and Sn films on 1 cm2 Nb substrates replicating the beam tubes and equator locations of the cavity and the coated multilayered films were annealed at 950 °C for 3 h. The XRD of the as?deposited and annealed films confirmed the formation of Nb3Sn after the annealing. The dissertation discusses the fabrication process, characterized results of the fabricated films, the design of the cylindrical sputter coater and the preliminary data obtained from the sputter coater.

Sayeed, Md Nizam↗
DOE OSTI2023

Nanosecond Laser Drying in Wafer Foundries for Significant Energy Efficiency Improvement

Surface drying is a critical process in microelectronics wafer fabrication. In order to reduce and eliminate watermarks, many surface drying processes have been studied and used. Most of the wafer foundries currently use drying processes based on Isopropyl Alcohol (IPA), which causes serious safety (fire), health, environmental, and energy efficiency issues. The long-term goal of this project is to develop a fast, effective, chemical-free, and extremely energy efficient wafer drying technology that employs nanosecond laser-induced sub-surface evaporation and explosion. The objectives of this project are to 1) experimentally develop and verify the laser surface drying method, explore and identify how and to what extent various physical parameters influence the drying efficiency and effectiveness; and 2) understand and optimize the underlying thermodynamics in the proposed laser surface drying, including micro/nanoscale sub-surface superheating, evaporation, explosion, and photo/thermochemical bond breaking via atomistic modeling and experimental characterization. Toward these objectives, five tasks have been accomplished successfully, including 1) develop in-lab laser surface drying setup and study the effect of varied laser parameters, 2) use multiscale hybrid-modeling to study and understand the physics of water behavior during drying toward process optimization, 3) investigate the effect of drying conditions on the drying effectiveness, 4) develop a large-scale laser drying scanning system with automatic scanning, and 5) conduct large-scale simulation to study the effect of dopant level and develop strategies for system development toward industry deployment.

42 ENGINEERING↗
NASA NTRS1993

Energetic Atoms Would Etch Photoresists Anisotropically

Directed beams of single oxygen atoms having kinetic energies between 1 and 5 eV used in anisotropic etching of oxygen-labile photoresist patterns on silicon wafers. Key step in manufacturing integrated circuits on semiconductor wafers. Damage to semiconductor material under photoresist layer reduced or eliminated. Method incorporated into lithographic processes for fabrication of integrated circuits.

Koontz, Steven↗
NASA NTRS2003

Measured Propagation Characteristics of Coplanar Waveguide on Semi-Insulating 4H-SiC Through 800 K

Wireless sensors for high temperature industrial applications and jet engines require RF transmission lines and RF integrated circuits (RFICs) on wide bandgap semiconductors such as SiC. In this paper, the complex propagation constant of coplanar waveguide fabricated on semiinsulating 4H-SiC has been measured through 813 K. It is shown that the attenuation increases 3.4 dB/cm at 50 GHz as the SiC temperature is increased from 300 K to 813 K. Above 500 K, the major contribution to loss is the decrease in SiC resistivity. The effective permittivity of the same line increases by approximately 5 percent at microwave frequencies and 20 percent at 1 GHz.

Ponchak, George E.↗
NASA NTRS2009

Survey Analysis of Materials Processing Experiments Aboard STS-47: Spacelab J

This Technical Memorandum (TM) is a survey outline of materials processing experiments aboard Space Shuttle Mission STS-47: Spacelab J, a joint venture between NASA and the National Space Development Agency of Japan. The mission explored materials processing experiments including electronics and crystal growth materials, metals and alloys, glasses and ceramics, and fluids. Experiments covered include Growth of Silicone Spherical Crystals and Surface Oxidation, Growth Experiment of Narrow Band-Gap Semiconductor Lead-Tin-Tellurium Crystals in Space, Study on Solidification of Immiscible Alloys, Fabrication of Very-Low-Density, High-Stiffness Carbon Fiber/Aluminum Hybridized Composites, High Temperature Behavior of Glass, and Study of Bubble Behavior. The TM underscores the historical significance of these experiments in the context of materials processing in space.

Sharpe, R. J.↗
NASA NTRS2017

Solid-State Neutron Detector Device

The structure and methods of fabricating a high efficiency compact solid state neutron detector based on III-Nitride semiconductor structures deposited on a substrate. The operation of the device is based on absorption of neutrons, which results in generation of free carriers.

Bensaoula, Abdelhak↗
DOE OSTI2022

Epitaxial Dirac Semimetal Vertical Heterostructures for Advanced Device Architectures

Exploiting the extraordinary transport and optical properties of 3D topological semimetals for device applications requires epitaxial integration with semiconductors to carefully control carrier transport, yet no studies have established heteroepitaxy on top of any topological semimetals to date. Here, a novel approach toward fabricating heterostructures is demonstrated by epitaxially incorporating the Dirac semimetal Cd 3 As 2 between Zn x Cd 1-x Te and CdTe layers via molecular beam epitaxy on GaAs (001) substrates. The approach utilizes the higher energy (001) surface of Cd 3 As 2 to stabilize 2D epitaxy of zinc blende semiconductors. To demonstrate the impact heterostructure formation offers to device performance, an all-epitaxial, barrier-type vertical photodetector is fabricated that accesses a different carrier separation mechanism than previously reported non-epitaxial junctions and consequently exhibits significantly reduced dark currents. Finally, the results highlight the important role that epitaxial integration can play in accessing advanced architectures for topological semimetal-based devices.

36 MATERIALS SCIENCE↗
NASA NTRS1993

Non-destructive, ultra-low resistance, thermally stable contacts for use on shallow junction InP solar cells

Contact formation to InP is plagued by violent metal-semiconductor intermixing that takes place during the contact sintering process. Because of this the InP solar cell cannot be sintered after contact deposition. This results in cell contact resistances that are orders of magnitude higher than those that could be achieved if sintering could be performed in a non-destructive manner. We report here on a truly unique contact system involving Au and Ge, which is easily fabricated, which exhibits extremely low values of contact resistivity, and in which there is virtually no metal-semiconductor interdiffusion, even after extended sintering. We present a description of this contact system and suggest possible mechanisms to explain the observed behavior.

Weizer, V. G.↗
NASA NTRS2011

Thermoelectric Performance Enhancement by Surrounding Crystalline Semiconductors with Metallic Nanoparticles

Direct conversion of thermal energy to electricity by thermoelectric (TE) devices may play a key role in future energy production and utilization. However, relatively poor performance of current TE materials has slowed development of new energy conversion applications. Recent reports have shown that the dimensionless Figure of Merit, ZT, for TE devices can be increased beyond the state-of-the-art level by nanoscale structuring of materials to reduce their thermal conductivity. New morphologically designed TE materials have been fabricated at the NASA Langley Research Center, and their characterization is underway. These newly designed materials are based on semiconductor crystal grains whose surfaces are surrounded by metallic nanoparticles. The nanoscale particles are used to tailor the thermal and electrical conduction properties for TE applications by altering the phonon and electron transport pathways. A sample of bismuth telluride decorated with metallic nanoparticles showed less thermal conductivity and twice the electrical conductivity at room temperature as compared to pure Bi2Te3. Apparently, electrons cross easily between semiconductor crystal grains via the intervening metallic nanoparticle bridges, but phonons are scattered at the interfacing gaps. Hence, if the interfacing gap is larger than the mean free path of the phonon, thermal energy transmission from one grain to others is reduced. Here we describe the design and analysis of these new materials that offer substantial improvements in thermoelectric performance.

Kim, Hyun-Jung↗
DOE OSTI2020

Application of templated vapor-liquid-solid growth to heteroepitaxy of InP on Si

Direct growth of III–V semiconductors on Si promises to combine the superior optoelectronic properties of III–Vs with the existing large-scale fabrication capabilities for Si. Vapor-liquid-solid-based growth techniques have previously been used to grow optoelectronic-quality III–Vs in polycrystalline films and various photolithography-defined features. We show that templated vapor-liquid-solid growth can produce epitaxial material when performed on crystalline substrates. In templated vapor-liquid-solid growth, the metal group-III precursor is evaporated along with a capping SiO 2 layer on the crystalline substrate, then melted and converted with exposure to a vapor-phase group-V precursor. We demonstrate homoepitaxial growth of InP on InP wafers using two forms of the SiO x capping layer to confine the liquid metal: evaporated SiO 2 and solgel SiO x , the latter of which is necessary for growth on Si. We then demonstrate heteroepitaxial growth of InP islands on Si substrates from both evaporated and electroplated In metals. The templated vapor-liquid-solid process provides better material utilization and growth rates than common vapor-phase techniques, with similar control and convenience, providing a path toward the large-scale fabrication of integrated optoelectronic components.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS2000

All-Metal Magnetic RAM

The factors that enter into the development of an all-metal, nonvolatile magnetic RAM, in which multilayer giant magnetoresistive films are used for all functions - storage, readout, and support electronics - are described. Four significant characteristics are expected to favor all-metal over hybrid magnetic RAM. First, silicon-technology fabrication requires a large number of masking steps, including complex ones such as ion implantation. Conversely, all-metal technology is inherently simple: fewer masking steps, no doping, scaling to lithographic limits, very little operating power. Second, the all-metal footprint is significantly smaller than the hybrid one. Third, an all-metal RAM is expected to be able to be miniaturized to lithographic limits; miniaturization of hybrid magnetic RAMs is likely to be limited by the semiconductor circuitry. Finally, semiconductor processing and magnetic processing in MRAM are done separately because the former requires high temperatures, whereas magnetic fabrication is a low-temperature process. By contrast, because both GMR electronics and the memory elements are made of the same materials, the two major components are deposited and patterned concurrently on the same substrate.

Torok, E. J.↗