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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 451 records · Page 25
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

On the Origin of Holes During Polarization Reset in Floating Body Ferroelectric FETs Towards Improving Switching Efficiency

In this article, we performed a comprehensive combined experimental and modeling study on the polarization reset mechanisms of floating body (i.e., channel) ferroelectric FETs, an important class of device with growing interests due to added functionalities and improved reliabilities. Using fully-depleted silicon-on-insulator (FDSOI) FeFET as a classical example, we demonstrate that: 1) without hole generation mechanisms, floating body FeFETs during reset is simply a capacitor divider, with negligible ferroelectric voltage drop for switching; ii) Band-to-band-tunneling (BTBT) around gate-to-S/D overlap even with zero drain bias generates holes to facilitate the reset in FDSOI FeFET, though at a slower speed and hold the reset state; iii) With scaling, S/D inner fringe field can enable fast reset, thus offering a potential efficiency boost approach; iv) a compact FDSOI FeFET model is developed that can capture the BTBT effect and reproduce the observed behaviors; v) the reset mechanism is also validated in a NAND string composed of FDSOI FeFETs, demonstrating its relevant applications. These insights show the strategies in improving reset efficiency, i.e., enhanced BTBT and inner fringe field.

42 ENGINEERING↗
DOE OSTI2025

The Upgrade of the SNS Extraction Kicker Power Supplies for the Proton Power Upgrade

The Proton Power Upgrade (PPU) project at the Spallation Neutron Source (SNS) aims to enhance the linear accelerator's power output from 1.4 to 2.8 megawatts. A critical focus lies on upgrading the Extraction Kicker Power Supplies to handle the amplified beam power. The existing capacitor charging power supplies lacked the capability to charge the Blumlein-type Pulse Forming Network (PFN) to the required 40 kV at a repetition rate of 60 Hz. To address this limitation, an initial solution involving the use of a resonant charging circuit was proposed. However, a challenge arose with a self-firing issue in the thyristor switch, which proved unsolvable within the given timeframe. Facing a critical decision point in the project, an alternative approach was explored: integrating a supplementary power supply to enhance the overall power capacity. This solution was tested and ultimately chosen as the path forward. To accommodate the additional power supply, the power distribution system had to undergo upgrades. Throughout this endeavor, a comprehensive examination of the system took place, with meticulous identification of key components. This paper delves into the technical challenges encountered during the process and the corresponding solutions that were implemented.

Tan, Yugang [ORNL] (ORCID:0000000155968252)↗
DOE OSTI2020

Design of BLDC Motor Diagnostic Device Based on Surge Test for Phase to Ground Fault

BLDC motor is essential in the industrial world, especially it been used for an electric vehicle. The benefit of using BLDC motor is that it has high rate efficiency and low mechanical losses. However, to know the isolation condition of winding and increase reliability, it needs to be tested. With the implementation of surge test based fault detection device of BLDC motor, the condition of BLDC motor can be monitored and maintained according to analysis of its condition. The surge test method used because it is sensitive in detecting the initial damage in the isolation failure process on stator winding. A surge voltage is generated from the Cockroft-Walton and switching circuit with capacitors. The result is analyzed using Error Area Ratio (EAR). The test result shows that the higher the value of resistance and inductance, the smaller the frequency of the surge wave. When the BLDC motor in a parallel short circuit condition, the threshold value of the EAR test-reff has a minimum value of 5.28%, an average of 13.52%, and a maximum of 28.55%.

BLDC motor↗
DOE OSTI2022

A 194nW Energy-Performance-Aware loT SoC Employing a 5.2nW 92.6% Peak Efficiency Power Management Unit for System Performance Scaling, Fast DVFS and Energy Minimization

A self-powered IoT system-on-chip (SoC) reduces power to sub-μw and employs multiple power-management techniques to trade-off ultra-low power (ULP), higher performance, smaller energy harvester footprint, and longer operating lifetime. Minimum Energy Point Tracking (MEPT) [1]–[4] keeps an SoC operating at the minimum energy point (MEP) to enhance system lifetime. Previous sample-and-hold MEPT schemes need frequent voltage comparisons and a high-frequency clock that increases power [2]. Current-ratio-based MEPT relies on specialized CMOS technology for body-bias tuning [3]. A switched-capacitor-based MEPT can achieve energy minimization at a targeted performance [4], but it uses a 30MHz clock witμW power consumption and low power efficiency. For ULP IoT applications, SoCs need to have ultra-low quiescent power, high efficiency for energy delivery, performance scaling based on available energy, and energy minimization to increase system lifetime. In this work, we propose an ULP IoT SoC with a triple-mode power management unit (PMU) that integrates energy-performance scaling, event-driven fast DVFS, and MEPT features to improve the system energy efficiency, as shown in Fig. 13.8.1. This work achieves a minimum 194nW power consumption for the SoC and 5.2nW quiescent power for the PMU with a 92.6% peak efficiency and >10 4 dynamic range. The timing waveform in Fig. 13.8.1 (bottom), demonstrates the transition of the three modes including energy aware (EA), performance aware (PA), and MEPT based on event priority and input voltage level which reflects the energy availability. As such, the system energy consumption and performance could be well-balanced based on both the input and output conditions.

self-powered IoT system-on-chip (SoC)↗
DOE OSTI2020

Current Source Inverter Based Large Constant Power Speed Ratio SPM Machine Drive for Traction Applications

A high-performance surface permanent magnet (SPM) machine drive with an extended constant power speed ratio is proposed using a current source inverter (CSI) for a traction application. The constant-power operation regions of an SPM machine can be extended in an appealing fashion by taking advantage of the output voltage boost capability of the CSI. The CSI is naturally a boost-type converter, in contrast to the voltage source inverter (VSI) which has buck-type characteristics. To investigate the value of the CSI voltage boost feature, a new traction motor with higher rated voltage and lower rated current has been designed and compared to the motor that would be used with a VSI. The lower CSI current makes it possible to reduce the mass of the inverter and output power cable, benefiting power density and cost reduction. The SPM machine is modeled in the synchronous reference frame including the effect of the ac filter capacitors at the CSI output terminals. The capability of extending the speed range of the proposed motor is verified via closed-form analysis and FEA simulation, and its performance characteristics are compared with those of a VSI-based SPM motor of the same type.

42 ENGINEERING↗
DOE OSTI2025

Inverse Segmented Motor Drive Using Dual ANPC Inverters for Common-Mode Voltage and Neutral-Point Current Cancellation

This article proposes an inverse segmented motor drive (SgMD) utilizing dual active neutral point clamped (ANPC) inverters. In the proposed configuration, the neutral point current and common-mode (CM) voltage is topologically canceled, achieving zero total neutral point current and CM voltage under ideal conditions. Also, the zero total neutral point current minimizes the neutral point voltage imbalance in ANPC inverters. The mechanisms behind neutral point current and CM voltage cancellation in the proposed inverse SgMD are first introduced. The modifications to the motor windings for implementing the inverse SgMD are explained, showing that a standard motor can be readily adapted for the proposed configuration. A space vector modulation (SVM) scheme tailored for the proposed topology is presented, along with a carrier-based implementation. Simulation results validate that the proposed topology can achieve zero total CM voltage and neutral point current. It is also shown that the proposed inverse SgMD can reduce neutral point voltage fluctuation by about 90% and RMS current stress in the dc-link capacitors by about 43% compared to the conventional SgMD.

Lee, Sangwhee [ORNL] (ORCID:0000000335490057)↗
DOE OSTI2020

Estimation, Minimization, and Validation of Commutation Loop Inductance for a 135-kW SiC EV Traction Inverter

With growing interests in low inductance SiC based power module packaging, it is vital to focus on system level design aspects to facilitate easy integration of the modules and reap system level benefits. To effectively utilize the low inductance modules, busbar and interconnects should also be designed with low stray inductances. A wholistic investigation of the flux path and flux cancellations in the module-busbar assembly which as differentially coupled series inductors is thus mandatory for a system level design. This work presents a busbar design which can be adopted to effectively integrate the CREE’s low inductance 1.2 kV/1.7 kV SiC power modules. The paper also proposes a novel measurement technique to measure the inductance of the modulebusbar assembly as a whole rather than deducing it from individual components. The inductance of the overall commutation loop of the inverter which encompasses the SiC power module, interconnects and PCB busbar have been estimated using finite element analysis (FEA). Furthermore, insights gained from FEA provided the guidelines to decide on the placement of the decoupling capacitors in the busbar to minimize the overall commutation loop inductance from 12.8 nH to 7.4 nH which resulted in significant reduction in the device voltage overshoot. The simulation results have been validated through measurements using an impedance analyzer with less than 5% difference between extracted loop inductance from FEA and measurements. The bus bar design study and the measurement technique discussed in this paper, can be easily extended to other power module packages. Finally, the 135 kW inverter has been compared to a similar highpower inverter utilizing a laminated busbar to highlight the performance of the former.

42 ENGINEERING↗
DOE OSTI2020

Methodology of Low Inductance Busbar Design for Three-Level Converters

Three-level (3L) converters are more susceptible to parasitics compared with two-level converters because of their complicated structure with multiple switching loops. In this article, the methodology of busbar layout design for 3L converters based on the magnetic cancellation effect is presented. The methodology can fit for 3L converters with symmetric and asymmetric configurations. A detailed design example is provided for a high-power 3L-active neutral point clamped (ANPC) converter, which includes the module selection, busbar layout, and dc-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. Furthermore, the results match with each other, and the inductances of short and long loops are 6.5 and 17.5 nH, respectively, which are significantly lower than the busbars of NPC-type converters in other references.

42 ENGINEERING↗
DOE OSTI2021

A Generic Two-Vector Model Predictive Control for Hybrid Multilevel Converters

In this article, a generic two-vector model predictive control (TV-MPC) strategy is proposed for the hybrid multilevel converters (HMCs). The proposed method selects two optimal voltage vectors among all the vector candidates using a geometric positioning approach to reduce the computational burden, which is a common issue in the existing MPC methods for HMC. Then duty cycles of the two selected vectors are optimized to minimize the current tracking error, such that the current tracking performance can be enhanced compared with the conventional MPC. In addition, the voltages of the floating dc capacitors can be balanced by evaluating all switching sequences that belong to the optimal voltage vectors with optimal duty cycles. Here, the concept of the proposed TV-MPC is generic and applicable for any HMCs. A typical HMC based on active neutral-point-clamped topology is adopted as a case study in this work. Comprehensive simulation and experimental studies are performed on an all silicon-carbide HMC prototype to validate the effectiveness of the proposed control scheme.

42 ENGINEERING↗
DOE OSTI2021

A Phase-Disposition PWM Enabled Model Predictive Control for a Nine-Level Inner-Interleaved Hybrid Multilevel Converter

This article brings forward a phase-disposition pulse width modulation enabled model predictive control (PDPWM-MPC) for a nine-level inner-interleaved hybrid multilevel converter (9L-IHMC). Firstly, three layers of virtual space vector diagrams (VSVD) are established based on the sign patterns of the original and virtual reference vectors in the abcframe, respectively, to achieve the phase-disposition pulse width modulation (PD-PWM) in a non-independent three-phase way. Then, three adjacent virtual vectors in the third-layer VSVD, together with their optimized duty cycles, are applied to guarantee the optimal current tracking. Finally, through the use of the duty cycle alternation approach, dc-link and floating capacitors voltages are balanced and circulating currents are mitigated as well. The proposed PDPWM-MPC can not only enable the decoupling of the low-and high-frequency stages in the 9L-IHMC, but also reduce both output current ripples and computational burden. In addition, it can achieve a constant equivalent switching frequency and address the disproportion of power losses associated with the PD-PWM. Here, both simulations and experiments on a silicon carbide device-based prototype substantiate the effectiveness of the proposed control strategy.

42 ENGINEERING↗
DOE OSTI2024

Data-Driven Digital Twin for Reliability Assessment of DC/DC Buck Converter

In commercial applications, the operation of DC/DC converters significantly impacts overall system performance and long-term reliability. This study introduces a data-driven digital twin (DT) approach for estimating critical degradation parameters of DC/DC BUCK converter under steady-state condition. Initially, a circuit-level MATLAB/Simulink digital model (DM C ) is refined against a hardware prototype’s switching model dataset using offline particle swarm optimization. The optimized digital model’s steady-state response is then verified with its average model response while varying the duty and load. Subsequently, degradation profiles are imposed on the inductor, capacitor, MOSFET in the DMC. A large dataset is generated from this model, allowing training, validation, and testing of machine learning (ML) models for component health regression tasks. The proposed method employs random forest ML models, achieving impressive regression results with a squared R value as high as 0.99978 and a root mean square error of 4.2× 10 –6 . The method is further validated on a medium power level DC/DC BUCK prototype with varying load conditions, and includes the analysis of MOSFET’s on-resistance under degradation conditions. This data-driven DT method shows promise for identifying parasitic degradation and ohmic loss parameters, enhancing converter reliability assessments in a non-invasive, generalized, and computationally efficient manner.

14 SOLAR ENERGY↗
DOE OSTI2023

Power Conversion Systems Enabled by SiC BiDFET Device

The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. Furthermore, the matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac-ac and ac dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.

42 ENGINEERING↗
DOE OSTI2021

Event Cause Analysis in Distribution Networks using Synchro Waveform Measurements

This paper presents a machine learning method for event cause analysis to enhance situational awareness in distribution networks. The data streams are captured using time-synchronized high sampling rates synchro waveform measurement units (SWMU). The proposed method is formulated based on a machine learning method, the convolutional neural network (CNN). This method is capable of capturing the spatiotemporal feature of the measurements effectively and perform the event cause analysis. Several events are considered in this paper to encompass a range of possible events in real distribution networks, including capacitor bank switching, transformer energization, fault, and high impedance fault (HIF). The dataset for our study is generated using the real time digital simulator (RTDS) to simulate real-world events. The event cause analysis is performed using only one cycle of the voltage waveforms after the event is detected. The simulation results show the effectiveness of the proposed machine learning-based method compared to the state-of-the-art classifiers.

Niazazari, Iman↗
DOE OSTI2021

Probabilistic Voltage Sensitivity based Preemptive Voltage Monitoring in Unbalanced Distribution Networks

With increasing penetration of renewable energy and active consumers, control and management of power distribution networks has become challenging. Renewable energy sources can cause random voltage fluctuations as their output power depends on weather conditions. Conventional voltage control schemes such as tap changers and capacitor banks lack the foresight required to quickly alleviate voltage violations. Thus, there is an urgent need for effective approaches for predicting and mitigating voltage violations as a result of random fluctuations in power injections. This work proposes a novel voltage monitoring approach based on low-complexity, data-driven probabilistic voltage sensitivity analysis. The usefulness of this work is not only in predicting voltage violations in unbalanced distribution grids, but also in opening up the door for optimal voltage control. Using system data and forecasts, the proposed approach predicts the distribution of system node voltages which is then used to to identify nodes that may violate the nominal operational limits with high probability. The method is tested on the IEEE 37 node distribution system considering integrated distributed solar energy sources. The method is validated against the classic load flow based method and offers over 95% accuracy in predicting voltage violations.

Abujubbeh, Mohammad↗
DOE OSTI2021

Giant Polarization in Nanodielectrics

The relative permittivity of a material is a scaling factor for capacitors and the devices based upon them; the larger the relative permittivity, the greater the degree of miniaturization, or potential for energy storage. Materials with a relative permittivity than that of silicon nitride (approximately 7) are referred to as high-dielectric constant materials. Values of about 100 are typical in titanium dioxide rutile. Values of about 10,000 are observed in barium titanate in the region of the ferroelectric transition, which while impressive, is not very useful due to the strong temperature dependence. The observation of a relative permittivity of over 100,000 in the calcium copper titanate material sparked considerable interest because it showed little temperature dependence between 100 and 600 K over most of the radio-frequency range. Further investigation revealed that this material appears to be naturally nanotextured and that the colossal permittivity was likely due to the surface and/or internal barrier layer capacitance effect, although the issue is not settled. Unfortunately, the dielectric losses in this class materials are relatively high. A new strategy to achieve high dielectric permittivity with low loss involves using localized lattice defect states through ambipolar co-doping; these intrinsic defect complexes give rise to strong dipoles that are responsible for a relative permittivity of 10,000 with exceptionally low dielectric losses over most of the radio frequency range and excellent thermal stability.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2026

MIND-MAC: Multi-Level In-memory Quasi Non-Destructive MAC Operation in Compact 2T-nC FeRAM for Efficient DNN Accelerator

We present MIND-MAC, a compact 2T-nC FeRAM architecture that performs multi-level, quasi-non-destructive in-memory multiply–accumulate (MAC) for deep neural networks. By exploiting voltage-controlled partial domain switching in MFM capacitors and read-transistor amplification, the cell stores multi-bit weights and gates bit-serial inputs to produce an accumulated current on shared lines. We combine TCAD-extracted parasitics with experimentally calibrated ferroelectric models in SPICE to validate device-/circuit-level behavior, and validate multi-level sensing and QNRO with measurements on a fabricated 2T-3C test vehicle. An analytical system model maps MIND-MAC to a 6-GB main-memory in-memory compute (IMC) architecture and benchmarks VGG13 inference in 61.08 ms at 964.99 mJ. Results indicate high density, reduced rewrite overhead, and energy efficiency, positioning 2T-nC FeRAM as a promising IMC candidate for next-generation AI hardware.

36 MATERIALS SCIENCE↗
DOE OSTI2025

A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.

DAQ↗