Search NASA⌕ Search

SEARCH · Search NASA

Results for “gate”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 451 records · Page 25
All sourcesNASA NTRSDOE OSTI
NASA NTRS2020

Single-Event Testing of the Texas Instruments SNV54LVC00AW Quadruple 2-Input Positive-NAND Gates

The purpose of this testing was to characterize the Texas Instruments SNV54LVC00AW for single-event latchup (SEL) in support of a NASA GSFC flight program. The SNV54LVC00A quadruple 2-input positive-NAND gate. These devices were tested at the Berkeley Accelerator Space Effects (BASE) Facility at Lawrence Berkeley National Laboratory (LBNL) where they were irradiated with the 10 MeV/amu heavy ion cocktail.

Campola, Michael↗
NASA NTRS2020

Performance Evaluation of Isolated Gate Driver, ADuM4121, Under Exposure to Extreme Temperature

Electronics designed for use in space missions are expected to be exposed to harsh environment including radiation and extreme temperature, to name a few. Severe thermal swings are also encountered depending on planetary exploration, orbital orientation, and mission duration. Most commercial-off-the-shelf (COTS) devices are not designed to function under such extreme conditions and very little data exist on their performance outside their specified range of operation. In this work, the performance of an isolated gate driver for controlling power-level transistors, including gallium nitride (GaN) and silicon carbide (SiC) devices, was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance for potential use of this device in space exploration missions under extreme temperature conditions.

Boomer, Kristen↗
NASA NTRS1995

Fabrication and Performance of Planar Schottky Diodes with T-gate-like Anodes in 200 GHz Subharmonically-Pumped Waveguide Mixers

A T-gate-like structure has been developed, fabricated and tested as the anode for millimeter and submillimeter-wave Schottky diodes. The low parasitics of the T-anode diodes yield extremely high cutoff frequencies, making the diodes useable at frequencies well beyond 1 THz. The diodes were tested as an antiparallel-pair, integrated monolithically with microstrip circuitry on a quartz substrate, in a subharmonically pumped waveguide mixer. A double sideband noise temperature of 600 K with a conversion loss of 4.7 dB were measured at 200 GHz. This is believed to be the lowest noise temperature ever reported for a room temperature subharmonically-pumped Schottky diode mixer at this frequency.

Planar↗
NASA NTRS2009

Single-Event Gate Rupture and Single-Event Burnout Test Results Performed on Hi-Rel Fuji Power MOSFETs: 2SK4217, 2SK4152, 2SK4155, and 2SK4158

Several newly available Hi-Rel total dose hardened power MOSFETs manufactured by Fuji Electric Device Technology Co. Ltd (FDT) in conjunction with the Japan Aerospace Exploration Agency (JAXA) were tested for single-event gate rupture (SEGR) and single-event burnout (SEB). The safe-operating area (SOA) of the 2SK4217 (a 100 V rated device), 2SK4152 (130 V), 2SK4155 (200 V), and the 2SK4158 (250 V) were tested with silver (Ag) and xenon (Xe) ions having incident LETs of 42.2 and 53.1 MeV cm2/mg, respectively. Test results show these devices are comparable to currently available total dose hardened technology.

Selva, Luis E.↗
NASA NTRS2001

Heavy ion induced soft breakdown of thin gate oxides

Heavy ion induced soft and hard breakdown are investigated in thin gate oxides as a function of LET, fluence, and voltage applied during irradiation. It is found that post-irradiation oxide conduction is well described by the Sune quantum point contact model.

radiation↗
NASA NTRS2009

Mitigation selection and qualification recommendations for Xilinx Virtex, Virtex-II, and Virtex-4 field programmable gate arrays

This work discusses mitigation selection and qualification techniques for Xilinx reconfigurable field programmable gate arrays (FPGAs). The aim of the paper is to provide readers with a better understanding of the engineering/reliability/project cost relationship that occurs when developing a mitigation strategy for static random access memory (SRAM)-based FPGAs.

Allen, Gregory↗
NASA NTRS2024

Single-Event Effects Test Report Lattice Semiconductor, LCMXO3D-9400HC-5BG484I Field Programmable Gate Array

The purpose of this test was to characterize single event effects (SEE) in the LCMXO3D-9400HC-5BG484I, a low power and low density field programmable gate array (FPGA). The SEE concerns for the device that were investigated in this testing are single event upsets (SEUs) in the configuration static random-access memory (SRAM), SEUs in the FPGA fabric, single event latch up (SEL), and single event functional interrupts (SEFIs). Testing was conducted at Lawrence Berkeley National Laboratory (LBNL) on August 26th, 2024 and August 28th, 2024.

Adia M Wood↗
DOE OSTI2024

Field Programmable Gate Array Data Capture for Control Systems

Some Industrial Control Systems (ICS) networks are based on protocols such as Serial and Industrial Ethernet. These protocols currently have no existing cybersecurity monitoring tools, leaving a large gap in the cyber defense of critical infrastructure. In order to analyze such ICS traffic, it is first necessary to implement methods of capturing the ICS data. Whereas traditional methods of analyzing data would use microprocessors, the nature of high-speed analog data can be difficult to implement on such a versatile processor, as they are rather inefficient for doing a single task. Whereas Field Programmable Gate Arrays (FPGAs) provide an adequate tool in analyzing high speed data, as despite the lack of program versatility, Programmable Logic can implement a solution with minimal clock cycles, allowing time for each new packet of data to be captured before a new data sample is taken.

42 ENGINEERING↗
NASA NTRS2006

Single Event Effects Test Results for the Actel ProASIC Plus and Altera Stratix-II Field Programmable Gate Arrays

This work describes radiation testing of Actel's ProASIC Plus and Altera's Stratix-II FPGAs. The Actel Device Under Test (DUT) was a ProASIC Plus APA300-PQ208 nonvolatile, field reprogrammable device which is based on a 0.22micron flash-based LVCMOS technology. Limited investigation has taken place into flash based FPGA technologies, therefore this test served as a preliminary reference point for various SEE behaviors. The Altera DUT was a Stratix-II EP2S60F1020C4. Single Event Upset (SEU) and Single Event Latchup (SEL) were the focus of these studies. For the Actel, a latchup test was done at an effective LET of 75.0 MeV-sq cm/mg at room temperature, and no latchup was detected when irradiated to a total fluence of 1 x 10(exp 7) particles/sq cm. The Altera part was shown to latchup at room temperature.

heavy ions↗
NASA NTRS2006

Upset Characterization of the PowerPC405 Hard-core Processor Embedded in Virtex-II Pro Field Programmable Gate Arrays

Shown in this presentation are recent results for the upset susceptibility of the various types of memory elements in the embedded PowerPC405 in the Xilinx V2P40 FPGA. For critical flight designs where configuration upsets are mitigated effectively through appropriate design triplication and configuration scrubbing, these upsets of processor elements can dominate the system error rate. Data from irradiations with both protons and heavy ions are given and compared using available models.

radiation effects↗
NASA NTRS2008

Current Leakage Evolution in Partially Gate Raptured Power MOSFETs

It has been observed that power MOSFETs can experience an SEGR and continue to function with altered parameters. We propose that there are three different types of SEGR modes; the micro-break, the thermal runaway, and the avalanche breakdown. Data that demonstrates these stages of device failure are presented as well as a proposed model for the micro-break. Brief discussions of the other modes, based on analysis combined with our interpretations of the older literature, are also given.

metal oxide semiconductor field-effect transistors↗
NASA NTRS2015

Using Classical Reliability Models and Single Event Upset (SEU) Data to Determine Optimum Implementation Schemes for Triple Modular Redundancy (TMR) in SRAM-Based Field Programmable Gate Array (FPGA) Devices

Space applications are complex systems that require intricate trade analyses for optimum implementations. We focus on a subset of the trade process, using classical reliability theory and SEU data, to illustrate appropriate TMR scheme selection.

Field Programmable Gate Array (FPGA)↗
NASA NTRS2016

Field Programmable Gate Aray (FPGA) Radiation Data: All Data is Not Equal

Electronic parts (integrated circuits) have grown in complexity such that determining all failure modes and risks based on single particle event radiation testing is impossible. In this presentation, the authors will present why this is so and provide some realism on what this means to FPGAs. Its all about understanding actual risks and not making assumptions.

radiation testing↗
NASA NTRS2018

NASA Electronic Parts and Packaging (NEPP) Field Programmable Gate Array (FPGA) Single Event Effects (SEE) Test Guideline Update

The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.

Test guidelines↗
NASA NTRS2018

NASA Electronic Parts and Packaging Field Programmable Gate Array Single Event Effects Test Guideline Update

The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.

Field Programmable Gate Array (FPGA)↗