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A multistation, multichannel cross correlation processor using the 250 k bit to 4 M bit recording format is discussed. The design is modular, using bit sliced microprocessors to perform the routine calculations for phase and delay on a per station basis, as well as for fractional bit shift correction and Fourier transformation of the correlation coefficients on a per baseline basis.
The Delta-T Processor (DTP) computes the instantaneous downtrack error in a specified orbiter onboard navigation state vector recovered via downlink telemetry. The downtrack error, expressed in units of time, is computed based on current incoming Earth based range and Doppler navigation tracking data and the ground selected onboard navigation state vector. The computed time difference when used to modify the timetag of the vector used for onboard navigation reduces the instantaneous downtrack error in this vector to within the threshold of the DTP, the input data, and the onboard software. This threshold is currently estimated to be approximately 2 to 4 nautical miles. The DTP is not restricted to using only onboard vectors. Any vector, either input via the manual entry device or accessible via the vector administration table, may be used. The DTP does not require that both data types be available.
A long-term experimental development program conducted at Goddard Space Flight Center to implement an ultrahigh-speed data processing system known as the Massively Parallel Processor (MPP) is described. The MPP is a single instruction multiple data stream computer designed to perform logical, integer, and floating point arithmetic operations on variable word length data. Information is presented on system architecture, the system configuration, the array unit architecture, individual processing units, and expected operating rates for several image processing applications (including the processing of Landsat data).
The massively parallel processor (MPP) system is designed to process satellite imagery at high rates. A large number (16,384) of processing elements (PE's) are configured in a square array. For optimum performance on operands of arbitrary length, processing is performed in a bit-serial manner. On 8-bit integer data, addition can occur at 6553 million operations per second (MOPS) and multiplication at 1861 MOPS. On 32-bit floating-point data, addition can occur at 430 MOPS and multiplication at 216 MOPS.
Processor has automatic range switching and continuous readout over eight decades. Comparator output switches logarithmic converter to detector of interest and enables blinder grid to protect more-sensitive detector when operating in high-input range. Could be used to process any wide-varying signal that is to be read on a limited-range recording device such as a strip-chart recorder.
Launch processing for Space Shuttle is checked out, controlled, and monitored with new system. Entire system can be exercised by two computer programs--one in master console and other in each of operations consoles. Control program in each operations console detects change in status and begins task initiation. All of front-end processors are exercised from consoles through common data buffer, and all data are logged to processed-data recorder for posttest analysis.
The TAPMRG processor merges or copies data files from one or more tapes onto a single output tape.
The function of the EROS processor is to allow a user to select a specific area from a full frame LANDSAT image which is written on tape in the EROS format. The area of interest is read from the EROS formatted tape and converted to the JSC Universal format and written onto another tape. This tape can then be read by the IMDACS processing system and normal analysis can be performed.
The patch image processor extracts patches in various size (32 x 32, 64 x 64, 128 x 128, and 256 x 256 pixels) from full frame LANDSAT imagery data. With the patches that are extracted, a patch image mosaic is created in the image processing system, IMDACS, format.
Basic engineering data regarding the Interim Digital SAR Processor (IDP) and the digitally correlated Seasat synthetic aperature radar (SAR) imagery are presented. The correlation function and IDP hardware/software configuration are described, and a preliminary performance assessment presented. The geometric and radiometric characteristics, with special emphasis on those peculiar to the IDP produced imagery, are described.
A correlated quadruple sampling processor for improved signal-to-noise ratio in the output of a charge-coupled device (CCD) is comprised of: switching means for momentarily clamping a CCD signal line at a first reference level A before a CCD data pulse and then obtaining a first data sample B with respect to the reference A during a CCD data pulse, and storing the positive sample B-A; switching means for momentarily clamping the CCD signal line a second time at the level C during the presence of the CCD data pulse and then obtaining a second data sample D with respect to the reference level C after the CCD data pulse, and storing the negative sample D-C; and means for obtaining the difference between the stored samples +(B-A) and -(D-C), thus increasing the net signal amplitude by a factor of about 2 while the noise would be increased by only a factor of square root of 2 since there will be no correlation in the noise between the double samples +(B-A) and -(D-C) effectively added.
Because of the high data-rate requirements, a practical system capable of collecting seismic information in the field and relaying it, via satellite, to a central collection point is not yet available. A seismic signal processor has been developed and tested for use with the NOAA/GOES satellite data collection system. Performance tests on recorded, as well as real time, short period signals indicate that the event recognition technique used is nearly perfect in its rejection of environmental noise and other non-seismic signals and that, with the use of solid state buffer memories, data can be acquired in many swarm situations. The design of a complete field data collection platform is discussed based on the prototype evaluation.
The architecture of a microprocessor-based packet switch using three processors for use on-board satellites is presented. The operation of the switch involves three distinct functions, namely, the input, the routing and the output functions. Each of these functions is performed by one of the three microprocessors. The operation of the switch along with those of the corresponding software routines are explained. An expression for the throughput is presented. A queue theoretic model of the switch is developed. Analytical expressions for the overall average response time at the various queues are obtained. A number of graphs showing the average response time as a function of some parameters of the switch are also presented.
A 30-cm-diameter Hg ion thruster similar in design to the J-series thruster was operated at fixed conditions with only five power supplies and was throttled over the baseline power range with six supplies. An analysis of the functional model power processor showed that the component mass and parts count would be reduced by about 14 and 35% respectively, and the electrical efficiency would be increased about 1.5% by replacing power supplies with relays. By introducing new circuit designs, additional reductions in the component mass and parts, as well as an increase in electrical efficiency would be expected. The impact on thruster performance of reducing the number of power supplies was to lower the propellant utilization efficiency about 1.0% and raise the electrical efficiency values from 0.2 to 1.3% over the throttle range.
This paper describes algorithms for efficiently computing inventory estimates from satellite based images. The algorithms incorporate a one dimensional feature extraction which optimizes the pairwise sum of Fisher distances. Biases are eliminated with a premultiplication by the inverse of the analytically derived error matrix. The technique is demonstrated with a numerical example using statistics obtained from an actual Landsat scene. Attention was given to implementation of the Massively Parallel processor (MPP). A timing analysis demonstrates that the inventory estimation can be performed an order of magnitude faster on the MPP than on a conventional serial machine.
Processor under development continuously generates pure silicon and separates it from reaction by-products. Silicon separator/collector intercepts impinging jet of reaction products and selectively funnels silicon into larger collector. Salt byproduct is removed by tubular condenser held at 1,000 degrees C, and then flows into collector, where it solidifies. Vacuum locks permit periodic salt removal without disturbing continuous operation.
An automatic correlation plane processor that can rapidly acquire, identify, and locate the autocorrelation outputs of a bank of multiple optical matched filters is described. The read-only memory (ROM) stored digital silhouette of each image associated with each matched filter allows TV video to be used to collect image energy to provide accurate normalization of autocorrelations. The resulting normalized autocorrelations are independent of the illumination of the matched input. Deviation from unity of a normalized correlation can be used as a confidence measure of correct image identification. Analog preprocessing circuits permit digital conversion and random access memory (RAM) storage of those video signals with the correct amplitude, pulse width, rising slope, and falling slope. TV synchronized addressing of 3 RAMs permits on-line storage of: (1) the maximum unnormalized amplitude, (2) the image x location, and (3) the image y location of the output of each of up to 99 matched filters. A fourth RAM stores all normalized correlations. A normalization approach, normalization for cross correlations, a system's description with block diagrams, and system's applications are discussed.
An iterative optical vector-matrix multiplier with a microprocessor-controlled feedback loop capable of performing a wealth of diverse operations was described. A survey and description of many of its operations demonstrates the versatility and flexibility of this class of optical processor and its use in diverse applications. General operations described include: linear difference and differential equations, linear algebraic equations, matrix equations, matrix inversion, nonlinear matrix equations, deconvolution and eigenvalue and eigenvector computations. Engineering applications being addressed for these different operations and for the IOP are: adaptive phased-array radar, time-dependent system modeling, deconvolution and optimal control.