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Progress on NASA’s Safe and Precise Landing Integrated Capabilities Evolution (SPLICE) project continues, specifically with this development of the Descent and Landing Computer (DLC). One of the DLC’s primary contributions as a SPLICE technology is its implementation of algorithms and operation of sensors to autonomously guide a spacecraft in performing more precise and safer landings on celestial bodies such as the Moon and Mars [1]. The second iteration of the DLC is known as the Engineering Test Unit (ETU) and one of its desired functionalities is the ability to preserve the fidelity of the system’s boot file through the use of memory scrubbing [2]. The ETU has two primary boards, one for housing a Multi-Processor System on a Chip (MPSoC) and the other for housing a Xilinx Kintex Ultrascale FPGA*. To emulate a memory scrubbing function implemented on the ETU’s FPGA board, the design and testing of a software application was performed on a Xilinx KCU105 FPGA evaluation board. The memory scrubbing application had to meet certain key criteria such as (1) properly utilize with the flash memory’s Serial Peripheral Interface (SPI) to read, write, and erase flash memory properly, (2) be able to detect arbitrarily large or small amounts of bit-errors, (3) be able to correct all detected errors, and (4) perform memory scrubbing indefinitely and autonomously. A prototype implementation was constructed and tested, demonstrating successful detection and correction of bit errors in multiple configurations. In the form of burst errors or singular bit flips, and in amounts of errors ranging from one to fifteen (per 256 Bytes), the application was successful in preserving memory fidelity.