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At least 487 records · Page 27

Evaluation of a Programmable Voltage-Controlled MEMS Oscillator, Type SiT3701, Over a Wide Temperature Range

Semiconductor chips based on MEMS (Micro-Electro-Mechanical Systems) technology, such as sensors, transducers, and actuators, are becoming widely used in today s electronics due to their high performance, low power consumption, tolerance to shock and vibration, and immunity to electro-static discharge. In addition, the MEMS fabrication process allows for the miniaturization of individual chips as well as the integration of various electronic circuits into one module, such as system-on-a-chip. These measures would simplify overall system design, reduce parts count and interface, improve reliability, and reduce cost; and they would meet requirements of systems destined for use in space exploration missions. In this work, the performance of a recently-developed MEMS voltage-controlled oscillator was evaluated under a wide temperature range. Operation of this new commercial-off-the-shelf (COTS) device was also assessed under thermal cycling to address some operational conditions of the space environment

Patterson, Richard↗

Field Programmable Gate Array Apparatus, Method, and Computer Program

An apparatus is provided that includes a plurality of modules, a plurality of memory banks, and a multiplexor. Each module includes at least one agent that interfaces between a module and a memory bank. Each memory bank includes an arbiter that interfaces between the at least one agent of each module and the memory bank. The multiplexor is configured to assign data paths between the at least one agent of each module and a corresponding arbiter of each memory bank based on the assigned data path. The at least one agent of each module is configured to read data from the corresponding arbiter of the memory bank or write modified data to the corresponding arbiter of the memory bank.

Morfopoulos, Arin C.↗

Programmable Remapper with Single Flow Architecture

An apparatus for image processing comprising a camera for receiving an original visual image and transforming the original visual image into an analog image, a first converter for transforming the analog image of the camera to a digital image, a processor having a single flow architecture for receiving the digital image and producing, with a single algorithm, an output image, a second converter for transforming the digital image of the processor to an analog image, and a viewer for receiving the analog image, transforming the analog image into a transformed visual image for observing the transformations applied to the original visual image. The processor comprises one or more subprocessors for the parallel reception of a digital image for producing an output matrix of the transformed visual image. More particularly, the processor comprises a plurality of subprocessors for receiving in parallel and transforming the digital image for producing a matrix of the transformed visual image, and an output interface means for receiving the respective portions of the transformed visual image from the respective subprocessor for producing an output matrix of the transformed visual image.

Fisher, Timothy E.↗

Programmable Logic Device (PLD) Design Description for the Integrated Power, Avionics, and Software (iPAS) Space Telecommunications Radio System (STRS) Radio

The Space Telecommunications Radio System (STRS) provides a common, consistent framework for software defined radios (SDRs) to abstract the application software from the radio platform hardware. The STRS standard aims to reduce the cost and risk of using complex, configurable and reprogrammable radio systems across NASA missions. To promote the use of the STRS architecture for future NASA advanced exploration missions, NASA Glenn Research Center (GRC) developed an STRS compliant SDR on a radio platform used by the Advance Exploration System program at the Johnson Space Center (JSC) in their Integrated Power, Avionics, and Software (iPAS) laboratory. At the conclusion of the development, the software and hardware description language (HDL) code was delivered to JSC for their use in their iPAS test bed to get hands-on experience with the STRS standard, and for development of their own STRS Waveforms on the now STRS compliant platform.The iPAS STRS Radio was implemented on the Reconfigurable, Intelligently-Adaptive Communication System (RIACS) platform, currently being used for radio development at JSC. The platform consists of a Xilinx ML605 Virtex-6 FPGA board, an Analog Devices FMCOMMS1-EBZ RF transceiver board, and an Embedded PC (Axiomtek eBox 620-110-FL) running the Ubuntu 12.4 operating system. Figure 1 shows the RIACS platform hardware. The result of this development is a very low cost STRS compliant platform that can be used for waveform developments for multiple applications.The purpose of this document is to describe the design of the HDL code for the FPGA portion of the iPAS STRS Radio particularly the design of the FPGA wrapper and the test waveform.

VHDL↗

Programmable Spectral Source and Design Tool for 3D Imaging Using Complementary Bandpass Filters

An endoscopic illumination system for illuminating a subject for stereoscopic image capture, includes a light source which outputs light; a first complementary multiband bandpass filter (CMBF) and a second CMBF, the first and second CMBFs being situated in first and second light paths, respectively, where the first CMBF and the second CMBF filter the light incident thereupon to output filtered light; and a camera which captures video images of the subject and generates corresponding video information, the camera receiving light reflected from the subject and passing through a pupil CMBF pair and a detection lens. The pupil CMBF includes a first pupil CMBF and a second pupil CMBF, the first pupil CMBF being identical to the first CMBF and the second pupil CMBF being identical to the second CMBF, and the detection lens includes one unpartitioned section that covers both the first pupil CMBF and the second pupil CMBF.

Shahinian, Hrayr Karnig↗

A Single-Chip Programmable Digital CMOS Imager with Enhanced Low Light Detection Capability

Low-power, low-cost, miniature and integrated digital imaging systems are expected to be widely used in consumer electronics in the near future. While CMOS technology has been responsible for the phenomenal growth in consumer electronics, micro-porcessors, memory, audio systems, and radio-frequency circuits (e.g. cellular phones), till recently, the video technology remained outside this mainstream.

digital↗

Programmable Multiresolution CMOS Active Pixel Sensor

CMOS active pixel sensors (APS) allow the flexibility of placing signal processing circuitry on the imaging focal plane. The multiresolution CMOS APS can perform block averaging on-chip to eliminate the off-chip software intensive image processing. This 128 x 128 APS array can be read out at any user-defined resolution by configuring a set of digital shift registers. The resolution frame rate is 30 Hz with higher rates for all other image resolutions.

APS↗

The Dark Energy Survey Supernova Programme: Modelling Selection Efficiency and Observed Core-collapse Supernova Contamination

The analysis of current and future cosmological surveys of Type Ia supernovae (SNe Ia) at high redshift depends on the accuratephotometric classification of the SN events detected. Generating realistic simulations of photometric SN surveys constitutes anessential step for training and testing photometric classification algorithms, and for correcting biases introduced by selectioneffects and contamination arising from core-collapse SNe in the photometric SN Ia samples. We use published SN time-seriesspectrophotometric templates, rates, luminosity functions, and empirical relationships between SNe and their host galaxies toconstruct a framework for simulating photometric SN surveys. We present this framework in the context of the Dark EnergySurvey (DES) 5-yr photometric SN sample, comparing our simulations of DES with the observed DES transient populations.We demonstrate excellent agreement in many distributions, including Hubble residuals, between our simulations and data.We estimate the core collapse fraction expected in the DES SN sample after selection requirements are applied and beforephotometric classification. After testing different modelling choices and astrophysical assumptions underlying our simulation,we find that the predicted contamination varies from 7.2 to 11.7 per cent, with an average of 8.8 per cent and an r.m.s. of 1.1 percent. Our simulations are the first to reproduce the observed photometric SN and host galaxy properties in high-redshift surveyswithout fine-tuning the input parameters. The simulation methods presented here will be a critical component of the cosmologyanalysis of the DES photometric SN Ia sample: correcting for biases arising from contamination, and evaluating the associatedsystematic uncertainty.

M Vincenzi↗