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Modified NRZ (non-return-to-zero) code immunizes record and playback systems against dc drift and bit slippage. In order to maximize bit packing density improved code called J-NRZ gives 100 percent NRZ efficiently and solves DC drift problem by adding check bits in specified format when long string is encountered. Remainder of data stream is encoded in NRZ format.
A 4-bit and a 3-bit adder are described which can be implemented under special hardware restrictions. The chip to be used is field-programmable logic array (FPLA) with 12 input lines, 50 AND gates inside, and output through only 6 OR gates. The context in which it is being used requires an enable function which can suppress one of the two numbers to be added. The 3-bit enabled adder is compatible with lookahead-carry mechanizations using the 74S182.
The viewpoints of design, programming, and application of the transportation network (TN) is presented. The TN is a programmable combinational logic network that connects 521 memory modules to 512 processors. The unscrambling of p-ordered vectors to 1-ordered vectors in one cycle is described. The TN design is based upon the concept of cyclic groups from abstract algebra and primitive roots and indices from number theory. The programming of the TN is very simple, requiring only 20 bits: 10 bits for offset control and 10 bits for barrel switch shift control. This simple control is executed by the control unit (CU), not the processors. Any memory access by a processor must be coordinated with the CU and wait for all other processors to come to a synchronization point. These wait and synchronization events can be a degradation in performance to a computation. The TN application is for multidimensional data manipulation, matrix processing, and data sorting, and can also perform a perfect shuffle. Unlike other more complicated and powerful permutation networks, the TN cannot, if possible at all, unscramble non-p-ordered vectors in one cycle.
The appearance of nonmetallic structural materials and microelectronics in aircraft design has resulted in a need for better knowledge of hazardous environments such as lightning and the effects these environments have on the aircraft. This feasibility study was performed to determine the lightning parameters in the greatest need of clarification and the performance requirements of equipment necessary to sense and record these parameters on an instrumented flight research aircraft. It was found that electric field rate of change, lightning currents, and induced voltages in aircraft wiring are the parameters of greatest importance. Flat-plate electric field sensors and resistive current shunts are proposed for electric field and current sensors, to provide direct measurements of these parameters. Six bit analog-to-digital signal conversion at a 5 nanosecond sampling rate, short-term storage of 85000 bits and long term storage of 5 x 10 to the 7th power bits of electric field, current and induced voltage data on the airplane are proposed, with readout and further analysis to be accomplished on the ground. A NASA F-106B was found to be suitable for use as the research aircraft because it has a minimum number of possible lightning attachment points, space for the necessary instrumentation, and appears to meet operational requirements. Safety considerations are also presented.
Research work is described that was carried out to develop adaptive delta modulators (ADM) capable of encoding black-and-white and color video signals in the presence of high bit error rates. These were a one-dimensional ADM capable of encoding black-and-white pictures and transmitting digitally encoded voice without increase in bandwidth; an ADM capable of encoding color video signals; and an ADM capable of encoding field-sequential color. For each of these three units, the bit rate could be adjusted within the range from 6 to 24 Mbits/sec. The effects of the bit rate and channel errors on the response of the picture are examined.
Because of the interlaced television scan, the two fields that form an interlaced video frame are generated 1/60 of a second apart. If the two fields are compressed independently, the correlation between adjacent lines is unused. The transmission rate can be reduced by using a field memory to form an interlaced frame. Four test images were processed as fields and as interlaced frames, using both theoretical and experimental compression designs. For comparable mean-square error and subjective appearance, field compression requires about one-half bit per sample more than frame compression. However, the overall transmission rate - the number of bits per image times the number of images per second - is more meaningful than the number of bits per sample. When transform compression at low transmission rates merges the adjacent lines, frame compression becomes similar to field repeating, and the memory can be reduced.
DIDCS is an interactive image display and manipulation system that is used for a variety of astronomical image reduction and analysis operations. The hardware system consists of a PDP 11/40 main frame with 32K of 16-bit core memory; 96K of 16-bit MOS memory; two 9 track 800 BPI tape drives; eight 2.5 million byte RKO5 type disk packs, three user terminals, and a COMTAL 8000-S display system which has sufficient memory to store and display three 512 x 512 x 8 bit images along with an overlay plane and function table for each image, a pseudo color table and the capability for displaying true color. The software system is based around the language FORTH, which will permit an open ended dictionary of user level words for image analyses and display. A description of the hardware and software systems will be presented along with examples of the types of astronomical research that are being performed. Also a short discussion of the commonality and exchange of this type of image analysis system will be given.
Versatile receiver processes data at variety of rates and code formats. Functions performed are: bit detection, NRZ-L conversion, frame synchronization (with programmable word length), bit-sync acquisition and tracking, error-curve normalization, lock detection, half-bit-ambiguity resolution, and data-rate tracking.
The major architectural features of the ILLIAC IV large scale, array processor are summarized along with their applicability to image processing. Several image processing algorithms are considered, including multispectral classification, texture feature extraction, two-dimensional Fourier transform, and synthetic aperture radar processing. The basic parallelism of the ILLIAC IV (64 processing elements acting in lock-step) is usually fully utilized by the image processing applications. The major architectural aspect of the system with respect to image processing is the relatively small local scratch-pad memory and the long latency time to access the main storage device. The major precision used for the image processing applications is the 32-bit floating point, given a choice of 8-bit integers and 64-bit floating point.
The massively parallel processor (MPP) system is designed to process satellite imagery at high rates. A large number (16,384) of processing elements (PE's) are configured in a square array. For optimum performance on operands of arbitrary length, processing is performed in a bit-serial manner. On 8-bit integer data, addition can occur at 6553 million operations per second (MOPS) and multiplication at 1861 MOPS. On 32-bit floating-point data, addition can occur at 430 MOPS and multiplication at 216 MOPS.
Imperfect carrier reference causes a degradation in detection performance in coherent communication systems. A measure of this degradation is the radio loss, which is the amount of increase in data signal to noise ratio (SNR) per bit required to achieve the same bit error rate when carrier reference is perfect. Performance analysis and numerical results are obtained for the Voyager high rate telemetry link with maximum likelihood convolutional decoding. The arraying of antennas provides not only improved performance due to an increase in effective antenna aperture, but also a decrease in radio loss with respect to a single antenna. This telemetry link performance improvement is a function of the carrier loop SNR and data bit error rate. When the carrier loop SNR's are low, it provides a significant improvement in the telemetry link performance since the decrease in radio loss with respect to a single station is substantial.
The use of the CYBER 203 vector computer for thermal analysis is investigated. Strengths of the CYBER 203 include the ability to perform, in vector mode using a 64 bit word, 50 million floating point operations per second (MFLOPS) for addition and subtraction, 25 MFLOPS for multiplication and 12.5 MFLOPS for division. The speed of scalar operation is comparable to that of a CDC 7600 and is some 2 to 3 times faster than Langley's CYBER 175s. The CYBER 203 has 1,048,576 64-bit words of real memory with an 80 nanosecond (nsec) access time. Memory is bit addressable and provides single error correction, double error detection (SECDED) capability. The virtual memory capability handles data in either 512 or 65,536 word pages. The machine has 256 registers with a 40 nsec access time. The weaknesses of the CYBER 203 include the amount of vector operation overhead and some data storage limitations. In vector operations there is a considerable amount of time before a single result is produced so that vector calculation speed is slower than scalar operation for short vectors.
A general algorithm for testing digital computer memory is presented. The test checks that (1) every bit can be cleared and set in each memory work, and (2) bits are not erroneously cleared and/or set elsewhere in memory at the same time. The algorithm can be applied to any size memory block and any size memory word. It is concise and efficient, requiring the very few cycles through memory. For example, a test of 16-bit-word-size memory requries only 384 cycles through memory. Approximately 15 seconds were required to test a 32K block of such memory, using a microcomputer having a cycle time of 133 nanoseconds.
The telemetry performance of an arrayed receiver system, including radio losses, is often given by a family of curves giving bit error rate vs bit SNR, with tracking loop SNR at one receiver held constant along each curve. This study shows how to process this information into a more compact, useful format in which the minimal total signal power and optimal carrier suppression, for a given fixed bit error rate, are plotted vs data rate. Examples for baseband-only combining are given. When appropriate dimensionless variables are used for plotting, receiver arrays with different numbers of antennas and different threshold tracking loop bandwidths look much alike, and a universal curve for optimal carrier suppression emerges.
The objectives of this article are to investigate and analyze the problem of combining symbol streams from many Deep Space Network stations to enhance bit signal-to-noise ratio and to compare the performance of this combining technique with baseband combining. Symbol stream combining (SSC) has some advantages and some disadvantages over baseband combining (BBC). The SSC suffers almost no loss in combining the digital data and no loss due to the transmission of the digital data by microwave links between the stations. The BBC suffers 0.2 dB loss due to alignment and combining the IF signals and 0.2 dB loss due to transmission of signals by microwave links. On the other hand, the losses in the subcarrier demodulation assembly (SDA) and in the symbol synchronization assembly (SSA) for SSC are more than the losses in the SDA and SSA for BBC. It is shown that SSC outperforms BBC by about 0.35 dB (in terms of the required bit energy-to-noise spectral density for a bit error rate of 1,000) for an array of three DSN antennas, namely 64 m, 34m(T/R) and 34m(R).
A correlation-simulation program for processing Seasat SAR data is presented, featuring the use of FORTRAN code to allow simple transference to another computer. The highest attainable azimuthal resolution for Seasat SAR experiments and the ability to generate images with varying quality by varying resolution or the number of looks are additional features. A fiber optics link transfers the Seasat data from high intensity digital tapes to an SEL 32/55 computer, and the least significant bits of the 5 bit data samples are truncated, thus the input data have 4 bits per sample. A total 8192 echoes are processed each time and stored on 8 separate data files on the disk. In addition, a program operating on 1-look high resolution images for performance simulations of proposed radar systems and processing schemes has been completed. Finally, the coding is simple, and 8 hours are required to process one image using this program.
This paper describes a high performance, digital, BPSK modem designed to improve the telemetry data handling capability of NASA's Deep Space Network. The data rate is continuously variable from 0.5 Mbps to 30 Mbps. It uses newly designed, high speed digital alogrithms for receive filtering, carrier tracking, bit timing and AGC. The carrier and bit time tracking loops have been designed to provide fast acquisition and low tracking phase jitter at E sub b/N sub 0 as low as -4 dB and bit transition density as low as 10%. The performance of the modem is within 0.65 dB below 10 Mbps, 1.0 dB from 10 Mbps to 20 Mbps, and 1.5 dB above 20 Mbps of theoretical coherent BPSK at a BER of 0.0004.
Specifications given for computer controlled optical mass memory system that stores and retrieves data from silver halide fiches 148-mmsquare and 7 mils (0.18mm) thick at user bit density of 30 Mbit/in. 2 (4.7 Mbit/cm2) with uncorrectable bit-error rate of 10 to negative 9th power or less. Allows for expansion to 10 the 15th power bit capacity.