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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 487 records · Page 27

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NASA NTRS1978

Formulation of consumables management models. Volume 2: Mission planning processor user guide

A user guide for the MPP (Mission Planning Processor) is presented. The MPP is used in the evaluation of particular missions, with appropriate display and storage of related consumables data. Design goals are accomplished by the use of an on-line/demand mode computer terminal Cathode Ray Tube Display. The process is such that the user merely adds specific mission/flight functions to a skeleton flight and/or alters the skeleton. The skeleton flight includes operational aspects from prelaunch through ground support equipment connect after rollout as required to place the STS (Space Transportation System) in a parking orbit, maintain the spacecraft and crew for the stated on-orbit period and return.

Daly, J. K.↗

NASA NTRS1978

GASP-PL/I Simulation of Integrated Avionic System Processor Architectures

A development study sponsored by NASA was completed in July 1977 which proposed a complete integration of all aircraft instrumentation into a single modular system. Instead of using the current single-function aircraft instruments, computers compiled and displayed inflight information for the pilot. A processor architecture called the Team Architecture was proposed. This is a hardware/software approach to high-reliability computer systems. A follow-up study of the proposed Team Architecture is reported. GASP-PL/1 simulation models are used to evaluate the operating characteristics of the Team Architecture. The problem, model development, simulation programs and results at length are presented. Also included are program input formats, outputs and listings.

Brent, G. A.↗

NASA NTRS1979

Concurrent error detecting codes for arithmetic processors

A method of concurrent error detection for arithmetic processors is described. Low-cost residue codes with check-length l and checkbase m = 2 to the l power - 1 are described for checking arithmetic operations of addition, subtraction, multiplication, division complement, shift, and rotate. Of the three number representations, the signed-magnitude representation is preferred for residue checking. Two methods of residue generation are described: the standard method of using modulo m adders and the method of using a self-testing residue tree. A simple single-bit parity-check code is described for checking the logical operations of XOR, OR, and AND, and also the arithmetic operations of complement, shift, and rotate. For checking complement, shift, and rotate, the single-bit parity-check code is simpler to implement than the residue codes.

Lim, R. S.↗

NASA NTRS1979

OPS MCC level B/C formulation requirements: Area targets and space volumes processor

The level B/C mathematical specifications for the area targets and space volume processor (ATSVP) as well as the characteristics of the system are provided. The mathematical equation necessary to determine whether the spacecraft lies within the area target or space volume is presented. A semianalytical technique for predicting the acquisition of signal (AOS) and loss of signal (LOS) time periods is discussed. A functional overview of the ATSVP which includes an outline of the process required to determine precise AOS and LOS times are given.

Bishop, M. J., Jr.↗

NASA NTRS1979

SPAR thermal analysis processors reference manual, system level 16. Volume 1: Program executive. Volume 2: Theory. Volume 3: Demonstration problems. Volume 4: Experimental thermal element capability. Volume 5: Programmer reference

User instructions are given for performing linear and nonlinear steady state and transient thermal analyses with SPAR thermal analysis processors TGEO, SSTA, and TRTA. It is assumed that the user is familiar with basic SPAR operations and basic heat transfer theory.

Marlowe, M. B.↗

NASA NTRS1980

As-built design specification of the data order processor ORDHDT

A description and subroutine documentation of the data order processor, ORHDT is given. As part of the LANDSAT imagery verification and extraction system, ORDHT creates a computer tape containing the AgRISTARS requirements for LANDSAT data to be ordered from Goddard Space Flight Center. A brief description of hardware requirements is also included.

Rios, A.↗

NASA NTRS1980

Approach to Sounding on the VAS Processor

The key features of the sounding software laboratory being installed on the VAS Processor at NASA/GSFC are outlined. Emphasis is on the support data and personal guidance that a meteorological researcher must provide to attune a physically modeled VAS sounding to his experiment. The fundamental aim of the sounding-support effort is to provide a system which makes use of: radiation transfer models based upon laboratory data, analytic inversion schemes, human guidance for quality control, statistically conditioned retrieval methods, and current ancillary data.

Chesters, D.↗

NASA NTRS1980

The Jet Propulsion Laboratory/California Institute of Technology block 2 VLBI processor

A multistation, multichannel cross correlation processor using the 250 k bit to 4 M bit recording format is discussed. The design is modular, using bit sliced microprocessors to perform the routine calculations for phase and delay on a per station basis, as well as for fractional bit shift correction and Fourier transformation of the correlation coefficients on a per baseline basis.

Rogtad, D. H.↗

NASA NTRS1980

Level B/C software ground navigation program. Delta-T processor

The Delta-T Processor (DTP) computes the instantaneous downtrack error in a specified orbiter onboard navigation state vector recovered via downlink telemetry. The downtrack error, expressed in units of time, is computed based on current incoming Earth based range and Doppler navigation tracking data and the ground selected onboard navigation state vector. The computed time difference when used to modify the timetag of the vector used for onboard navigation reduces the instantaneous downtrack error in this vector to within the threshold of the DTP, the input data, and the onboard software. This threshold is currently estimated to be approximately 2 to 4 nautical miles. The DTP is not restricted to using only onboard vectors. Any vector, either input via the manual entry device or accessible via the vector administration table, may be used. The DTP does not require that both data types be available.

Source record↗

NASA NTRS1979

The Massively Parallel Processor and its applications

A long-term experimental development program conducted at Goddard Space Flight Center to implement an ultrahigh-speed data processing system known as the Massively Parallel Processor (MPP) is described. The MPP is a single instruction multiple data stream computer designed to perform logical, integer, and floating point arithmetic operations on variable word length data. Information is presented on system architecture, the system configuration, the array unit architecture, individual processing units, and expected operating rates for several image processing applications (including the processing of Landsat data).

Strong, J. P.↗

NASA NTRS1980

Design of a massively parallel processor

The massively parallel processor (MPP) system is designed to process satellite imagery at high rates. A large number (16,384) of processing elements (PE's) are configured in a square array. For optimum performance on operands of arbitrary length, processing is performed in a bit-serial manner. On 8-bit integer data, addition can occur at 6553 million operations per second (MOPS) and multiplication at 1861 MOPS. On 32-bit floating-point data, addition can occur at 430 MOPS and multiplication at 216 MOPS.

Batcher, K. E.↗

NASA NTRS1982

Log-Output Signal Processor Scans Eight Decades

Processor has automatic range switching and continuous readout over eight decades. Comparator output switches logarithmic converter to detector of interest and enables blinder grid to protect more-sensitive detector when operating in high-input range. Could be used to process any wide-varying signal that is to be read on a limited-range recording device such as a strip-chart recorder.

Hayden, J. L.↗

NASA NTRS1982

One Way of Testing a Distributed Processor

Launch processing for Space Shuttle is checked out, controlled, and monitored with new system. Entire system can be exercised by two computer programs--one in master console and other in each of operations consoles. Control program in each operations console detects change in status and begins task initiation. All of front-end processors are exercised from consoles through common data buffer, and all data are logged to processed-data recorder for posttest analysis.

Edstrom, R.↗

NASA NTRS1980

Tape merge/copy processor

The TAPMRG processor merges or copies data files from one or more tapes onto a single output tape.

Obrien, S. O.↗

NASA NTRS1980

EROS to universal tape conversion processor

The function of the EROS processor is to allow a user to select a specific area from a full frame LANDSAT image which is written on tape in the EROS format. The area of interest is read from the EROS formatted tape and converted to the JSC Universal format and written onto another tape. This tape can then be read by the IMDACS processing system and normal analysis can be performed.

Obrien, S. O.↗

NASA NTRS1980

PATCH image processor user's manual

The patch image processor extracts patches in various size (32 x 32, 64 x 64, 128 x 128, and 256 x 256 pixels) from full frame LANDSAT imagery data. With the patches that are extracted, a patch image mosaic is created in the image processing system, IMDACS, format.

Nieves, M. J.↗

NASA NTRS1981

An introduction to the interim digital SAR processor and the characteristics of the associated Seasat SAR imagery

Basic engineering data regarding the Interim Digital SAR Processor (IDP) and the digitally correlated Seasat synthetic aperature radar (SAR) imagery are presented. The correlation function and IDP hardware/software configuration are described, and a preliminary performance assessment presented. The geometric and radiometric characteristics, with special emphasis on those peculiar to the IDP produced imagery, are described.

Wu, C.↗

NASA NTRS1981

CCD correlated quadruple sampling processor

A correlated quadruple sampling processor for improved signal-to-noise ratio in the output of a charge-coupled device (CCD) is comprised of: switching means for momentarily clamping a CCD signal line at a first reference level A before a CCD data pulse and then obtaining a first data sample B with respect to the reference A during a CCD data pulse, and storing the positive sample B-A; switching means for momentarily clamping the CCD signal line a second time at the level C during the presence of the CCD data pulse and then obtaining a second data sample D with respect to the reference level C after the CCD data pulse, and storing the negative sample D-C; and means for obtaining the difference between the stored samples +(B-A) and -(D-C), thus increasing the net signal amplitude by a factor of about 2 while the noise would be increased by only a factor of square root of 2 since there will be no correlation in the noise between the double samples +(B-A) and -(D-C) effectively added.

Gaalema, S. D.↗