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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 505 records · Page 28
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Design and performance of an in-vacuum, magnetic field mapping system for the Muon g-2 experiment

The E989 Muon g-2 experiment at Fermilab aims to measure the anomalous magnetic moment, a$_\mu$, of the muon with a precision of 140 parts-per-billion. This requires a precise measurement of both the anomalous spin precession frequency, $\omega_a$, and the average magnetic field in terms of the equivalent, free proton Larmor frequency, $\omega_p$. The measurement of $\omega_p$ with a total systematic uncertainty of 70 parts-per-billion involves a combination of various NMR probes. There are 378 probes in fixed locations constantly monitoring field drifts. A water-based probe provides the calibration in terms of $\omega_p$. A crucial element for the multi-step measurement of $\omega_p$ is the regular mapping of the magnetic field over the muon storage region. The former E821 experiment at Brookhaven employed an in-vacuum field mapping system equipped with 17 NMR probes, which was developed by the University of Heidelberg. We have refurbished and upgraded this system with new probes and electronics. The upgrades include a new communication scheme incorporating time-division multiplexing to separate the important NMR reference clock from the data communication. The addition digitization of the NMR signals replaced the hardware-implemented zero-crossing counting of the E821 system. The digitized signals offer new capabilities in the NMR frequency analysis and its related systematic uncertainties. While the mechanical systems that move the field mapper around the ring have been mostly refurbished, the motion control system was completely replaced with a custom-built electronics centered around a commercial Galil motion controller. Both the field mapping NMR system and its motion control were successfully commissioned at Fermilab and have been in reliable operation during the first data taking periods. This article provides details of the upgrades of the field mapper and its performance.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

A New Scheme of Redundant Timing Crosschecking for Frontend Systems

In high energy physics experiments, frontend digitization modules are usually driven by a common clock. At the frontend electronics and digitization modules of the detector, a precise timing reference must establish in order to make a useful timing measurement. It would be very useful for the frontend digitization system to include a feature of redundant timing crosschecking. The inspiration for the timing crosschecking scheme came from the long-abandoned analog mean-timer schemes. In this scheme, several Front-end modules are connected together through a cable set with taps connected to the digitization modules. Pulses are driven from every FE modules alternately without overlapping. The arrival times of pulses sent from FE modules are digitized at the timing crosschecking module. The mean times will change as temperature changes, but their difference between two FE modules are cancelled mathematically. This feature enables easy achievement of good timing precision without the need for complex hardware.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Method for active sensor signal optimization

A system and method for optimizing a fiber optic sensor by properly clocking or rotationally orienting a window with a fiber optic focuser. This method may include shining light through the focuser into the window and receiving with a reflectometer a first reflection from a first surface of the window and a second reflection from a second surface of the window. Next, the method may include calculating a delta of intensities between the first and second reflections, and then rotating an orientation of the window to a next rotational orientation. The steps of rotating the orientation of the window, receiving reflections, and calculating their delta may be repeated any plurality of times to solve for a plurality of deltas. Then, the method may include the steps of determining which one of the deltas is the largest and fixing the window to the focuser at a rotational orientation associated therewith.

42 ENGINEERING↗
DOE OSTI2020

Application of Dynamical System Scaling to Bubble Dynamics

Dynamical System Scaling (DSS) provides a useful method for analyzing, categorizing and scaling time-dependent processes. A key feature of DSS is the temporal displacement rate, D, which relates the natural process time to the reference clock time. Because of its property of being invariant under a two-parameter affine transformation, it provides an underlying basis for process scaling. Application of DSS to bubble dynamics serves to elucidate the physical significance of the temporal displacement rate and its role in scaling a variety of bubble dynamics processes. This paper shows that the temporal displacement rate consists of the sum of dimensionless groups that govern the bubble dynamics. Preserving the temporal displacement rate for a prototype and a scaled model results in similitude of the time-dependent normalized bubble size, growth rates and interfacial accelerations for different fluid conditions. For vapor bubble growth in a superheated liquid, it is shown that inertial controlled bubble growth occurs when D=0 and thermally controlled bubble growth occurs when D=1 .

dynamical system scaling, SMR, bubble dynamics, DS↗
DOE OSTI2020

Pulsed start-up system for electrostatic generators

A new rotor start-up system is provided for application to rotating systems such as stationary or vehicular electromechanical battery systems. An embodiment of the system consists of a “locator” that includes a stationary permanent-magnet pole above which is a circular ferromagnetic (e.g., iron) strip embedded in the lower, inner edge of the flywheel rotor. The lower edge of this strip is wave-like so that the magnet can pull the rotor around to a position where the position relative to the minimum capacity between the rotor and stator electrodes is such as to launch the rotor in a chosen direction, i.e., either clock-wise or counter-clockwise. Startup from rest is then accomplished by applying a short high-voltage ac or dc pulse to the EMB capacitor.

42 ENGINEERING↗
DOE OSTI2020

Modular scalable power conversion

A cascaded architecture composed of interconnected blocks that are each designed to process constant power and eliminate bulk energy storage are provided. Further, local controls within each block natively achieve both block- and system-level aims, making the system modular and scalable. Further methods of providing power conversion using such interconnected clocks are also provided.

Maksimovic, Dragan↗
DOE OSTI2021

A Novel Decentralized PWM Interleaving Technique for Ripple Minimization in Series-Stacked DC-DC Converters: Preprint

Cascaded dc-dc converters are commonly used in applications where distributed energy sources or loads are connected to elevated voltage levels for power transfer. In such systems, it is advantageous to minimize the ripple on the bus current and voltage by proper phase shifting of the pulse-width modulation (PWM) pulses among the converters via a method known as interleaving. Existing approaches use either a centralized controller or separate communication lines among the stacked converters to control their relative PWM switch transitions. The key drawbacks are that these methods entail significant wiring, the central controller acts as a single point of failure, and implementation on very large numbers of units is impractical. In this paper, we introduce a decentralized interleaving control (DIC) strategy that acts on local current measurements at every converter and achieves communication-free PWM interleaving among the series-stacked converters. The proposed controller is simple in structure and is shown to converge asymptotically to the interleaved state irrespective of clock drifts among the digital signal processors. Experimental results are provided for a system of five series-connected converters showing a 10 times reduction in the current ripple compared to normal operation.

41 EE - Solar Energy Technologies Office (EE-4S)↗
DOE OSTI2021

Transmitter with fully re-assignable segments for reconfigurable FFE taps

Methods and systems of performing feed forward equalization (FFE) on data streams are described. A circuitry may generate staggered data streams from data streams of an input signal. The staggered data streams may include data in staggered unit intervals. The circuitry may include a plurality of segments. A segment may define a specific unit interval to carve the staggered data streams into one unit interval pulses positioned at the specific unit interval. The specific unit interval to carve the staggered data streams may indicate an assignment of the segment as one of a FFE pre tap, a FFE main tap, and a FFE post tap. The plurality of segments may be assigned to different FFE taps based on different clock signal selection defining different unit intervals to perform the carving. The plurality of segments may output respective one unit interval pulses to reproduce the input signal.

Toprak-Deniz, Zeynep↗
DOE OSTI2021

Leaky Buddies: Cross-Component Covert Channels on Integrated CPU-GPU Systems

Graphics Processing Units (GPUs) are ubiquitous components used across the range of today’s computing plat- forms, from phones and tablets, through personal computers, to high-end server class platforms. With the increasing importance of graphics and video workloads, recent processors are shipped with GPU devices that are integrated on the same chip. Integrated GPUs share some resources with the CPU and as a result, there is a potential for microarchitectural attacks from the GPU to the CPU or vice versa. We consider the potential for covert channel attacks that arise either from shared microarchitectural components (such as caches) or through shared contention domains (e.g., shared buses). We illustrate these two types of channels by developing two reliable covert channel attacks. The first covert channel uses the shared LLC cache in Intel’s integrated GPU architectures. The second is a contention based channel targeting the ring bus connecting the CPU and GPU to the LLC. This is the first demonstrated microarchitectural attack crossing the component boundary (GPU to CPU or vice versa). Cross-component channels introduce a number of new challenges that we had to overcome since they occur across heterogeneous components that use different computation models and are interconnected using asymmetric memory hierarchies. We also exploit GPU parallelism to increase the bandwidth of the communication, even without relying on a common clock. The LLC based channel achieves a bandwidth of 120 kbps with a low error rate of 2%, while the contention based channel delivers up to 400 kbps with a 0.8% error rate. We also demonstrate a proof- of-concept prime-and-probe side channel attack that probes the full LLC from the GPU.

Cyber secruity, high performance comptuing, Hetero↗
DOE OSTI2021

A 3D FPGA Track Segment Seeding Engine Based on the Tiny Triplet Finder

A 3D track segment seeding engine core based on the Tiny Triplet Finder has been implemented and tested in a low-cost FPGA device. The seeding engine is designed to preselect and group hits (stubs) from cylindrical detector layers to feed subsequent track fitting stage. The seeding engine consists of a Hough transform space for r-z view and a Tiny Triplet Finder for r-phi view to implement 3D constraints. The seeding engine is organized as a pipeline so that each hit is processed in a single clock cycle. Test results show that the seeding engine operates as expected.

Wu, Jinyuan↗
DOE OSTI2020

A 20 Gbps Data Transmitting ASIC with PAM4 for Particle Physics Experiments

We present the design principle and test results of a data transmitting ASIC, GBS20, for particle physics experiments. The goal of GBS20 will be an ASIC that employs two serializers each from the 10.24 Gbps lpGBT SerDes, sharing the PLL also from lpGBT. A PAM4 encoder plus a VCSEL driver will be implemented in the same die to use the same clock system, eliminating the need of CDRs in the PAM4 encoder. This way the transmitter module, GBT20, developed using the GBS20 ASIC, will have the exact lpGBT data interface and transmission protocol, with an output up to 20.48 Gbps over one fiber. With PAM4 embedded FPGAs at the receiving end, GBT20 will halve the fibers needed in a system and better use the input bandwidth of the FPGA. A prototype, GBS20v0 is fabricated using a commercial 65 nm CMOS technology. This prototype has two serializers and a PAM4 encoder sharing the lpGBT PLL, but no user data input. An internal PRBS generator provides data to the serializers. GBS20v0 is tested barely up to 20.48 Gbps. With lessons learned from this prototype, we are designing the second prototype, GBS20v1, that will have 16 user data input channels each at 1.28 Gbps. We present the design concept of the GBS20 ASIC and the GBT20 module, the preliminary test results, and lessons learned from GBS20v0 and the design of GBS20v1 which will be not only a test chip but also a user chip with 16 input data channels.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Low modulation index 3-phase solid state transformer

A solid-state transformer (SST) comprises a transformer core, a primary winding, a secondary winding, a primary-side switch bank, and a secondary-side switch bank. Each of the switch banks includes six 4-quadrant switches. The twelve 4-quadrant switches are toggled on and off over six clock cycles in a repetitive sequence with a period that is a function of a desired operating frequency of the transformer. The sequence is configured such that at any given time, 2 of 3 input and output phases are connected to the primary and secondary windings. The SST further includes L-C filter circuits that are configured to filter high-frequency components of current and voltage waveforms such that these components are not back-fed to the electrical mains or delivered to a load. The SST includes a primary-side filter circuit and a secondary-side filter circuit that can each include respective L-C filters for three input or output phases.

Koplow, Jeffrey P.↗
DOE OSTI2022

Self-regulating power management for a neural network system

A neural network runs a known input data set using an error free power setting and using an error prone power setting. The differences in the outputs of the neural network using the two different power settings determine a high level error rate associated with the output of the neural network using the error prone power setting. If the high level error rate is excessive, the error prone power setting is adjusted to reduce errors by changing voltage and/or clock frequency utilized by the neural network system. If the high level error rate is within bounds, the error prone power setting can remain allowing the neural network to operate with an acceptable error tolerance and improved efficiency. The error tolerance can be specified by the neural network application.

Kegel, Andrew G.↗
DOE OSTI2022

Carrier and sampling frequency offset estimation for RF communication with crystal-less nodes

When the ultra-low power mm-scale sensor node does not have a crystal oscillator and phase-lock loop, it inevitably exhibits significant carrier frequency offset (CFO) and sampling frequency offset (SFO) with respect to the reference frequencies in the gateway. This disclosure enables efficient real-time calculation of accurate SFO and CFO at the gateway, thus the ultra-low power mm-scale sensor node can be realized without a costly and bulky clock reference crystal and also power-hungry phase lock loop. In the proposed system, the crystal-less sensor starts transmission with repetitive RF pulses with a constant interval, followed by the data payload using pulse-position modulation (PPM). A proposed algorithm uses a two-dimensional (2D) fast Fourier transform (FFT) based process that identifies the SFO and CFO at the same time to establish successful wireless communication between the gateway and crystal-less sensor nodes.

Kim, Hun-Seok↗
DOE OSTI2023

Oscillator for adiabatic computational circuitry

An adiabatic resonator, an adiabatic oscillator, and an adiabatic oscillator system are disclosed. An adiabatic system is one that ideally transfers no heat outside of the system, thereby reducing the required operating power. The adiabatic resonator, which includes a plurality of tank circuits, acts as an energy reservoir, the missing aspect of previously attempted adiabatic computational systems. By using the adiabatic resonator as a feedback element with an amplifier, an adiabatic oscillator is formed. An adiabatic oscillator system is formed with a primary adiabatic oscillator feeding a plurality of secondary adiabatic oscillators. In this manner, the adiabatic oscillator system may be used to generate the multiple clock signals required of adiabatic computational logic elements, such as Split-level Charge Recovery Logic and 2-Level Adiabatic Logic. The adiabatic oscillator system stores enough energy to drive many individual adiabatic computational logic elements, permitting implementation of complex logic circuits.

Brocato, Robert W.↗
DOE OSTI2023

Sub-nanosecond RF synchronization for MIMO software defined radio sensor networks

This disclosure presents distributed and decentralized synchronization for wireless transceivers. The disclosed system, device, and method achieve sub-nanosecond synchronization using low-cost commercial off the shelf software defined radios. By providing a decentralized mechanism that does not rely on a hierarchical master-slave structure, networks constructed as disclosed are robust to sensor drop-out in contested or harsh environments. Such networks may be used to create phased array radars and communication systems without requiring wired connections to distribute a common clock or local oscillator reference.

Moghaddam, Mahta↗
DOE OSTI2023

Digital Q-Meter for continuous-wave NMR

A method to perform continuous-wave NMR measurements of nuclear magnetization at high magnetic fields, above 2.5 T, without analog down-mixing is described. An FPGA controls a digital clock pulse which is used to stimulate a resonant circuit and provide a reference signal. An algorithm determines the real portion of a resonant circuit signal near the Larmor frequency of the species of interest using only two measurements of the waveform per cycle. The FPGA automatically alters a variable capacitance to tune the resonant circuit to the Larmor frequency.

Maxwell, James↗
DOE OSTI2023

Self-regulating power management for a neural network system

A neural network runs a known input data set using an error free power setting and using an error prone power setting. The differences in the outputs of the neural network using the two different power settings determine a high level error rate associated with the output of the neural network using the error prone power setting. If the high level error rate is excessive, the error prone power setting is adjusted to reduce errors by changing voltage and/or clock frequency utilized by the neural network system. If the high level error rate is within bounds, the error prone power setting can remain allowing the neural network to operate with an acceptable error tolerance and improved efficiency. The error tolerance can be specified by the neural network application.

Kegel, Andrew G.↗