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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 505 records · Page 28
All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

Nanoelectronics: Opportunities for future space applications

Further improvements in the performance of integrated electronics will eventually halt due to practical fundamental limits on our ability to downsize transistors and interconnect wiring. Avoiding these limits requires a revolutionary approach to switching device technology and computing architecture. Nanoelectronics, the technology of exploiting physics on the nanometer scale for computation and communication, attempts to avoid conventional limits by developing new approaches to switching, circuitry, and system integration. This presentation overviews the basic principles that operate on the nanometer scale that can be assembled into practical devices and circuits. Quantum resonant tunneling (RT) is used as the center-piece of the overview since RT devices already operate at high temperature (120 degrees C) and can be scaled, in principle, to a few nanometers in semiconductors. Near- and long-term applications of GaAs and silicon quantum devices are suggested for signal and information processing, memory, optoelectronics, and radio frequency (RF) communication.

Frazier, Gary↗
NASA NTRS2006

Ferroelectric Material Application: Modeling Ferroelectric Field Effect Transistor Characteristics from Micro to Nano

All present ferroelectric transistors have been made on the micrometer scale. Existing models of these devices do not take into account effects of nanoscale ferroelectric transistors. Understanding the characteristics of these nanoscale devices is important in developing a strategy for building and using future devices. This paper takes an existing microscale ferroelectric field effect transistor (FFET) model and adds effects that become important at a nanoscale level, including electron velocity saturation and direct tunneling. The new model analyzed FFETs ranging in length from 40,000 nanometers to 4 nanometers and ferroelectric thickness form 200 nanometers to 1 nanometer. The results show that FFETs can operate on the nanoscale but have some undesirable characteristics at very small dimensions.

MacLeod, Todd, C.↗
NASA NTRS2009

Prognostics for Electronics Components of Avionics Systems

Electronics components have and increasingly critical role in avionics systems and for the development of future aircraft systems. Prognostics of such components is becoming a very important research filed as a result of the need to provide aircraft systems with system level health management. This paper reports on a prognostics application for electronics components of avionics systems, in particular, its application to the Isolated Gate Bipolar Transistor (IGBT). The remaining useful life prediction for the IGBT is based on the particle filter framework, leveraging data from an accelerated aging tests on IGBTs. The accelerated aging test provided thermal-electrical overstress by applying thermal cycling to the device. In-situ state monitoring, including measurements of the steady-state voltages and currents, electrical transients, and thermal transients are recorded and used as potential precursors of failure.

Celaya, Jose R.↗
DOE OSTI2023

Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform

Two-dimensional (2D) materials are promising candidates for future electronics due to their excellent electrical and photonic properties. Although promising results on the wafer-scale synthesis (≤150 mm diameter) of monolayer molybdenum disulfide (MoS 2 ) have already been reported, the high-quality synthesis of 2D materials on wafers of 200 mm or larger, which are typically used in commercial silicon foundries, remains difficult. The back-end-of-line (BEOL) integration of directly grown 2D materials on silicon complementary metal–oxide–semiconductor (CMOS) circuits is also unavailable due to the high thermal budget required, which far exceeds the limits of silicon BEOL integration (<400 °C). This high temperature forces the use of challenging transfer processes, which tend to introduce defects and contamination to both the 2D materials and the BEOL circuits. Here we report a low-thermal-budget synthesis method (growth temperature < 300 °C, growth time ≤ 60 min) for monolayer MoS 2 films, which enables the 2D material to be synthesized at a temperature below the precursor decomposition temperature and grown directly on silicon CMOS circuits without requiring any transfer process. We designed a metal–organic chemical vapour deposition reactor to separate the low-temperature growth region from the high-temperature chalcogenide-precursor-decomposition region. We obtain monolayer MoS 2 with electrical uniformity on 200 mm wafers, as well as a high material quality with an electron mobility of ~35.9 cm 2 V -1 s -1 . Finally, we demonstrate a silicon-CMOS-compatible BEOL fabrication process flow for MoS 2 transistors; the performance of these silicon devices shows negligible degradation (current variation < 0.5%, threshold voltage shift < 20 mV). We believe that this is an important step towards monolithic 3D integration for future electronics.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
NASA NTRS2019

Performance Evaluation of High-Speed, Low-Side Gate Driver, FAN3122, over Extended Temperature Range

Emerging power metal-oxide semiconductor field-effect transistor (MOSFETs) based on silicon carbide and gallium nitride technology are finding widespread use in many electronic applications such as motor control and DC/DC converters due to their higher voltage, higher temperature tolerance, and higher frequency switching capabilities. To utilize these power devices and to meet circuit/system compactness, modularity, and operational functionality, gate drivers that provide unique attributes, such as fast switching and high-current handling capability, are needed. In addition, power systems geared for use in space mission applications require on-board devices to withstand exposure to extreme temperatures and wide thermal swings. Very little data, however, exist on the performance of such devices and circuits under extreme temperatures. In this work, the performance of a high-speed gate driver with potential use in controlling power-level transistors was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance for potential use of this device in space exploration missions under extreme temperature conditions.

Wide Bandgap Semiconductors↗
DOE OSTI2022

Ultra‐Narrow Phosphorene Nanoribbons Produced by Facile Electrochemical Process

Abstract Phosphorene nanoribbons (PNRs) have inspired strong research interests to explore their exciting properties that are associated with the unique two‐dimensional (2D) structure of phosphorene as well as the additional quantum confinement of the nanoribbon morphology, providing new materials strategy for electronic and optoelectronic applications. Despite several important properties of PNRs, the production of these structures with narrow widths is still a great challenge. Here, a facile and straightforward approach to synthesize PNRs via an electrochemical process that utilize the anisotropic Na + diffusion barrier in black phosphorus (BP) along the [001] zigzag direction against the [100] armchair direction, is reported. The produced PNRs display widths of good uniformity (10.3 ± 3.8 nm) observed by high‐resolution transmission electron microscopy, and the suppressed B 2g vibrational mode from Raman spectroscopy results. More interestingly, when used in field‐effect transistors, synthesized bundles exhibit the n‐type behavior, which is dramatically different from bulk BP flakes which are p‐type. This work provides insights into a new synthesis approach of PNRs with confined widths, paving the way toward the development of phosphorene and other highly anisotropic nanoribbon materials for high‐quality electronic applications.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS2004

EHW Approach to Temperature Compensation of Electronics

Efforts are under way to apply the concept of evolvable hardware (EHW) to compensate for variations, with temperature, in the operational characteristics of electronic circuits. To maintain the required functionality of a given circuit at a temperature above or below the nominal operating temperature for which the circuit was originally designed, a new circuit would be evolved; moreover, to obtain the required functionality over a very wide temperature range, there would be evolved a number of circuits, each of which would satisfy the performance requirements over a small part of the total temperature range. The basic concepts and some specific implementations of EHW were described in a number of previous NASA Tech Briefs articles, namely, "Reconfigurable Arrays of Transistors for Evolvable Hardware" (NPO-20078), Vol. 25, No. 2 (February 2001), page 36; Evolutionary Automated Synthesis of Electronic Circuits (NPO- 20535), Vol. 26, No. 7 (July 2002), page 37; "Designing Reconfigurable Antennas Through Hardware Evolution" (NPO-20666), Vol. 26, No. 7 (July 2002), page 38; "Morphing in Evolutionary Synthesis of Electronic Circuits" (NPO-20837), Vol. 26, No. 8 (August 2002), page 31; "Mixtrinsic Evolutionary Synthesis of Electronic Circuits" (NPO-20773) Vol. 26, No. 8 (August 2002), page 32; and "Synthesis of Fuzzy-Logic Circuits in Evolvable Hardware" (NPO-21095) Vol. 26, No. 11 (November 2002), page 38. To recapitulate from the cited prior articles: EHW is characterized as evolutionary in a quasi-genetic sense. The essence of EHW is to construct and test a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The connection and disconnection can be effected by use of field-programmable transistor arrays (FPTAs). The evolution is guided by a search-andoptimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality. The evolved circuits can be tested by mathematical modeling (that is, computational simulation) only, tested in real hardware, or tested in combinations of computational simulation and real hardware.

Stoica, Adrian↗
NASA NTRS1983

Recovery of damage in rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays

This paper reports on the recovery properties of rad-hard MOS devices during and after irradiation by electrons, protons, alphas, and gamma rays. The results indicated that complex recovery properties controlled the damage sensitivities of the tested parts. The results also indicated that damage sensitivities depended on dose rate, total dose, supply bias, gate bias, transistor type, radiation source, and particle energy. The complex nature of these dependencies make interpretation of LSI device performance in space (exposure to entire electron and proton spectra) difficult, if not impossible, without respective ground tests and analyses. Complete recovery of n-channel shifts was observed, in some cases within hours after irradiation, with equilibrium values of threshold voltages greater than their pre-irradiation values. This effect depended on total dose, radiation source, and gate bias during exposure. In contrast, the p-channel shifts recovered only 20 percent within 30 days after irradiation.

Brucker, G. J.↗
DOE OSTI2022

Atomic-scale defects generated in the early/intermediate stages of dielectric breakdown in Si/SiO 2 transistors

In this study, electrically detected magnetic resonance and near-zero-field magnetoresistance measurements were used to study atomic-scale traps generated during high-field gate stressing in Si/SiO 2 MOSFETs. The defects observed are almost certainly important to time-dependent dielectric breakdown. The measurements were made with spin-dependent recombination current involving defects at and near the Si/SiO 2 boundary. The interface traps observed are P b0 and P b1 centers, which are silicon dangling bond defects. The ratio of P b0 /P b1 is dependent on the gate stressing polarity. Electrically detected magnetic resonance measurements also reveal generation of E' oxide defects near the Si/SiO 2 interface. Near-zero-field magnetoresistance measurements made throughout stressing reveal that the local hyperfine environment of the interface traps changes with stressing time; these changes are almost certainly due to the redistribution of hydrogen near the interface.

42 ENGINEERING↗
NASA NTRS2003

Applications of Gas Imaging Micro-Well Detectors to an Advanced Compton Telescope

We present a concept for an Advanced Compton Telescope (ACT) based on the use of pixelized gas micro-well detectors to form a three-dimensional electron track imager. A micro-well detector consists of an array of individual micro-patterned proportional counters opposite a planar drift electrode. When combined with thin film transistor array readouts, large gas volumes may be imaged with very good spatial and energy resolution at reasonable cost. The third dimension is determined by timing the drift of the ionization electrons. The primary advantage of this approach is the excellent tracking of the Compton recoil electron that is possible in a gas volume. Such good electron tracking allows us to reduce the point spread function of a single incident photon dramatically, greatly improving the imaging capability and sensitivity. The polarization sensitivity, which relies on events with large Compton scattering angles, is particularly enhanced. We describe a possible ACT implementation of this technique, in which the gas tracking volume is surrounded by a CsI calorimeter, and present our plans to build and test a small prototype over the next three years.

Bloser, P. F.↗
NASA NTRS2013

Fully Printed, Flexible, Phased Array Antenna for Lunar Surface Communication

NASAs future exploration missions focus on the manned exploration of the Moon, Mars, and beyond, which will rely heavily on the development of a reliable communications infrastructure from planetary surface-to-surface, surface-to-orbit, and back to Earth. Flexible antennas are highly desired in many scenarios. Active phased array antennas (active PAAs) with distributed control and processing electronics at the surface of an antenna aperture offer numerous advantages for radar communications. Large-area active PAAs on flexible substrates are of particular interest in NASA s space radars due to their efficient inflatable package that can be rolled up during transportation and deployed in space. Such an inflatable package significantly reduces stowage volume and mass. Because of these performance and packaging advantages, large-area inflatable active PAAs are highly desired in NASA s surface-to-orbit and surface-to-relay communications. To address the issues of flexible electronics, a room-temperature printing process of active phased-array antennas on a flexible Kapton substrate was developed. Field effect transistors (FETs) based on carbon nanotubes (CNTs), with many unique physical properties, were successfully proved feasible for the PAA system. This innovation is a new type of fully inkjet-printable, two-dimensional, high-frequency PAA on a flexible substrate at room temperature. The designed electronic circuit components, such as the FET switches in the phase shifter, metal interconnection lines, microstrip transmission lines, etc., are all printed using a special inkjet printer. Using the developed technology, entire 1x4, 2x2, and 4x4 PAA systems were developed, packaged, and demonstrated at 5.3 GHz. Several key solutions are addressed in this work to solve the fabrication issues. The source/drain contact is developed using droplets of silver ink printed on the source/drain areas prior to applying CNT thin-film. The wet silver ink droplets allow the silver to wet the CNT thin-film area and enable good contact with the source and drain contact after annealing. A passivation layer to protect the device channel is developed by bonding a thin Kapton film on top of the device channel. This film is also used as the media for transferring the aligned CNT thin-film on the device substrate. A simple and cost-effective technique to form multilayer metal interconnections on flexible substrate is developed and demonstrated. Contact vias are formed on the second substrate prior to bonding on the first substrate. Inkjet printing is used to fill the silver ink into the via structure. The printed silver ink penetrates through the vias to contact with the contact pads on the bottom layer. It is then annealed to form a good connection. One-dimensional and two-dimensional PAAs were fabricated and characterized. In these circuits, multilayer metal interconnects were used to make a complete PAA system.

Subbaraman, Harish↗
DOE OSTI2025

Radiation Response of Ga 2 O 3 MOSFETs Probed via Focused Particle Beams

Gallium Oxide (Ga 2 O 3 ), particularly in its β-phase, is attracting lots of interest for high-power and high-voltage electronics due to its wide bandgap, high breakdown field, and thermal stability. This study investigates the radiation response of Ga 2 O 3 Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) under Total Ionizing Dose (TID) and Displacement Damage (DD) conditions, which are critical for applications in radiation environments. Utilizing a dual-beam Focused Ion Beam and Scanning Electron Microscope setup, microscale analysis of radiation effects on individual devices is performed. The findings reveal distinct behaviors under TID and DD + TID conditions, with TID leading to threshold voltage shifts due to trapped charges, while DD results in decreased drive current attributed to increased carrier scattering from lattice defects. Notably, it is demonstrated that the TID effect can be mitigated through dynamic threshold voltage adjustments and that the predicted TID from ions calculated by Monte Carlo simulations overestimates actual TID due to unaccounted charge yield effects. In conclusion, this research enhances the understanding of Ga2O3 MOSFETs' performance in harsh radiation environments, providing insights for the design of robust electronic devices for space and nuclear applications.

MOSFET↗
DOE OSTI2026

Enhancing mobility and interface state engineering via UV-ozone treatment in BEOL-compatible ultrathin TiO 2 transistors

It has emerged as a potential candidate to improve the performance of monolithic-three-dimensional (M3D) integration of fused logic and memories through low-temperature in situ synthesis of high-performance metal–oxide–semiconductor (MOS) transistors. Here, we report the demonstration of the BEOL-compatible low thermal budget (350 °C) fabrication process of ultrathin-TiO2 transistors by the combination of RTA and UV-ozone treatment (RTA-UVOz). UV–ozone (UVOz) treatment of TiO2 anatase films significantly enhances stability, boosting ION current and field effect mobility (μ FE ) by two times of magnitude in TiO2 TFTs. UV ozone treatment helps to eliminate pre-existing oxygen vacancies and carbon contamination on TiO2 channels even at low temperature (100 °C), resulting in high-quality channel/dielectric interfaces with low interface states (D it ). During UVOz treatment, oxygen species (O x ) passivate the oxygen vacancies ($V$$^{2+}_{o}$), and hence low concentration of $V$$^{2+}_{o}$ would be left for ionization/de-ionization under PBS/NBS, leading to improved bias stress stability. Furthermore, the TiO 2 TFTs with thin ZrO 2 gate dielectric exhibited excellent performance including a lower subthreshold swing (SS) of 98 mV/dec with high drive I ON current ∼ 4.5 μA/μm, a high I ON /I OFF > 10 9 , and mobility μFE of 7 cm 2 /V-s under a battery powered voltage of 1 V. UV–ozone treatment enables high-performance, CMOS-compatible TiO 2 transistors with a low thermal budget, ideal for next-generation flexible, energy-efficient electronics.

BEOL↗
DOE OSTI2022

Manipulating high-temperature superconductivity by oxygen doping in Bi2Sr2CaCu2O8+δ thin flakes

Abstract Harnessing the fascinating properties of correlated oxides requires precise control of their carrier density. Compared to other methods, oxygen doping provides an effective and more direct way to tune the electronic properties of correlated oxides. Although several approaches, such as thermal annealing and oxygen migration, have been introduced to change the oxygen content, a continuous and reversible solution that can be integrated with modern electronic technology is much in demand. Here, we report a novel ionic field-effect transistor using solid Gd-doped CeO2 as the gate dielectric, which shows a remarkable carrier-density-tuning ability via electric-field-controlled oxygen concentration at room temperature. In Bi2Sr2CaCu2O8+δ (Bi-2212) thin flakes, we achieve a reversible superconductor–insulator transition by driving oxygen ions in and out of the samples with electric fields, and map out the phase diagram all the way from the insulating regime to the over-doped superconducting regime by continuously changing the oxygen doping level. Scaling analysis indicates that the reversible superconductor–insulator transition for the Bi-2212 thin flakes follows the theoretical description of a two-dimensional quantum phase transition. Our work provides a route for realizing electric-field control of phase transition in correlated oxides. Moreover, the configuration of this type of transistor makes heterostructure/interface engineering possible, thus having the potential to serve as the next-generation all-solid-state field-effect transistor.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2013

Towards Prognostics for Electronics Components

Electronics components have an increasingly critical role in avionics systems and in the development of future aircraft systems. Prognostics of such components is becoming a very important research field as a result of the need to provide aircraft systems with system level health management information. This paper focuses on a prognostics application for electronics components within avionics systems, and in particular its application to an Isolated Gate Bipolar Transistor (IGBT). This application utilizes the remaining useful life prediction, accomplished by employing the particle filter framework, leveraging data from accelerated aging tests on IGBTs. These tests induced thermal-electrical overstresses by applying thermal cycling to the IGBT devices. In-situ state monitoring, including measurements of steady-state voltages and currents, electrical transients, and thermal transients are recorded and used as potential precursors of failure.

Saha, Bhaskar↗
NASA NTRS2011

Prognostics of Power Mosfets Under Thermal Stress Accelerated Aging Using Data-Driven and Model-Based Methodologies

An approach for predicting remaining useful life of power MOSFETs (metal oxide field effect transistor) devices has been developed. Power MOSFETs are semiconductor switching devices that are instrumental in electronics equipment such as those used in operation and control of modern aircraft and spacecraft. The MOSFETs examined here were aged under thermal overstress in a controlled experiment and continuous performance degradation data were collected from the accelerated aging experiment. Dieattach degradation was determined to be the primary failure mode. The collected run-to-failure data were analyzed and it was revealed that ON-state resistance increased as die-attach degraded under high thermal stresses. Results from finite element simulation analysis support the observations from the experimental data. Data-driven and model based prognostics algorithms were investigated where ON-state resistance was used as the primary precursor of failure feature. A Gaussian process regression algorithm was explored as an example for a data-driven technique and an extended Kalman filter and a particle filter were used as examples for model-based techniques. Both methods were able to provide valid results. Prognostic performance metrics were employed to evaluate and compare the algorithms.

Electrolytic capacitors↗
NASA NTRS2012

A Comparison of High-Energy Electron and Cobalt-60 Gamma-Ray Radiation Testing

In this paper, a comparison between the effects of irradiating microelectronics with high energy electrons and Cobalt-60 gamma-rays is examined. Additionally, the effect of electron energy is also discussed. A variety of part types are investigated, including discrete bipolar transistors, hybrids, and junction field effect transistors

Boutte, Alvin J.↗
NASA NTRS2008

IR DirectFET Extreme Environments Evaluation Final Report

In 2007, International Rectifier (IR) introduced a new version of its DirectFET metal oxide semiconductor field effect transistor (MOSFET) packaging. The new version (referred to as 'Version 2') enhances device moisture resistance, makes surface mount (SMT) assembly of these devices to printed wiring boards (PWBs) more repeatable, and subsequent assembly inspection simpler. In the present study, the National Aeronautics Space Administration (NASA) Jet Propulsion Laboratory (JPL), in collaboration with Stellar Microelectronics (Stellar), continued an evaluation of the DirectFET that they started together in 2006. The present study focused on comparing the two versions of the DirectFET and examining the suitability of the DirectFET devices for space applications. This study evaluated both versions of two DirectFET packaged devices that had both been shown in the 2006 study to have the best electrical and thermal properties: the IRF6635 and IRF6644. The present study evaluated (1) the relative electrical and thermal performance of both versions of each device, (2) the performance through high reliability testing, and (3) the performance of these devices in combination with a range of alternate solder alloys in the extreme thermal environments of deep space....

electronic parts packaging↗