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Using a finite-field transform, a simplified algorithm for decoding Reed-Solomon codes is developed to correct erasures as well as errors over the finite-field GF(q to the m power), where q is a prime and m is an integer. If the finite-field transform is a fast transform, this decoder can be faster and simpler than a decoder that uses more conventional methods.
A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation are presented. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.
Several error control coding techniques for reliable satellite communications were investigated to find algorithms for fast decoding of Reed-Solomon codes in terms of dual basis. The decoding of the (255,223) Reed-Solomon code, which is used as the outer code in the concatenated TDRSS decoder, was of particular concern.
In most mesosphere-stratosphere-troposphere (MST) applications pulsed radars are peak power limited and have excess average power capability. Short pulses are required for good range resolution but the problem of range biguity (signals received simultaneously from more than one altitude) sets a minimum limit on the interpulse period (IPP). Pulse compression is a echnique which allows more of the transmitter average power capacity to be used without scarificing range resolution. Binary phase coding methods for pulse compression are discussed. Many aspects of codes and decoding and their applications to MST experiments are addressed; this includes Barker codes and longer individual codes, and then complementary codes and other code sets. Software decoding, hardware decoders, and coherent integrators are also discussed.
It is generally recognized that the understanding of the molecular basis of primitive translation is a fundamental step in developing a theory of the origin of life. However, even in modern molecular biology, the mechanism for the decoding of messenger RNA triplet codons into an amino acid sequence of a protein on the ribosome is understood incompletely. Most of the proposed models for prebiotic translation lack, not only experimental support, but also a careful theoretical scrutiny of their compatibility with well understood stereochemical and energetic principles of nucleic acid structure, molecular recognition principles, and the chemistry of peptide bond formation. Present studies are concerned with comparative structural modelling and mechanistic simulation of the decoding apparatus ranging from those proposed for prebiotic conditions to the ones involved in modern biology. Any primitive decoding machinery based on nucleic acids and proteins, and most likely the modern day system, has to satisfy certain geometrical constraints. The charged amino acyl and the peptidyl termini of successive adaptors have to be adjacent in space in order to satisfy the stereochemical requirements for amide bond formation. Simultaneously, the same adaptors have to recognize successive codons on the messenger. This translational complex has to be realized by components that obey nucleic acid conformational principles, stabilities, and specificities. This generalized condition greatly restricts the number of acceptable adaptor structures.
A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this paper we present some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative alorithm to find the error locator polynomial. Two codes are considered: (1) a d sub min = 4 single-byte-error-correcting (SBEC), double-byte-error-detecting (DBED) RS code; and (2) a d sub min = 6 double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS code.
The optimum coding technique for MST (mesosphere stratosphere troposphere) radars is that which gives the lowest possible sidelobes in practice and can be implemented without too much computing power. Coding techniques are described in Farley (1985). A technique mentioned briefly there but not fully developed and not in general use is discussed here. This is decoding by means of a filter which is not matched to the transmitted waveform, in order to reduce sidelobes below the level obtained with a matched filter. This is the first part of the technique discussed here; the second part consists of measuring the transmitted waveform and using it as the basis for the decoding filter, thus reducing errors due to imperfections in the transmitter. There are two limitations to this technique. The first is a small loss in signal to noise ratio (SNR), which usually is not significant. The second problem is related to incomplete information received at the lowest ranges. An appendix shows a technique for handling this problem. Finally, it is shown that the use of complementary codes on transmission and nonmatched decoding gives the lowest possible sidelobe level and the minimum loss in SNR due to mismatch.
A class of bandwidth efficient block codes for M-ary PSK modulation is presented. A soft-decision decoding for this class of codes is devised. Some specific short codes for Quad Phase Shift Key (QPSK), 8-PSK and 16-PSK modulations are constructed. These codes have good minimum squared Euclidean distances and provide 2 to 5.8 dB coding gains over uncoded QPSK modulation without (or with little) bandwidth expansion. The complete weight distributions of these specific codes are determined. Based on these weight distributions, their error probabilities are evaluated. Some of these codes have simple trellis structures and hence can be decoded by Viterbi decoding algorithm with relatively simple implementation. Moreover, the codes are very suitable for use as inner codes for various cascaded coding schemes with Reed-Solomon codes as outer codes.
Advances made in error-correction coding for deep space communications are described. The code believed to be the best is a (15, 1/6) convolutional code, with maximum likelihood decoding; when it is concatenated with a 10-bit Reed-Solomon code, it achieves a bit error rate of 10 to the -6th, at a bit SNR of 0.42 dB. This code outperforms the Voyager code by 2.11 dB. The use of source statics in decoding convolutionally encoded Voyager images from the Uranus encounter is investigated, and it is found that a 2 dB decoding gain can be achieved.
The software developed for the decoding system used in the telemetry link of the Phobos Lander mission is described. Encoders and decoders are provided to cover the three possible telemetry configurations. The software can be used to decode actual data or to simulate the performance of the telemetry system. The theoretical properties of the codes chosen for this mission are analyzed and discussed.
A software package enabling engineers to conduct experiments to determine the actual performance of long constraint-length convolutional codes over the Voyager 1 communication link directly from the Jet Propulsion Laboratory (JPL) has been developed. Using this software, engineers are able to enter test data from the Laboratory in Pasadena, California. The software encodes the data and then sends the encoded data to a personal computer (PC) at the Goldstone Deep Space Complex (GDSC) over telephone lines. The encoded data are sent to the transmitter by the PC at GDSC. The received data, after being echoed back by Voyager 1, are first sent to the PC at GDSC, and then are sent back to the PC at the Laboratory over telephone lines for decoding and further analysis. All of these operations are fully integrated and are completely automatic. Engineers can control the entire software system from the Laboratory. The software encoder and the hardware decoder interface were developed for other applications, and have been modified appropriately for integration into the system so that their existence is transparent to the users. This software provides: (1) data entry facilities, (2) communication protocol for telephone links, (3) data displaying facilities, (4) integration with the software encoder and the hardware decoder, and (5) control functions.
An upper bound on the bit-error probability (BEP) of a linear cyclic code over GF(2 exp l) with hard-decision (HD) maximum-likelihood (ML) decoding on memoryless symmetric channels is derived. Performance results are presented for Reed-Solomon codes on GF(32), GF(64), and GF(128). Also, a union upper bound on the BEP of a linear cyclic code with either HD or soft-decision (SD) ML decoding is developed, as well as the corresponding bounds for the extended code of a linear cyclic code. Using these bounds, which are tight at low bit error rate, the performance advantage of SD and HD ML over bounded-distance decoding is established.
Shortest sequence of bits likely to be filled with error bursts examined. Algorithm improves synchronization of frames of noisy binary-coded data signals after Viterbi decoding (recovery from "inner" convolutional code used in transmission channel) and before Reed-Solomon or other decoding (recovery from "outer" error-correcting block code). Based on comparisons of sequences of correct and erroneous Viterbi-decoded received bits with known marker sequence denoting beginning of frame of data. Does not require count of number of bits in received sequence disagreeing with corresponding bits in marker sequence.
New decoder realized by simplified pipeline architecture. Simplified procedure for correction of errors and erasures in Reed-Solomon codes expected to result in simpler decoding equipment. Development widens commercial applicability of Reed-Solomon codes, used to correct bursts of errors in digital communication and recording systems. Improved decoder less complex. Made more regular, simple, and suitable for implementation in both VLSI and software.
Several modulation and coding advances supported by NASA are summarized. To support long-constraint-length convolutional code, a VLSI maximum-likelihood decoder, utilizing parallel processing techniques, which is being developed to decode convolutional codes of constraint length 15 and a code rate as low as 1/6 is discussed. A VLSI high-speed 8-b Reed-Solomon decoder which is being developed for advanced tracking and data relay satellite (ATDRS) applications is discussed. A 300-Mb/s modem with continuous phase modulation (CPM) and codings which is being developed for ATDRS is discussed. Trellis-coded modulation (TCM) techniques are discussed for satellite-based mobile communication applications.
The decoding and error-correction of data transmitted over a noisy channel is in principle equivalent to the operation of a neural network performing as a content-addressable memory. For a successful application, however, the neural network has to be capable of storing arbitrary words, and it has to be guaranteed that the stored words represent the only stable attractors of the memory. This paper presents a novel high-order neural network architecture that has these characteristics. The analog nature of the network can be used to perform soft-decision decoding with any block code. The performance in terms of postdecoding bit error rate versus SNR is demonstrated for two exemplary block codes. The comparison with a conventional decoding algorithm for a (15,5) cyclic redundancy code shows, for example, that the bit error rate at 7dB SNR can be decreased by two orders of magnitude.
A VLSI coder is presented that can function either as an encoder or decoder for Reed-Solomon codes. VLSI is one approach to implementing high-performance Reed-Solomon decoders. There are three VLSI technologies that could be used: gate arrays, standard cells, and full custom. The first two approaches are relatively easy to implement, but are limited in both performance and density. Full-custom VLSI is used to achieve both circuit density and speed, and allows control of the amount of interconnect. Speed, which is a function of capacitance, which is a function of interconnect, is an important parameter in high-performance VLSI. A single 8.2 mm x 8.4 mm, 200,000 transistor CMOS chip implementation of the Reed-Solomon code required by the Hubble Space Telescope is reported. The chip features a 10-MHz sustained byte rate independent of error pattern. The 1.6-micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes and shortened codes are supported with no external buffering. Erasure corrections and random error corrections are supported with programmable correction of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors in the incoming message.
As systems designers design communication systems with digital rather than analog components to reduce noise and increase channel capacity, they must have the ability to perform traditional communication algorithms digitally. The use of trellis coded modulation as well as the extensive use of convolutional encoding for error detection and correction requires an efficient digital implementation of the Viterbi Algorithm for real time demodulation and decoding. Digital signal processors are now fast enough to implement Viterbi decoding in conjunction with the normal receiver/transmitter functions for lower speed channels on a single chip as well as performing fast decoding for higher speed channels, if the algorithm is implemented efficiently. The purpose of this paper is to identify a good way to implement the Viterbi Algorithm (VA) on the Motorola DSP56001, balancing performance considerations with speed and memory efficiency.