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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 505 records · Page 28

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NASA NTRS1981

A seismic signal processor suitable for use with the NOAA/GOES satellite data collection system

Because of the high data-rate requirements, a practical system capable of collecting seismic information in the field and relaying it, via satellite, to a central collection point is not yet available. A seismic signal processor has been developed and tested for use with the NOAA/GOES satellite data collection system. Performance tests on recorded, as well as real time, short period signals indicate that the event recognition technique used is nearly perfect in its rejection of environmental noise and other non-seismic signals and that, with the use of solid state buffer memories, data can be acquired in many swarm situations. The design of a complete field data collection platform is discussed based on the prototype evaluation.

Webster, W. J., Jr.↗

NASA NTRS1980

Evaluation of a three-processor architecture for a satellite packet switch

The architecture of a microprocessor-based packet switch using three processors for use on-board satellites is presented. The operation of the switch involves three distinct functions, namely, the input, the routing and the output functions. Each of these functions is performed by one of the three microprocessors. The operation of the switch along with those of the corresponding software routines are explained. An expression for the throughput is presented. A queue theoretic model of the switch is developed. Analytical expressions for the overall average response time at the various queues are obtained. A number of graphs showing the average response time as a function of some parameters of the switch are also presented.

Arozullakh, M.↗

NASA NTRS1981

Extended operating range of the 30-cm ion thruster with simplified power processor requirements

A 30-cm-diameter Hg ion thruster similar in design to the J-series thruster was operated at fixed conditions with only five power supplies and was throttled over the baseline power range with six supplies. An analysis of the functional model power processor showed that the component mass and parts count would be reduced by about 14 and 35% respectively, and the electrical efficiency would be increased about 1.5% by replacing power supplies with relays. By introducing new circuit designs, additional reductions in the component mass and parts, as well as an increase in electrical efficiency would be expected. The impact on thruster performance of reducing the number of power supplies was to lower the propellant utilization efficiency about 1.0% and raise the electrical efficiency values from 0.2 to 1.3% over the throttle range.

Rawlin, V. K.↗

NASA NTRS1980

Inventory estimation on the massively parallel processor

This paper describes algorithms for efficiently computing inventory estimates from satellite based images. The algorithms incorporate a one dimensional feature extraction which optimizes the pairwise sum of Fisher distances. Biases are eliminated with a premultiplication by the inverse of the analytically derived error matrix. The technique is demonstrated with a numerical example using statistics obtained from an actual Landsat scene. Attention was given to implementation of the Massively Parallel processor (MPP). A timing analysis demonstrates that the inventory estimation can be performed an order of magnitude faster on the MPP than on a conventional serial machine.

Argentiero, P. D.↗

NASA NTRS1983

Processor Generates and Extracts Silicon

Processor under development continuously generates pure silicon and separates it from reaction by-products. Silicon separator/collector intercepts impinging jet of reaction products and selectively funnels silicon into larger collector. Salt byproduct is removed by tubular condenser held at 1,000 degrees C, and then flows into collector, where it solidifies. Vacuum locks permit periodic salt removal without disturbing continuous operation.

Gould, R. K.↗

NASA NTRS1981

Energy normalization of TV viewed optical correlation (automated correlation plane analyzer for an optical processor)

An automatic correlation plane processor that can rapidly acquire, identify, and locate the autocorrelation outputs of a bank of multiple optical matched filters is described. The read-only memory (ROM) stored digital silhouette of each image associated with each matched filter allows TV video to be used to collect image energy to provide accurate normalization of autocorrelations. The resulting normalized autocorrelations are independent of the illumination of the matched input. Deviation from unity of a normalized correlation can be used as a confidence measure of correct image identification. Analog preprocessing circuits permit digital conversion and random access memory (RAM) storage of those video signals with the correct amplitude, pulse width, rising slope, and falling slope. TV synchronized addressing of 3 RAMs permits on-line storage of: (1) the maximum unnormalized amplitude, (2) the image x location, and (3) the image y location of the output of each of up to 99 matched filters. A fourth RAM stores all normalized correlations. A normalization approach, normalization for cross correlations, a system's description with block diagrams, and system's applications are discussed.

Grumet, A.↗

NASA NTRS1981

Iterative optical vector-matrix processors (survey of selected achievable operations)

An iterative optical vector-matrix multiplier with a microprocessor-controlled feedback loop capable of performing a wealth of diverse operations was described. A survey and description of many of its operations demonstrates the versatility and flexibility of this class of optical processor and its use in diverse applications. General operations described include: linear difference and differential equations, linear algebraic equations, matrix equations, matrix inversion, nonlinear matrix equations, deconvolution and eigenvalue and eigenvector computations. Engineering applications being addressed for these different operations and for the IOP are: adaptive phased-array radar, time-dependent system modeling, deconvolution and optimal control.

Casasent, D.↗

NASA NTRS1981

Computer program documentation for the patch subsampling processor

The programs presented are intended to provide a way to extract a sample from a full-frame scene and summarize it in a useful way. The sample in each case was chosen to fill a 512-by-512 pixel (sample-by-line) image since this is the largest image that can be displayed on the Integrated Multivariant Data Analysis and Classification System. This sample size provides one megabyte of data for manipulation and storage and contains about 3% of the full-frame data. A patch image processor computes means for 256 32-by-32 pixel squares which constitute the 512-by-512 pixel image. Thus, 256 measurements are available for 8 vegetation indexes over a 100-mile square.

Nieves, M. J.↗

NASA NTRS1980

Design of a recursive vector processor using polynomial splines

The problem of obtaining smoothed estimates of function values, particularly their derivatives, from a finite set of inaccurate measurements is considered. A recursive two-dimensional vector processor is introduced as an approximation to the nonrecursive constrained least-squares estimation. Here, piecewise bicubic Hermite polynomials are extensively used as approximating functions, and the smoothing integral is converted to a discrete quadratic form. This makes it possible to convert the problem of fitting an approximating function to one of estimating the function values and derivatives at the nodes.

Kim, C. S.↗

NASA NTRS1984

Digital SAR Processor

Produces real-time, single-look, high-resolution imagery. Digital synthetic-aperature-radar (SAR) processor achieves rate of 4 million samples per second. System combines frequency-domain and time-domain processing for two-dimensional azimuth correlation.

Wu, C.↗

NASA NTRS1982

Recent developments of NASTRAN pre- amd post-processors: Response spectrum analysis (RESPAN) and interactive graphics (GIFTS)

Two specific NASTRAN preprocessors and postprocessors are examined. A postprocessor for dynamic analysis and a graphical interactive package for model generation and review of resuls are presented. A computer program that provides response spectrum analysis capability based on data from NASTRAN finite element model is described and the GIFTS system, a graphic processor to augment NASTRAN is introduced.

Hirt, E. F.↗

NASA NTRS1982

The language parallel Pascal and other aspects of the massively parallel processor

A high level language for the Massively Parallel Processor (MPP) was designed. This language, called Parallel Pascal, is described in detail. A description of the language design, a description of the intermediate language, Parallel P-Code, and details for the MPP implementation are included. Formal descriptions of Parallel Pascal and Parallel P-Code are given. A compiler was developed which converts programs in Parallel Pascal into the intermediate Parallel P-Code language. The code generator to complete the compiler for the MPP is being developed independently. A Parallel Pascal to Pascal translator was also developed. The architecture design for a VLSI version of the MPP was completed with a description of fault tolerant interconnection networks. The memory arrangement aspects of the MPP are discussed and a survey of other high level languages is given.

Reeves, A. P.↗

NASA NTRS1983

Measurement of fault latency in a digital avionic mini processor, part 2

The results of fault injection experiments utilizing a gate-level emulation of the central processor unit of the Bendix BDX-930 digital computer are described. Several earlier programs were reprogrammed, expanding the instruction set to capitalize on the full power of the BDX-930 computer. As a final demonstration of fault coverage an extensive, 3-axis, high performance flght control computation was added. The stages in the development of a CPU self-test program emphasizing the relationship between fault coverage, speed, and quantity of instructions were demonstrated.

Mcgough, J.↗

NASA NTRS1983

Massively parallel processor computer

An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array is described. It comprises a large number (e.g., 16,384 in a 128 x 128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered parallel data, including spatial translation by shifting or sliding of bits vertically or horizontally to neighboring processing elements.

Fung, L. W.↗

NASA NTRS1983

DBPQL: A view-oriented query language for the Intel Data Base Processor

An interactive query language (BDPQL) for the Intel Data Base Processor (DBP) is defined. DBPQL includes a parser generator package which permits the analyst to easily create and manipulate the query statement syntax and semantics. The prototype language, DBPQL, includes trace and performance commands to aid the analyst when implementing new commands and analyzing the execution characteristics of the DBP. The DBPQL grammar file and associated key procedures are included as an appendix to this report.

Fishwick, P. A.↗

NASA NTRS1983

Triangular system solutions on an optical systolic processor

It is noted that the simplified system of equations presented by Casasent and Ghosh (1983) can also be solved optically. One realization of this is described, with attention given to data flow and speed for the case of a lower triangular system of equations. The solution of an upper triangular system of equations can be handled in analogous fashion. The problem requires a matrix-vector processor. Only one carrier frequency input to the acoustooptic cell and only one output detector are used. To multiply a matrix by a vector in this system, the time-multiplexed vector elements are fed into the acoustooptic cell.

Ghosh, A.↗

NASA NTRS1982

A network control concept for the 30/20 GHz communication system baseband processor

The architecture and system design for a satellite-switched TDMA communication system employing on-board processing was developed by Motorola for NASA's Lewis Research Center. The system design is based on distributed processing techniques that provide extreme flexibility in the selection of a network control protocol without impacting the satellite or ground terminal hardware. A network control concept that includes system synchronization and allows burst synchronization to occur within the system operational requirement is described. This concept integrates the tracking and control links with the communication links via the baseband processor, resulting in an autonomous system operational approach.

Sabourin, D. J.↗

NASA NTRS1985

NASTRAN NASTPLT Plotting Post Processor

NASTRAN NASTPLT Plotting Post Processor reads NASTRAN-generated NASTPLT plot files, checks file contents for validity and translates NASTPLT plot commands into appropriate calls to plotting routines for either CALCOMP Tektronix PLOT10, or Versatec plotting systems.

Strang, R.↗