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At least 523 records · Page 29
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

NASA GRC and MSFC Space-Plasma Arc Testing Procedures

Tests of arcing and current collection in simulated space plasma conditions have been performed at the NASA Glenn Research Center (GRC) in Cleveland, Ohio, for over 30 years and at the Marshall Space Flight Center (MSFC) in Huntsville, Alabama, for almost as long. During this period, proper test conditions for accurate and meaningful space simulation have been worked out, comparisons with actual space performance in spaceflight tests and with real operational satellites have been made, and NASA has achieved our own internal standards for test protocols. It is the purpose of this paper to communicate the test conditions, test procedures, and types of analysis used at NASA GRC and MSFC to the space environmental testing community at large, to help with international space-plasma arcing-testing standardization. To be discussed are: 1.Neutral pressures, neutral gases, and vacuum chamber sizes. 2. Electron and ion densities, plasma uniformity, sample sizes, and Debuy lengths. 3. Biasing samples versus self-generated voltages. Floating samples versus grounded. 4. Power supplies and current limits. Isolation of samples from power supplies during arcs. 5. Arc circuits. Capacitance during biased arc-threshold tests. Capacitance during sustained arcing and damage tests. Arc detection. Prevention sustained discharges during testing. 6. Real array or structure samples versus idealized samples. 7. Validity of LEO tests for GEO samples. 8. Extracting arc threshold information from arc rate versus voltage tests. 9. Snapover and current collection at positive sample bias. Glows at positive bias. Kapon (R) pyrolisis. 10. Trigger arc thresholds. Sustained arc thresholds. Paschen discharge during sustained arcing. 11. Testing for Paschen discharge threshold. Testing for dielectric breakdown thresholds. Testing for tether arcing. 12. Testing in very dense plasmas (ie thruster plumes). 13. Arc mitigation strategies. Charging mitigation strategies. Models. 14. Analysis of test results. Finally, the necessity of testing will be emphasized, not to the exclusion of modeling, but as part of a complete strategy for determining when and if arcs will occur, and preventing them from occurring in space.

Ferguson, Dale C.↗
NASA NTRS2005

Arcing in LEO - Does the Whole Array Discharge?

The conventional wisdom about solar array arcing in LEO is that only the parts the solar array that are swept over by the arc-generated plasma front are discharged in the initial arc. This limits the amount of energy that can be discharged. Recent work done at the NASA Glenn Research Center has shown that this idea is mistaken. In fact, the capacitance of the entire solar array may be discharged, which for large arrays leads to very large and possibly debilitating arcs, even if no sustained arc occurs. We present the laboratory work that conclusively demonstrates this fact by using a grounded plate that prevents the arc-plasma front from reaching certain array strings. Finally, we discuss the dependence of arc strength and arc pulse width on the capacitance that is discharged, and provide a physical mechanism for discharge of the entire array, even when parts of the array are not accessible to the arc-plasma front. Mitigation techniques are also presented.

Ferguson, Dale C.↗
NASA NTRS2005

Arcing in LEO: Does the Whole Array Discharge?

The conventional wisdom about solar array arcing in LEO is that only the parts of the solar array that are swept over by the arc-generated plasma front are discharged in the initial arc. This limits the amount of energy that can be discharged. Recent work done at the NASA Glenn Research Center has shown that this idea is mistaken. In fact, the capacitance of the entire solar array may be discharged, which for large arrays leads to very large and possibly debilitating arcs, even if no sustained arc occurs. We present the laboratory work that conclusively demonstrates this fact by using a grounded plate that prevents the arc-plasma front from reaching certain array strings. Finally, we discuss the dependence of arc strength and arc pulse width on the capacitance that is discharged, and provide a physical mechanism for discharge of the entire array, even when parts of the array are not accessible to the arc-plasma front. Mitigation techniques are also presented.

Ferguson, Dale C.↗
NASA NTRS2005

NASA GRC and MSFC Space-Plasma Arc Testing Procedures

Tests of arcing and current collection in simulated space plasma conditions have been performed at the NASA Glenn Research Center (GRC) in Cleveland, Ohio, for over 30 years and at the Marshall Space flight Center (MSFC) for almost as long. During this period, proper test conditions for accurate and meaningful space simulation have been worked out, comparisons with actual space performance in spaceflight tests and with real operational satellites have been made, and NASA has achieved our own internal standards for test protocols. It is the purpose of this paper to communicate the test conditions, test procedures, and types of analysis used at NASA GRC and MSFC to the space environmental testing community at large, to help with international space-plasma arcing testing standardization. To be discussed are: 1. Neutral pressures, neutral gases, and vacuum chamber sizes. 2. Electron and ion densities, plasma uniformity, sample sizes, and Debye lengths. 3. Biasing samples versus self-generated voltages. Floating samples versus grounded. 4. Power supplies and current limits. Isolation of samples from power supplies during arcs. Arc circuits. Capacitance during biased arc-threshold tests. Capacitance during sustained arcing and damage tests. Arc detection. Preventing sustained discharges during testing. 5. Real array or structure samples versus idealized samples. 6. Validity of LEO tests for GEO samples. 7. Extracting arc threshold information from arc rate versus voltage tests. 8 . Snapover and current collection at positive sample bias. Glows at positive bias. Kapton pyrolization. 9. Trigger arc thresholds. Sustained arc thresholds. Paschen discharge during sustained arcing. 10. Testing for Paschen discharge thresholds. Testing for dielectric breakdown thresholds. Testing for tether arcing. 11. Testing in very dense plasmas (ie thruster plumes). 12. Arc mitigation strategies. Charging mitigation strategies. Models. 13. Analysis of test results. Finally, the necessity of testing will be emphasized, not to the exclusion of modeling, but as part of a complete strategy for determining when and if arcs will occur, and preventing them from occurring in space.

Ferguson, Dale C.a↗
NASA NTRS2000

Radio Frequency (RF) Micro-Electromechanical Systems (MEMS) Switches for Space Communications

Micro-electromechanical systems (MEMS) is an emerging technology for radio frequency (RF) systems because it has the potential to dramatically decrease loss and improve efficiency. In this paper, we address the design and fabrication of novel MEMS switches being developed at NASA Glenn Research Center. Two types of switches are being developed: a microstrip series single pole single throw (SPST) switch and a coplanar waveguide (CPW) series SPST and single pole double throw (SPDT) switches. These are being fabricated as an integral part of 50 Ohm microstrip and CPW RF integrated circuits using microfabrication techniques. The construction of the switch relies on a cantilever beam that is partially supported by a dielectric post. The cantilever beam is electro-magnetically actuated. To decrease stiction, a Si3N4 thin film is deposited over the contact area. Thus, when the switch is closed, the ON-state insertion loss is governed by the parallel plate capacitance formed by the two contacts. The isolation in the OFF-state is governed by the parasitic capacitance when the cantilever is in the up position. RF MEMS switches have been demonstrated with 80% lower insertion loss than conventional solid state devices (GaAs Metal Semiconductor Field Effect Transistors (MESFETs) and Silicon PIN diodes) based switches. For example, a conventional GaAs five-bit phase shifter which is required for beam steering in a phased array antenna has approximately 7 dB of insertion loss at 26.5 GHz where as a comparable MEMS based phase shifter is expected to have only 2 dB of insertion loss. This translates into 56% lower power dissipation and therefore decreases the thermal load on the spacecraft and also reduces the power amplifier requirements. These benefits will enable NASA to build the next generation of deep space science crafts and micro/nano satellites.

Simons, Rainee N.↗
NASA NTRS2006

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

Shuler, Robert L.↗
NASA NTRS2005

A wide-band dual-polarized VHF microstrip antenna for global sensing of sea ice thickness

A VHF microstrip patch antenna was developed to achieve a bandwidth of 45 MHz (30%) from 127 MHz to 172 MHz with dual-linear-polarization capability. This microstrip antenna used foam substrates and dual stacked patches with capacitive probe feeds to achieve wide bandwidth. Four such capacitive feeds were used to achieve dual polarizations with less than -20 dB of cross-polarization level. Twenty-four shorting pins were used on the lower patch to achieve acceptable isolation between the four feed probes. This antenna has a measured gain of 8.5 dB at 137 MHz and 10 dB at 162 MHz. By using the Method of Moments technique, multipath scattering patterns were calculated when the antenna is mounted on the outside of a Twin Otter aircraft.

VHF↗
NASA NTRS2006

A Magnetic Field Response Recorder: A New Tool for Measurement Acquisition

A magnetic field response recorder was developed to facilitate a measurement acquisition method that uses magnetic fields to power and to interrogate all sensors. Sensors are designed as electrically passive inductive-capacitive or passive inductive-capacitive-resistive circuits that produce magnetic field responses when electrically activated by oscillating magnetic fields. When electrically activated, the sensor's magnetic field response attributes (frequency, amplitude and bandwidth) correspond to the one or more physical states that each sensor measures. The response recorder makes it possible to simultaneously measure two unrelated physical properties using this class of sensors. The recorder is programmable allowing it to analyze one or more response attributes simultaneously. A single sensor design will be used to demonstrate that the acquisition method and the sensor example can be used to for all phases of a component's life from manufacturing to damage that can destroy it.

Woodard, Stanley E.↗
NASA NTRS2007

Role for Lower Extremity Interstitial Fluid Volume Changes in the Development of Orthostasis after Simulated Microgravity

Reentry orthostasis after exposure to the conditions of spaceflight is a persistent problem among astronauts. In a previous study, a computer model systems analysis was used to examine the physiologic mechanisms involved in this phenomenon. In this analysis, it was determined that an augmented capacitance of lower extremity veins due to a fluid volume contracture of the surrounding interstitial spaces during spaceflight results in an increase in sequestered blood volume upon standing and appears to be the initiating mechanism responsible for reentry orthostasis. In this study, we attempt to validate the central premise of this hypothesis using a ground-based spaceflight analog. 10 healthy subjects were placed at bed rest in a 6 head down tilt position for 60 days of bed rest. The impact of adaptations in interstitial fluid volume and venous capacitance in the lower extremities were then observed during a standard tilt test protocol performed before and after the confinement period. The interstitial thickness superficial to the calcaneous immediately below the lateral malleolus was measured using ultrasound with a 17-5 MHz linear array transducer. Measurements of the changes in anterior tibial vein diameter during tilt were obtained by similar methods. The measurements were taken while the subjects were supine and then during upright tilt (80') for thirty minutes, or until the subject had signs of presyncope. Additional measurements of the superficial left tibia interstitial thickness and stroke volume by standard echocardiographic methods were also recorded. In addition, calf compliance was measured over a pressure range of 10-60 mmHg, using plethysmography, in a subset of these subjects (n = 5). There was a average of 6% diminution in the size of the lower extremity interstitial space as compared to measurements acquired prior to bed rest. This contracture of the interstitial space coincided with a subsequent relative increase in the percentage change in tibial vein diameter and stroke volume upon tilting in contrast to the observations made before bed rest (54 vs 23% respectively). Compliance in the calf increased by an average of 36% by day 27 of bedrest. A systems analysis using a computer model of cardiovascular physiology suggests that microgravity induced interstitial volume depletion results in an accentuation of venous blood volume sequestration and is the initiating event in reentry orthostasis. This hypothesis was tested in volunteer subjects using a ground-based spaceflight analog model that simulated the body fluid redistribution induced by microgravity exposure. Measurements of changes in the interstitial spaces and observed responses of the anterior tibial vein with tilt, together with the increase in calf compliance, were consistent with our proposed mechanism for the initiation of postflight orthostasis often seen in astronauts.

Platts, Steven H.↗
NASA NTRS1980

Edge smoothing for real-time simulation of a polygon face object system as viewed by a moving observer

The visual system within an aircraft flight simulation system receives flight data and terrain data which is formated into a buffer memory. The image data is forwarded to an image processor which translates the image data into face vertex vectors Vf, defining the position relationship between the vertices of each terrain object and the aircraft. The image processor then rotates, clips, and projects the image data into two-dimensional display vectors (Vd). A display generator receives the Vd faces, and other image data to provide analog inputs to CRT devices which provide the window displays for the simulated aircraft. The video signal to the CRT devices passes through an edge smoothing device which prolongs the rise time (and fall time) of the video data inversely as the slope of the edge being smoothed. An operational amplifier within the edge smoothing device has a plurality of independently selectable feedback capacitors each having a different value. The values of the capacitors form a series which doubles as a power of two. Each feedback capacitor has a fast switch responsive to the corresponding bit of a digital binary control word for selecting (1) or not selecting (0) that capacitor. The control word is determined by the slope of each edge. The resulting actual feedback capacitance for each edge is the sum of all the selected capacitors and is directly proportional to the value of the binary control word. The output rise time (or fall time) is a function of the feedback capacitance, and is controlled by the slope through the binary control word.

Lotz, Robert W.↗
NASA NTRS1980

DC-to-DC switching converter

A dc-to-dc converter having nonpulsating input and output current uses two inductances, one in series with the input source, the other in series with the output load. An electrical energy transferring device with storage, namely storage capacitance, is used with suitable switching means between the inductances to DC level conversion. For isolation between the source and load, the capacitance may be divided into two capacitors coupled by a transformer, and for reducing ripple, the inductances may be coupled. With proper design of the coupling between the inductances, the current ripple can be reduced to zero at either the input or the output, or the reduction achievable in that way may be divided between the input and output.

Cuk, Slobodan M.↗
NASA NTRS2002

Silicon base plate with low parasitic electrical interference for sensors

A microgyroscope has a baseplate made of the same material as the rest of the microgyroscope. The baseplate is a silicon baseplate having a heavily p-doped epilayer covered by a thick dielectric film and metal electrodes. The metal electrodes are isolated from the ground plane by the dielectric. This provides very low parasitic capacitive coupling between the electrodes. The thick dielectric reduces the capacitance between the electrodes and the ground plane.

Tang, Tony K.↗
NASA NTRS1986

Silicon controlled rectifier polyphase bridge inverter commutated with gate-turn-off thyristor

A polyphase SCR inverter (10) having N switching poles, each comprised of two SCR switches (1A, 1B; 2A, 2B . . . NA, NB) and two diodes (D1B; D1B; D2A, D2B . . . DNA, DNB) in series opposition with saturable reactors (L1A, L1B; L2A, L2B . . . LNA, LNB) connecting the junctions between the SCR switches and diodes to an output terminal (1, 2 . . . 3) is commutated with only one GTO thyristor (16) connected between the common negative terminal of a dc source and a tap of a series inductor (14) connected to the positive terminal of the dc source. A clamp winding (22) and diode (24) are provided, as is a snubber (18) which may have its capacitance (c) sized for maximum load current divided into a plurality of capacitors (C.sub.1, C.sub.2 . . . C.sub.N), each in series with an SCR switch S.sub.1, S.sub.2 . . . S.sub.N). The total capacitance may be selected by activating selected switches as a function of load current. A resistor 28 and SCR switch 26 shunt reverse current when the load acts as a generator, such as a motor while braking.

Edwards, Dean B.↗
NASA NTRS1989

Monolithic transistor gate energy recovery system

Energy is recovered from an insulated gate semiconductor switch, such as a MOSFET, that is otherwise lost in the gate capacitance by producing a notch in the gate control voltage for an interval B following an interval A after initial application of a gate control voltage pulse for turning the switch on, and a notch for an interval C following termination of the gate control voltage pulse followed by interval D during which the switch is turned on again, where each interval is a period .DELTA.T given by ##EQU1## L.sub.s is the inductance (discrete and/or parasitic) in series with the gate electrode of the insulated gate semiconductor switch, and C.sub.in is the capacitance of that switch between its gate and source electrodes. The interval .DELTA.T may be provided directly by timing in a pulse forming circuit for the gate control voltage applied, or adaptively by sensing the gate voltage v.sub.g and comparing it with fixed progressively higher voltages v.sub.1, v.sub.2 and v.sub.3, where v.sub.2 is intermediate v.sub.1 and v.sub.3 which correspond to the lower and upper levels of v.sub.g as the switch is turned off and on.

Rippel, Wally E.↗
NASA NTRS2007

Wireless Fluid Level Measuring System

A level-sensing probe positioned in a tank is divided into sections with each section including (i) a fluid-level capacitive sensor disposed along the length thereof, (ii) an inductor electrically coupled to the capacitive sensor, (iii) a sensor antenna positioned for inductive coupling to the inductor, and (iv) an electrical conductor coupled to the sensor antenna. An electrically non-conductive housing accessible from a position outside of the tank houses antennas arrayed in a pattern. Each antenna is electrically coupled to the electrical conductor from a corresponding one of the sections. A magnetic field response recorder has a measurement head with transceiving antennas arrayed therein to correspond to the pattern of the housing's antennas. When a measurement is to be taken, the measurement head is mechanically coupled to the housing so that each housing antenna is substantially aligned with a specific one of the transceiving antennas.

Taylor, Bryant D.↗
NASA NTRS2008

RF MEMS Switches with SiC Microbridges for Improved Reliability

Radio frequency (RF) microelectromechanical (MEMS) switches offer superior performance when compared to the traditional semiconductor devices such as PIN diodes or GaAs transistors. MEMS switches have a return loss (RL) better than -25 dB, negligible insertion loss (IL), isolation better than -30 dB, and near zero power consumption. However, RF MEMS switches have several drawbacks the most serious being long-term reliability. The ability for the switch to operate for millions or even billions of cycles is a major concern and must be addressed. MEMS switches are basically grouped in two categories, capacitive and metal-to-metal contact. The capacitive type switch consists of a movable metal bridge spanning a fixed electrode and separated by a narrow air gap and thin insulating material. The metal-to-metal contact type utilizes the same basic design but without the insulating material. After prolonged operation the metal bridges, in most of these switches, begin to sag and eventually fail to actuate. For the metal-to-metal type, the two metal layers may actually fuse together. Also if the switches are not packaged properly or protected from the environment moisture may build up and cause stiction between the top and bottom electrodes rendering them useless. Many MEMS switch designs have been developed and most illustrate fairly good RF characteristics. Nevertheless very few have demonstrated both great RF performance and ability to perform millions/billions of switching cycles. Of these, nearly all are of metal-to-metal type so as the frequency increases RF performance decreases.

Scardelletti, Maximilian C.↗
NASA NTRS2008

Linear dynamic range enhancement in a CMOS imager

A CMOS imager with increased linear dynamic range but without degradation in noise, responsivity, linearity, fixed-pattern noise, or photometric calibration comprises a linear calibrated dual gain pixel in which the gain is reduced after a pre-defined threshold level by switching in an additional capacitance. The pixel may include a novel on-pixel latch circuit that is used to switch in the additional capacitance.

Pain, Bedabrata↗
NASA NTRS2009

Improved Signal Chains for Readout of CMOS Imagers

An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

Pain, Bedabrata↗