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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2019

Optimization of Condensed Matter Physics Application with OpenMP Tasking Model

The Density Matrix Renormalization Group (DMRG++) is a condensed matter physics application used to study superconductivity properties of materials. It’s main computations consist of calculating hamiltonian matrix which requires sparse matrix-vector multiplications. This paper presents task-based parallelization and optimization strategies of the Hamiltonian algorithm. The algorithm is implemented as a mini-application in C++ and parallelized with OpenMP. The optimization leverages tasking features, such as dependencies or priorities included in the OpenMP standard 4.5. The code refactoring targets performance as much as programmability. The optimized version achieves a speedup of 8.0× with 8 threads and 20.5× with 40 threads on a Power9 computing node while reducing the memory consumption to 90 MB with respect to the original code, by adding less than ten OpenMP directives.

Criado, Joel↗
DOE OSTI2022

Data-driven modeling of coarse mesh turbulence for reactor transient analysis using convolutional recurrent neural networks

Advanced nuclear reactors often exhibit complex thermal-fluid phenomena during transients. To accurately capture such phenomena, a coarse-mesh three-dimensional (3-D) modeling capability is desired for modern nuclear-system code. In the coarse-mesh 3-D modeling of advanced-reactor transients that involve flow and heat transfer, accurately predicting the turbulent viscosity is a challenging task that requires an accurate and computationally efficient model to capture the unresolved fine-scale turbulence. In this work, we propose a data-driven coarse-mesh turbulence model based on local flow features for the transient analysis of thermal mixing and stratification in a sodium-cooled fast reactor. The model has a coarse mesh setup to ensure computational efficiency, while it is trained by fine-mesh computational fluid dynamics (CFD) data to ensure accuracy. A novel neural network architecture, combining a densely connected convolutional network and a long-short-term-memory network, is developed that can efficiently learn from the spatial temporal CFD transient simulation results. The neural network model was trained and optimized on a loss-of flow transient and demonstrated high accuracy in predicting the turbulent viscosity field during the whole transient. The trained model's generalization capability was also investigated on two other transients with different inlet conditions. The study demonstrates the potential of applying the proposed data-driven approach to support the coarse-mesh multi-dimensional modeling of advanced reactors.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2019

Charge Transition of Oxygen Vacancies during Resistive Switching in Oxide-Based RRAM

Resistive random-access memory (RRAM) devices have attracted broad interest as promising building blocks for high-density nonvolatile memory and neuromorphic computing applications. Atomic level thermodynamic and kinetic descriptions of resistive switching (RS) processes are essential for continued device design and optimization but are relatively lacking for oxide-based RRAMs. It is generally accepted that RS occurs due to the redistribution of charged oxygen vacancies driven by an external electric field. However, this assumption contradicts the experimentally observed stable filaments, where the high vacancy concentration should lead to a strong Coulomb repulsion and filament instability. In this work, through predictive atomistic calculations in combination with experimental measurements, we attempt to understand the interactions between oxygen vacancies and the microscopic processes that are required for stable RS in a Ta 2 O 5 -based RRAM. We propose a model based on a series of charge transition processes that explains the drift and aggregation of vacancies during RS. The model was validated by experimental measurements where illuminated devices exhibit accelerated RS behaviors during SET and RESET. The activation energies of ion migration and charge transition were further experimentally determined through a transient current measurement, consistent with the modeling results. Finally, our results help provide comprehensive understanding on the internal dynamics of RS and will benefit device optimization and applications.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2016

Retention modeling for ultra-thin density of Cu-based conductive bridge random access memory (CBRAM)

We investigate the effect of Cu concentration On-state resistance retention characteristics of W/Cu/Ti/HfO{sub 2}/Pt memory cell. The development of RRAM device for application depends on the understanding of the failure mechanism and the key parameters for device optimization. In this study, we develop analytical expression for cations (Cu{sup +}) diffusion model using Gaussian distribution for detailed analysis of data retention time at high temperature. It is found that the improvement of data retention time depends not only on the conductive filament (CF) size but also on Cu atoms concentration density in the CF. Based on the simulation result, better data retention time is observed for electron wave function associated with Cu{sup +} overlap and an extended state formation. This can be verified by analytical calculation of Cu atom defects inside the filament, based on Cu{sup +} diffusion model. The importance of Cu diffusion for the device reliability and the corresponding local temperature of the filament were analyzed by COMSOL Multiphysics simulation.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2021

Co-design of Advanced Architectures for Graph Analytics using Machine Learning

A graph is an excellent way of representing relationships among entities. We can use graph analytics to synthesize and analyze such relational data, and extract relevant features that are useful for various tasks such as machine learning. Considering the crucial role of graph analytics in various domains, it is important and timely to investigate the right hardware configurations that can achieve optimal performance for graph workloads on future high-performance computing systems. Design space exploration studies facilitate the selection of appropriate configurations (e.g. memory) to achieve a desired system performance. Recently, the approach of accelerating graph analytics using persistent non-volatile memory has gained a lot of attention. Traditional system simulators such as Gem5 and NVMain can be used to explore the design space of these advanced memory architectures for graph workloads. However, these simulators are slow in execution thus limiting the efficiency of design space exploration studies. To overcome this challenge, we proposed a machine learning based approach to co-design advanced memory architectures for graph workloads. We tested our approach with DRAM, non-volatile memory, and hybrid memory (DRAM+NVM) using a breadth first search benchmark algorithm. Our results showed the applicability of the proposed machine learning based approach to the co-design of the advanced memory architectures. In this paper, we provide recommendations on selecting advanced memory architectures to achieve desired performance for graph workloads. We also discuss the performances of different machine learning models that were considered in this study.

Kurte, Kuldeep↗
DOE OSTI2017

Evaluation of the Single-precision Floatingpoint Vector Add Kernel Using the Intel FPGA SDK for OpenCL

Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication and kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

Modeling the Virtual Machine Launching Overhead under Fermicloud

FermiCloud is a private cloud developed by the Fermi National Accelerator Laboratory for scientific workflows. The Cloud Bursting module of the FermiCloud enables the FermiCloud, when more computational resources are needed, to automatically launch virtual machines to available resources such as public clouds. One of the main challenges in developing the cloud bursting module is to decide when and where to launch a VM so that all resources are most effectively and efficiently utilized and the system performance is optimized. However, based on FermiCloud’s system operational data, the VM launching overhead is not a constant. It varies with physical resource (CPU, memory, I/O device) utilization at the time when a VM is launched. Hence, to make judicious decisions as to when and where a VM should be launched, a VM launch overhead reference model is needed. The paper is to develop a VM launch overhead reference model based on operational data we have obtained on FermiCloud and uses the reference model to guide the cloud bursting process.

Garzoglio, Gabriele↗
DOE OSTI2014

Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2013

Software design space exploration for exascale combustion co-design

The design of hardware for next-generation exascale computing systems will require a deep understanding of how software optimizations impact hardware design trade-offs. In order to characterize how co-tuning hardware and software parameters affects the performance of combustion simulation codes, we created ExaSAT, a compiler-driven static analysis and performance modeling framework. Our framework can evaluate hundreds of hardware/software configurations in seconds, providing an essential speed advantage over simulators and dynamic analysis techniques during the co-design process. Our analytic performance model shows that advanced code transformations, such as cache blocking and loop fusion, can have a significant impact on choices for cache and memory architecture. Our modeling helped us identify tuned configurations that achieve a 90% reduction in memory traffic, which could significantly improve performance and reduce energy consumption. These techniques will also be useful for the development of advanced programming models and runtimes, which must reason about these optimizations to deliver better performance and energy efficiency.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2026

Design, characterization and shape recovery behavior of 3D/4D printed shape memory polymers (SMPs)

Shape memory polymers (SMPs) represent a paradigm shift in material science, uniquely capable of undergoing reversible shape transformations triggered by external stimuli, positioning them as pivotal in developing next-generation biomedical devices, aerospace components, and adaptive structures. Extensive research has been done on SMPs with a major focus on high-temperature programming methods, which can limit energy efficiency and applicability with temperature-sensitive materials. Additionally, while various SMP blends have demonstrated great potential, limited work has been done on the suitability for 3D printing these materials, particularly under high-strain and ambient temperature programming conditions. In this study, a three-component optimized SMP composition was evaluated by 3D printing via the Material Extrusion (MEX) technique and investigating its ambient temperature-programming behavior at high strains. The SMP formulation studied was a tailored blend of thermoplastic polyurethane (TPU), polycaprolactone (PCL), and an octadecane diol-based copolymer (OBC) that exhibits robust shape memory behavior, high strain tolerance, and efficient force generation. Rigorous thermal, mechanical, and shape recovery analyses, along with optimized printing parameters and consistent shape recovery rates of up to 90%, were achieved under dynamic mechanical analysis (DMA), even under ambient programming conditions. This work demonstrates the SMP composition’s potential for adaptive, self-deployable systems with 4D printing characteristics ideal for bio-inspired structures and artificial muscle fibers.

Sudan, Kavish [University of Louisville, KY]↗
DOE OSTI2014

Thread-Level Parallelization and Optimization of NWChem for the Intel MIC Architecture

In the multicore era it was possible to exploit the increase in on-chip parallelism by simply running multiple MPI processes per chip. Unfortunately, manycore processors' greatly increased thread- and data-level parallelism coupled with a reduced memory capacity demand an altogether different approach. In this paper we explore augmenting two NWChem modules, triples correction of the CCSD(T) and Fock matrix construction, with OpenMP in order that they might run efficiently on future manycore architectures. As the next NERSC machine will be a self-hosted Intel MIC (Xeon Phi) based supercomputer, we leverage an existing MIC testbed at NERSC to evaluate our experiments. In order to proxy the fact that future MIC machines will not have a host processor, we run all of our experiments in tt native mode. We found that while straightforward application of OpenMP to the deep loop nests associated with the tensor contractions of CCSD(T) was sufficient in attaining high performance, significant effort was required to safely and efficiently thread the TEXAS integral package when constructing the Fock matrix. Ultimately, our new MPI OpenMP hybrid implementations attain up to 65x better performance for the triples part of the CCSD(T) due in large part to the fact that the limited on-card memory limits the existing MPI implementation to a single process per card. Additionally, we obtain up to 1.6x better performance on Fock matrix constructions when compared with the best MPI implementations running multiple processes per card.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

An emerging use-case of machine learning (ML) is to train a model on a high-performance system and deploy the trained model on energy-constrained embedded systems. Neuromorphic hardware platforms, which operate on principles of the biological brain, can significantly lower the energy overhead of a machine learning inference task, making these platforms an attractive solution for embedded ML systems. In this paper, we present a design-technology tradeoff analysis to implement such inference tasks on the processing elements (PEs) of a Non-Volatile Memory (NVM)-based neuromorphic hardware. Through detailed circuit-level simulations at scaled process technology nodes, we show the negative impact of technology scaling on the information-processing latency, which impacts the quality-of-service (QoS) of an embedded ML system. At a finer granularity, the latency inside a PE depends on 1) the delay introduced by parasitic components on its current paths, and 2) the varying delay to sense different resistance states of its NVM cells. Based on these two observations, we make the following three contributions. First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the QoS. Second, on the architecture front, we introduce isolation transistors within each PE to partition it into regions that can be individually power-gated, reducing both latency and energy. Finally, on the system-software front, we propose a mechanism to leverage the proposed technological and architectural enhancements when implementing a machine-learning inference task on neuromorphic PEs of the hardware. Evaluations with a recent neuromorphic hardware architecture show that our proposed design-technology co-optimization approach improves both performance and energy efficiency of machine-learning inference tasks without incurring high cost-per-bit.

42 ENGINEERING↗
DOE OSTI2020

Sage: parallel semi-asymmtric graph algorithms for NVRAMs

Non-volatile main memory (NVRAM) technologies provide an attractive set of features for large-scale graph analytics, including byte-addressability, low idle power, and improved memory-density. NVRAM systems today have an order of magnitude more NVRAM than traditional memory (DRAM). NVRAM systems could therefore potentially allow very large graph problems to be solved on a single machine, at a modest cost. However, a significant challenge in achieving high performance is in accounting for the fact that NVRAM writes can be much more expensive than NVRAM reads. In this paper, we propose an approach to parallel graph analytics using the Parallel Semi-Asymmetric Model (PSAM), in which the graph is stored as a read-only data structure (in NVRAM), and the amount of mutable memory is kept proportional to the number of vertices. Similar to the popular semi-external and semi-streaming models for graph analytics, the PSAM approach assumes that the vertices of the graph fit in a fast read-write memory (DRAM), but the edges do not. In NVRAM systems, our approach eliminates writes to the NVRAM, among other benefits. To experimentally study this new setting, we develop Sage, a parallel semi-asymmetric graph engine with which we implement provably-efficient (and often work-optimal) PSAM algorithms for over a dozen fundamental graph problems. We experimentally study Sage using a 48--core machine on the largest publicly-available real-world graph (the Hyperlink Web graph with over 3.5 billion vertices and 128 billion edges) equipped with Optane DC Persistent Memory, and show that Sage outperforms the fastest prior systems designed for NVRAM. Importantly, we also show that Sage nearly matches the fastest prior systems running solely in DRAM, by effectively hiding the costs of repeatedly accessing NVRAM versus DRAM.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Design of Hopfield Networks Based on Superconducting Coupled Oscillators

The global energy shortage has driven the development of many energy-efficient computational platforms beyond Moore's law, among which brain-inspired neuromorphic computing is one of the promising solutions. Associative memory and pattern recognition are important computations solved by brain-inspired Hopfield networks. Classical Hopfield networks store memories via fixed point attractors of their dynamics. In oscillatory Hopfield networks, these attractors are replaced by periodic orbits. Here, we design an oscillatory Hopfield network based on coupled superconducting oscillators. We first employ a mathematical phase reduction approach to map networks of coupled superconducting rapid single flux quantum (RSFQ) ring oscillators to coupled Kuramoto phase-oscillator networks. We use this theory to numerically optimize the hardware's mutual inductances in order to directly match the phase-reduced superconducting oscillators to a model of phase-oscillator-based Hopfield networks. The resulting network can store multiple oscillatory phase-locked memory patterns and recover the patterns based on the initial phase conditions. As different pattern recognition tasks, or learning, require tunable connectivity strengths between the oscillatory nodes, we further employ a coupler circuit that enables tuning the coupling strength between two oscillators by applying an external flux. We demonstrate the functionality of our design through numerical simulations of a small example network with oscillators operating at 86 GHz and recognizing patterns within 10 ns. Our approach enables the learning and retrieval of dynamical memory patterns with a wide range of applications where rhythmic dynamic output is beneficial.

Cheng, Ran↗
DOE OSTI2016

NANDFlashSim: High-Fidelity, Microarchitecture-Aware NAND Flash Memory Simulation [NANDFlashSim: Intrinsic Latency Variation Aware NAND Flash Memory System Modeling and Simulation at Microarchitecture Level]

As the popularity of NAND flash expands in arenas from embedded systems to high-performance computing, a high-fidelity understanding of its specific properties becomes increasingly important. Further, with the increasing trend toward multiple-die, multiple-plane architectures and high-speed interfaces, flash memory systems are expected to continue to scale and cheapen, resulting in their broader proliferation. However, when designing NAND-based devices, making decisions about the optimal system configuration is nontrivial, because flash is sensitive to a number of parameters and suffers from inherent latency variations, and no available tools suffice for studying these nuances. The parameters include the architectures, such as multidie and multiplane, diverse node technologies, bit densities, and cell reliabilities. Therefore, we introduce NANDFlashSim, a high-fidelity, latency-variation-aware, and highly configurable NAND-flash simulator, which implements a detailed timing model for 16 state-of-the-art NAND operations. Using NANDFlashSim, we notably discover the following. First, regardless of the operation, reads fail to leverage internal parallelism. Second, MLC provides lower I/O bus contention than SLC, but contention becomes a serious problem as the number of dies increases. Third, many-die architectures outperform many-plane architectures for disk-friendly workloads. Lastly, employing a high-performance I/O bus or an increased page size does not enhance energy savings.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Indicator-directed Dynamic Power Management for Iterative Workloads on GPU-Accelerated Systems

Modern high-performance and warehouse computing centers show strong interest in minimizing system power consumption while satisfying customers’ quality of service (QoS). Dynamic voltage and frequency scaling (DVFS) is effective for achieving this goal. Nevertheless, automating the process online and making it transparent to users must address three major challenges: (1) Complexity — today’s hardware components (e.g., CPUs, GPUs, memory, network, etc.) can be configured in several or dozens of frequency/voltage states for satisfying divergent system demands. Given their combination and the emergence of heterogeneity, searching the optimal configuration in the design space online can be timing consuming. (2) QoS guarantee — user-defined objectives such as power constraint and performance target must be monitored, predicted and ensured at the best effort. (3) Adaptability — various known and unknown workloads run on systems. Workloads characteristics should be quickly determined and configurations dynamically adjusted in accord with workloads and QoS. In this work, we focus on applications exhibiting an interesting feature – iterative or periodic, which is common among conventional HPC and emerging machine learning workloads. We propose an online dynamic power-performance (ODPP) management framework to dynamically adjust GPU DVFS configurations to meet performance and power objectives and constraints, without any code annotation or intrusion. Particularly, ODPP extracts the performance and power indicators for applications from their resources utilization profiles in a short episode. It further automatically constructs an accurate model that infers from the indicators how the application's performance and power vary with GPU core and memory frequencies. Aided with the model, for both seen and unseen applications, ODPP can quickly determine the most appropriate DVFS configuration for their execution. We evaluate ODPP on an NVIDIA GPU using multiple exascale computing (ECP) and deep learning applications.

Zou, Pengfei↗
DOE OSTI2015

SU-E-T-500: Initial Implementation of GPU-Based Particle Swarm Optimization for 4D IMRT Planning in Lung SBRT

Purpose 4D-IMRT planning, combined with dynamic MLC tracking delivery, utilizes the temporal dimension as an additional degree of freedom to achieve improved OAR-sparing. The computational complexity for such optimization increases exponentially with increase in dimensionality. In order to accomplish this task in a clinically-feasible time frame, we present an initial implementation of GPU-based 4D-IMRT planning based on particle swarm optimization (PSO). Methods The target and normal structures were manually contoured on ten phases of a 4DCT scan of a NSCLC patient with a 54cm3 right-lower-lobe tumor (1.5cm motion). Corresponding ten 3D-IMRT plans were created in the Eclipse treatment planning system (Ver-13.6). A vendor-provided scripting interface was used to export 3D-dose matrices corresponding to each control point (10 phases × 9 beams × 166 control points = 14,940), which served as input to PSO. The optimization task was to iteratively adjust the weights of each control point and scale the corresponding dose matrices. In order to handle the large amount of data in GPU memory, dose matrices were sparsified and placed in contiguous memory blocks with the 14,940 weight-variables. PSO was implemented on CPU (dual-Xeon, 3.1GHz) and GPU (dual-K20 Tesla, 2496 cores, 3.52Tflops, each) platforms. NiftyReg, an open-source deformable image registration package, was used to calculate the summed dose. Results The 4D-PSO plan yielded PTV coverage comparable to the clinical ITV-based plan and significantly higher OAR-sparing, as follows: lung Dmean=33%; lung V20=27%; spinal cord Dmax=26%; esophagus Dmax=42%; heart Dmax=0%; heart Dmean=47%. The GPU-PSO processing time for 14940 variables and 7 PSO-particles was 41% that of CPU-PSO (199 vs. 488 minutes). Conclusion Truly 4D-IMRT planning can yield significant OAR dose-sparing while preserving PTV coverage. The corresponding optimization problem is large-scale, non-convex and computationally rigorous. Our initial results indicate that GPU-based PSO with further software optimization can make such planning clinically feasible. This work was supported through funding from the National Institutes of Health and Varian Medical Systems.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2020

Determining Multi-Component Phase Diagrams with Desired Characteristics Using Active Learning

Herein, we demonstrate how to predict and experimentally validate phase diagrams for multi-component systems from a high-dimensional virtual space of all possible phase diagrams involving several elements based on small existing experimental data. The experimental data for bulk phases for known systems represents a sampling from this space, and screening the space allows multi-component phase diagrams with given design criteria to be built. This approach uses machine learning methods to predict phase diagrams and Bayesian experimental design to minimize experiments for refinement and validation, all within an active learning loop. The approach is proven by predicting and synthesizing the ferroelectric ceramic system (1-ω)(Ba 0.61 Ca 0.28 Sr 0.11 TiO 3 )-ω(BaTi 0.888 Zr 0.0616 Sn 0.0028 Hf 0.0476 O 3 ) with a relatively high transition temperature and triple point, as well as the NiTi-based pseudo-binary phase diagram (1-ω)(Ti 0.309 Ni 0.485 Hf 0.20 Zr 0.006 )-ω(Ti 0.309 Ni 0.485 Hf 0.07 Zr 0.068 Nb 0.068 ) designed for high transition temperature (ω ≤ 1). Each phase diagram is validated and optimized through only three new experiments. The complexity of these compounds is beyond the reach of today’s computational methods.

36 MATERIALS SCIENCE↗