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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 523 records · Page 29
All sourcesNASA NTRSDOE OSTI
DOE OSTI2014

Lattice QCD with Domain Decomposition on Intel Xeon Phi Co-Processors

The gap between the cost of moving data and the cost of computing continues to grow, making it ever harder to design iterative solvers on extreme-scale architectures. This problem can be alleviated by alternative algorithms that reduce the amount of data movement. We investigate this in the context of Lattice Quantum Chromodynamics and implement such an alternative solver algorithm, based on domain decomposition, on Intel Xeon Phi co-processor (KNC) clusters. We demonstrate close-to-linear on-chip scaling to all 60 cores of the KNC. With a mix of single- and half-precision the domain-decomposition method sustains 400-500 Gflop/s per chip. Compared to an optimized KNC implementation of a standard solver [1], our full multi-node domain-decomposition solver strong-scales to more nodes and reduces the time-to-solution by a factor of 5.

Heybrock, Simon↗
DOE OSTI2013

Scaling the Ion Trap Quantum Processor

Trapped atomic ions are standards for quantum information processing, serving as quantum memories, hosts of quantum gates in quantum computers and simulators, and nodes of quantum communication networks. Quantum bits based on trapped ions enjoy a rare combination of attributes: They have exquisite coherence properties, they can be prepared and measured with nearly 100% efficiency, and they are readily entangled with each other through the Coulomb interaction or remote photonic interconnects. The outstanding challenge is the scaling of trapped ions to hundreds or thousands of qubits and beyond, at which scale quantum processors can outperform their classical counterparts in certain applications. We review the latest progress and prospects in that effort, with the promise of advanced architectures and new technologies, such as microfabricated ion traps and integrated photonics.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2014

QCD For Intel(R) Xeon Phi(tm) and Xeon(tm) processors

This library provides a library containing highly optimized Wilson-Dslash, Wilson Clover operator and Krylov subspace solvers for Lattice QCD simulations. The library is targeted at Intel(R) Xeon Phi(tm), and Intel(R) Xeon(tm) processors.

Joo, Balint↗
DOE OSTI2016

Processor Emulator with Benchmark Applications

A processor emulator and a suite of benchmark applications have been developed to assist in characterizing the performance of data-centric workloads on current and future computer architectures. Some of the applications have been collected from other open source projects. For more details on the emulator and an example of its usage, see reference [1].

Lloyd, G. Scott↗
DOE OSTI2018

Peptide Hit Results Processor

The Peptide Hit Results Processor (PHRP) can be used to convert an X!Tandem results file (XML format), MSGF+ .tsv search result file, Sequest Synopsis/First Hits file, or Inspect search result into a series of tab-delimited text files summarizing the results. It will insert modification symbols into the peptide sequences for modified peptides. Parallel files are created containing sequence information, modification details, and protein information. The user can optionally provide a modification definition file that specifies the symbol to use for each modification mass.

Gibbons, Bryson↗
DOE OSTI2017

Workbench Analysis Sequence Processor

The Workbench Analysis Sequence Processor (WASP) was developed to streamline lexing, parsing, access, validation, and analysis of ascii text files.

Lefebvre, RobertA.↗
DOE OSTI2022

High-dimensional discrete Fourier transform gates with a quantum frequency processor

The discrete Fourier transform (DFT) is of fundamental interest in photonic quantum information, yet the ability to scale it to high dimensions depends heavily on the physical encoding, with practical recipes lacking in emerging platforms such as frequency bins. In this article, we show that d -point frequency-bin DFTs can be realized with a fixed three-component quantum frequency processor (QFP), simply by adding to the electro-optic modulation signals one radio-frequency harmonic per each incremental increase in d . We verify gate fidelity F W > 0.9997 and success probability P W > 0.965 up to d = 10 in numerical simulations, and experimentally implement the solution for d = 3, utilizing measurements with parallel DFTs to quantify entanglement and perform tomography of multiple two-photon frequency-bin states. Our results furnish new opportunities for high-dimensional frequency-bin protocols in quantum communications and networking.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2016

Large-Scale Test of Dynamic Correlation Processors: Implications for Correlation-Based Seismic Pipelines

Correlation detectors are of considerable interest to the seismic monitoring communities because they offer reduced detection thresholds and combine detection, location and identification functions into a single operation. They appear to be ideal for applications requiring screening of frequent repeating events. However, questions remain about how broadly empirical correlation methods are applicable. We describe the effectiveness of banks of correlation detectors in a system that combines traditional power detectors with correlation detectors in terms of efficiency, which we define to be the fraction of events detected by the correlators. This paper elaborates and extends the concept of a dynamic correlation detection framework – a system which autonomously creates correlation detectors from event waveforms detected by power detectors; and reports observed performance on a network of arrays in terms of efficiency. We performed a large scale test of dynamic correlation processors on an 11 terabyte global dataset using 25 arrays in the single frequency band 1-3 Hz. The system found over 3.2 million unique signals and produced 459,747 screened detections. A very satisfying result is that, on average, efficiency grows with time and, after nearly 16 years of operation, exceeds 47% for events observed over all distance ranges and approaches 70% for near regional and 90% for local events. This observation suggests that future pipeline architectures should make extensive use of correlation detectors, principally for decluttering observations of local and near-regional events. Our results also suggest that future operations based on correlation detection will require commodity large-scale computing infrastructure, since the numbers of correlators in an autonomous system can grow into the hundreds of thousands.

47 OTHER INSTRUMENTATION↗
DOE OSTI2012

Ultrafast Power Processor for Smart Grid: Power Module Development

This project’s goal was to increase the switching speed and decrease the losses of the power semiconductor devices and power switch modules necessary to enable Smart Grid energy flow and control equipment such as the Ultra-Fast Power Processor. The primary focus of this project involves exploiting the new silicon-based Super-GTO (SGTO) technology and build on prototype modules already being developed. The prototype super gate-turn-off thyristor (SGTO) has been tested fully under continuously conducting and double-pulse hard-switching conditions for conduction and switching characteristics evaluation. The conduction voltage drop measurement results indicate that SGTO has excellent conduction characteristics despite inconsistency among some prototype devices. Tests were conducted with two conditions: (1) fixed gate voltage and varying anode current condition, and (2) fixed anode current and varying gate voltage condition. The conduction voltage drop is relatively a constant under different gate voltage condition. In terms of voltage drop as a function of the load current, there is a fixed voltage drop about 0.5V under zero current condition, and then the voltage drop is linearly increased with the current. For a 5-kV voltage blocking device that may operate under 2.5-kV condition, the projected voltage drop is less than 2.5 V under 50-A condition, or 0.1%. If the device is adopted in a converter operating under soft-switching condition, then the converter can achieve an ultrahigh efficiency, typically above 99%. The two-pulse switching test results indicate that SGTO switching speed is very fast. The switching loss is relatively low as compared to that of the insulated-gate-bipolar-transistors (IGBTs). A special phenomenon needs to be noted is such a fast switching speed for the high-voltage switching tends to create an unexpected Cdv/dt current, which reduces the turn-on loss because the dv/dt is negative and increases the turn-off loss because the dv/dt is positive. As a result, the turn-on loss at low current is quite low, and the turn-off loss at low current is relatively high. The phenomenon was verified with junction capacitance measurement along with the dv/dt calculation. Under 2-kV test condition, the turn-on and turn-off losses at 25-A is about 3 and 9 mJ, respectively. As compared to a 4.5-kV, 60-A rated IGBT, which has turn-on and turn-off losses about 25 and 20 mJ under similar test condition, the SGTO shows significant switching loss reduction. The switching loss depends on the switching frequency, but under hard-switching condition, the SGTO is favored to the IGBT device. The only concern is during low current turn-on condition, there is a voltage bump that can translate to significant power loss and associated heat. The reason for such a current bump is not known from this study. It is necessary that the device manufacturer perform though test and provide the answer so the user can properly apply SGTO in pulse-width-modulated (PWM) converter and inverter applications.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2017

Addressing Thermal and Performance Variability Issues in Dynamic Processors

As CMOS scaling nears its end, parameter variations (process, temperature and voltage) are becoming a major concern. To overcome parameter variations and provide stability, modern processors are becoming dynamic, opportunistically adjusting voltage and frequency based on thermal and energy constraints, which negatively impacts traditional bulk-synchronous parallelism-minded hardware and software designs. As node-level architecture is growing in complexity, implementing variation control mechanisms only with hardware can be a challenging task. In this paper we investigate a software strategy to manage hardwareinduced variations, leveraging low-level monitoring/controlling mechanisms.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Dosimetry Processor v1.0 User's Manual

The following discussion contains a detailed description of how to interface and operate Dosimetry Processor v1.0 software application. It describes the input required from the user to process dosimetry and actions to take for troubleshooting.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2018

Metrics and Benchmarks for Quantum Processors: State of Play

A compelling narrative has taken hold as quantum computing explodes into the commercial sector: Quantum computing in 2018 is like classical computing in 1965. In 1965 Gordon Moore wrote his famous paper about integrated circuits, saying: "At present, [minimum cost] is reached when 50 components are used per circuit. But... the complexity for minimum component costs has increased at a rate of roughly a factor of two per year... by 1975, the number of components per integrated circuit for minimum cost will be 65,000." This narrative is both appealing (we want to believe that quantum computing will follow the incredibly successful path of classical computing!) and plausible (2018 saw IBM, Intel, and Google announce 50-qubit integrated chips). But it is also deeply misleading. Here is an alternative: Quantum computing in 2018 is like classical computing in 1938. In 1938, John Atanasoff and Clifford Berry built the very first electronic digital computer. It had no program, and was not Turing-complete. Vacuum tubes — the standard "bit" for 20 years — were still 5 years in the future. ENIAC and the achievement of "computational supremacy" (over hand calculation) wouldn't arrive for 8 years, despite the accelerative effect of WWII. Integrated circuits and the information age were more than 20 years away. Neither of these analogies is perfect. Quantum computing technology is more like 1938, while the level of funding and excitement suggest 1965 (or later!). But the point of the cautionary analogy to 1938 is simple: Quantum computing in 2018 is a research field. It is far too early to establish metrics or benchmarks for performance. The best role for neutral organizations like IEEE is to encourage and shape research into metrics and benchmarks, so as to be ready when they become necessary. This white paper presents the evidence and reasoning for this claim. We explain what it means to say that quantum computing is a "research field", and why metrics and benchmarks for quantum processors also constitute a research field. We discuss the potential for harmful consequences of prematurely establishing standards or frameworks. We conclude by suggesting specific actions that IEEE or similar organizations can take to accelerate the development of good metrics and benchmarks for quantum computing.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Workbench Analysis Sequence Processor

The Workbench Analysis Sequence Processor (WASP) was developed to streamline lexing, parsing, access, validation, and analysis of ascii text files. The foundation of WASP resides on the parse tree data structure, where each node in the tree represents the syntax of the input document. Nodes can parent nodes with children. Nodes that have no children are known as terminal or leaf nodes , and they represent tokens (string, number, delimiter, etc.) in the text file. The fast lexical analyzer generator (flex - https://www.gnu.org/software/flex/) and GNU Bison parser generator (https://www.gnu.org/software/bison/) are extensively used for lexing and parsing.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Optimizing the Performance of Sparse-Matrix Vector Products on Next-Generation Processors

Matrix-vector products are ubiquitous in high-performance scientific applications and have a growing set of occurrences in advanced data analysis activities. Achieving high performance for these kernels is therefore paramount, in part, because these operations can consume vast amounts of application execution time. In this report we document the development of several sparse-matrix vector product kernel implementations using a variety of programming models and approaches. Each kernel is run on a broad set of matrices selected to demonstrate the wide variety of matrix structure and sparsity that is possible with a single, generic kernel. For benchmarking and performance analysis, we utilize leading computing architectures for the NNSA/ASC program including Intel's Knights Landing processor and IBM's POWER8.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Screening IMS Seismic Detections using Dynamic Correlation Processor: Progress report for 2020

LLNL completed the FY20 workplan entailing application of the Dynamic Correlation Processor (DCP) to International Monitoring System (IMS) primary seismic data in 2019 and 2020. The effective analysis period was curtailed to January 1 through November 12, 2019 due to a data compression change that rendered later data unusable. Fixing the data compression error is a priority for our data source, and we plan to extend the period of data analysis when the fix is implemented. We found that the percentage overlap between detections generated by the International Data Centre (IDC) DFX software and detections generated by DCP varied widely by station. Overlap is 30-40% at some stations, suggesting that a large percentage of DFX detections could be screened (removed) from the detection-event association algorithm. However, detection overlap was much lower, a few percent, at many stations and the percentage overlap was low at stations known to have many mines and other local sources of seismicity. Unexpectedly low detection overlap at many stations prompted us to examine results for the ARCES station in detail. There is considerable mine activity near ARCES, but our initial FY20 analysis found only ~2% DCP/DFX detection overlap. Differences in the pre-processing (e.g. beam recipes) used by DCP and DFX appear to be the cause of low detection overlap at ARCES. DCP uses wideband filters to improve detector robustness and the IDC uses narrow-band pre-filtering to improve sensitivity. After reprocessing ARCES using the IDC beam recipe, DCP/DFX overlap increased to ~74%. This result shows that we must reprocess the IMS network using the IDC station-specific beam recipes if we are to effectively screen DFX detections and improve automatic event building performance at the IDC.

58 GEOSCIENCES↗
DOE OSTI2020

A VXS [VITA41] Trigger Processor for the 12GEV Experimental Programs at Jefferson Lab

The VXS_Trigger_Processor [VTP] was developed and commissioned for CLAS12 in the fall of 2016. This board is a VITA41 switch card and it collects data from a variety of front-end TDC and Flash ADC modules. The VTP has since been used in several experiments at Jefferson Lab serving as the L1 trigger module for a variety of detector types, such as stacked calorimeters, strip calorimeters, time-of-flight, Cerenkov, hodoscopes, drift chambers, and silicon strips. Trigger algorithms implemented include cluster finding (1D, 2D), drift chamber segment and road finding, geometry matching between various detectors, particle counting, and general global trigger bit processing. The VTP is also capable of reading out each front-end crate with up to 40Gbps Ethernet which is an enormous increase compared to the currently used 200MB/s VME bus. Recent progress has been made to show that a firmware and software upgrade can enable existing Jefferson Lab front-end crates to operate in a streaming DAQ mode. In February 2020, tests will be performed on a full calorimeter and matched hodoscope which are components of the CLAS12 Forward Tagger detector system with beam in Hall B. This paper details the hardware performance, triggered, and streaming applications that have been implemented using the VTP for several experiments at Jefferson Lab.

ABBOTT, David↗