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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 523 records · Page 29
All sourcesNASA NTRSDOE OSTI
NASA NTRS1973

Integrated circuit package with lead structure and method of preparing the same

A beam-lead integrated circuit package assembly including a beam-lead integrated circuit chip, a lead frame array bonded to projecting fingers of the chip, a rubber potting compound disposed around the chip, and an encapsulating molded plastic is described. The lead frame array is prepared by photographically printing a lead pattern on a base metal sheet, selectively etching to remove metal between leads, and plating with gold. Joining of the chip to the lead frame array is carried out by thermocompression bonding of mating goldplated surfaces. A small amount of silicone rubber is then applied to cover the chip and bonded joints, and the package is encapsulated with epoxy resin, applied by molding.

Kennedy, B. W.↗
NASA NTRS1974

Basic memory module

Construction and electrical characterization of the 4096 x 2-bit Basic Memory Module (BMM) are reported for the Space Ultrareliable Modular Computer (SUMC) program. The module uses four 2K x 1-bit N-channel FET, random access memory chips, called array chips, and two sense amplifier chips, mounted and interconnected on a ceramic substrate. Four 5% tolerance power supplies are required. At the Module, the address, chip select, and array select lines require a 0-8.5 V MOS signal level. The data output, read-strobe, and write-enable lines operate at TTl levels. Although the module is organized as 4096 x 2 bits, it can be used in a 8196 x 1-bit application with appropriate external connections. A 4096 x 1-bit organization can be obtained by depopulating chips.

Tietze, F. C.↗
NASA NTRS1983

Design considerations for FET-gated power transistors

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Chen, D. Y.↗
NASA NTRS1989

Monolithic Microwave Switching Matrix

Gallium arsenide integrated-circuit chip switches any of three microwave input signals to any of three output ports. Measuring 4.9 mm on side, chip contains nine field-effect transistor (FET) crosspoint switches. Housed in custom-designed package with standard connectors for easy integration into system. FET's on chip operated as passive switches and consume no static power and insignificant amounts of switching power. Chip module cascades with similar modules into large arrays handling as many as 100 inputs and 100 outputs. Applications include switching and routing vast amounts of data between computers at extremely high speed. On communications satellite, chip switches microwave signals to and from Earth stations and other satellites.

Fujikawa, Gene↗
NASA NTRS1990

Universal nondestructive mm-wave integrated circuit test fixture

Monolithic microwave integrated circuit (MMIC) test includes a bias module having spring-loaded contacts which electrically engage pads on a chip carrier disposed in a recess of a base member. RF energy is applied to and passed from the chip carrier by chamfered edges of ridges in the waveguide passages of housings which are removably attached to the base member. Thru, Delay, and Short calibration standards having dimensions identical to those of the chip carrier assure accuracy and reliability of the test. The MMIC chip fits in an opening in the chip carrier with the boundaries of the MMIC lying on movable reference planes thereby establishing accuracy and flexibility.

Romanofsky, Robert R.↗
NASA NTRS1992

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Shalkhauser, K. A.↗
NASA NTRS1992

Ultra-dense magnetoresistive mass memory

This report details the progress and accomplishments of Nonvolatile Electronics (NVE), Inc., on the design of the wafer scale MRAM mass memory system during the fifth quarter of the project. NVE has made significant progress this quarter on the one megabit design in several different areas. A test chip, which will verify a working GMR bit with the dimensions required by the 1 Meg chip, has been designed, laid out, and is currently being processed in the NVE labs. This test chip will allow electrical specifications, tolerances, and processing issues to be finalized before construction of the actual chip, thus providing a greater assurance of success of the final 1 Meg design. A model has been developed to accurately simulate the parasitic effects of unselected sense lines. This model gives NVE the ability to perform accurate simulations of the array electronic and test different design concepts. Much of the circuit design for the 1 Meg chip has been completed and simulated and these designs are included. Progress has been made in the wafer scale design area to verify the reliable operation of the 16 K macrocell. This is currently being accomplished with the design and construction of two stand alone test systems which will perform life tests and gather data on reliabiliy and wearout mechanisms for analysis.

Daughton, J. M.↗
NASA NTRS1993

A three channel telemetry system

A three channel telemetry system intended for biomedical applications is described. The transmitter is implemented in a single chip using a 2 micron BiCMOS processes. The operation of the system and the test results from the latest chip are discussed. One channel is always dedicated to temperature measurement while the other two channels are generic. The generic channels carry information from transducers that are interfaced to the system through on-chip general purpose operational amplifiers. The generic channels have different bandwidths: one from dc to 250 Hz and the other from dc to 1300 Hz. Each generic channel modulates a current controlled oscillator to produce a frequency modulated signal. The two frequency modulated signals are summed and used to amplitude modulate the temperature signal which acts as a carrier. A near-field inductive link telemeters the combined signals over a short distance. The chip operates on a supply voltage anywhere from 2.5 to 3.6 Volts and draws less than 1 mA when transmitting a signal. The chip can be incorporated into ingestible, implantable and other configurations. The device can free the patient from tethered data collection systems and reduces the possibility of infection from subcutaneous leads. Data telemetry can increase patient comfort leading to a greater acceptance of monitoring.

Lesho, Jeffery C.↗
NASA NTRS1993

Radiation hardened microprocessor for small payloads

The RH-3000 program is developing a rad-hard space qualified 32-bit MIPS R-3000 RISC processor under the Naval Research Lab sponsorship. In addition, under IR&D Harris is developing RHC-3000 for embedded control applications where low cost and radiation tolerance are primary concerns. The development program leverages heavily from commercial development of the MIPS R-3000. The commercial R-3000 has a large installed user base and several foundry partners are currently producing a wide variety of R-3000 derivative products. One of the MIPS derivative products, the LR33000 from LSI Logic, was used as the basis for the design of the RH-3000 chipset. The RH-3000 chipset consists of three core chips and two support chips. The core chips include the CPU, which is the R-3000 integer unit and the FPA/MD chip pair, which performs the R-3010 floating point functions. The two support whips contain all the support functions required for fault tolerance support, real-time support, memory management, timers, and other functions. The Harris development effort had first passed silicon success in June, 1992 with the first rad-hard 32-bit RH-3000 CPU chip. The CPU device is 30 kgates, has a 508 mil by 503 mil die size and is fabricated at Harris Semiconductor on the rad-hard CMOS Silicon on Sapphire (SOS) process. The CPU device successfully passed tesing against 600,000 test vectors derived directly on the LSI/MIPS test suite and has been operational as a single board computer running C code for the past year. In addition, the RH-3000 program has developed the methodology for converting commercially developed designs utilizing logic synthesis techniques based on a combination of VHDK and schematic data bases.

Shah, Ravi↗
NASA NTRS1993

Mixed voltage VLSI design

A technique for minimizing the power dissipated in a Very Large Scale Integration (VLSI) chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits. Since the overall throughput of a VLSI chip depends on the speed of the critical path(s) in the chip, it may be possible to sustain the throughput rates attained at higher voltages by operating the circuits in the critical path(s) with a high voltage while operating the other circuits with a lower voltage to minimize the power dissipation. The interface between the gates which operate at different voltages is crucial for low power dissipation since the interface may possibly have high static current dissipation thus negating the gains of the low voltage operation. The design of a voltage level translator which does the interface between the low voltage and high voltage circuits without any significant static dissipation is presented. Then, the results of the mixed voltage design using a greedy algorithm on three chips for various operating voltages are presented.

Panwar, Ramesh↗
NASA NTRS1984

NSC 800, 8-bit CMOS microprocessor

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Suszko, S. F.↗
NASA NTRS2006

Using Existing NASA Satellites as Orbiting Testbeds to Accelerate Technology Infusion into Future Missions

One of the shared problems for new space mission developers is that it is extremely difficult to infuse new technology into new missions unless that technology has been flight validated. Therefore, the issue is that new technology is required to fly on a successful mission for flight validation. We have been experimenting with new technology on existing satellites by retrofitting primarily the flight software while the missions are on-orbit to experiment with new operations concepts. Experiments have been using Earth Observing 1 (EO-1), which is part of the New Millennium Program at NASA. EO-1 finished its prime mission one year after its launch on November 21,2000. From November 21,2001 until the present, EO-1 has been used in parallel with additional science data gathering to test out various sensor web concepts. Similarly, the Cosmic Hot Interstellar Plasma Spectrometer (CHIPS) satellite was also a one year mission flown by the University of Berkeley, sponsored by NASA and whose prime mission ended August 30,2005. Presently, CHIPS is being used to experiment with a seamless space to ground interface by installing Core Flight System (cFS), a "plug-and-play" architecture developed by the Flight Software Branch at NASA/GSFC on top of the existing space-to-ground Internet Protocol (IP) interface that CHIPS implemented. For example, one targeted experiment is to connect CHIPS to a rover via this interface and the Internet, and trigger autonomous actions on CHIPS, the rover or both. Thus far, having satellites to experiment with new concepts has turned out to be an inexpensive way to infuse new technology for future missions. Relevant experiences thus far and future plans will be discussed in this presentation.

Mandl, Daniel↗
NASA NTRS2009

Microfluidic Mixing Technology for a Universal Health Sensor

A highly efficient means of microfluidic mixing has been created for use with the rHEALTH sensor an elliptical mixer and passive curvilinear mixing patterns. The rHEALTH sensor provides rapid, handheld, complete blood count, cell differential counts, electrolyte measurements, and other lab tests based on a reusable, flow-based microfluidic platform. These geometries allow for cleaning in a reusable manner, and also allow for complete mixing of fluid streams. The microfluidic mixing is performed by flowing two streams of fluid into an elliptical or curvilinear design that allows the combination of the flows into one channel. The mixing is accomplished by either chaotic advection around micro - fluidic loops. All components of the microfluidic chip are flow-through, meaning that cleaning solution can be introduced into the chip to flush out cells, plasma proteins, and dye. Tests were performed on multiple chip geometries to show that cleaning is efficient in any flowthrough design. The conclusion from these experiments is that the chip can indeed be flushed out with microliter volumes of solution and biological samples are cleaned readily from the chip with minimal effort. The technology can be applied in real-time health monitoring at patient s bedside or in a doctor s office, and real-time clinical intervention in acute situations. It also can be used for daily measurement of hematocrit for patients on anticoagulant drugs, or to detect acute myocardial damage outside a hospital.

Chan, Eugene Y.↗
NASA NTRS2007

Power-Amplifier Module for 145 to 165 GHz

A power-amplifier module that operates in the frequency range of 145 to 165 GHz has been designed and constructed as a combination of (1) a previously developed monolithic microwave integrated circuit (MMIC) power amplifier and (2) a waveguide module. The amplifier chip was needed for driving a high-electron-mobility-transistor (HEMT) frequency doubler. While it was feasible to connect the amplifier and frequency-doubler chips by use of wire bonds, it was found to be much more convenient to test the amplifier and doubler chips separately. To facilitate separate testing, it was decided to package the amplifier and doubler chips in separate waveguide modules. Figure 1 shows the resulting amplifier module. The amplifier chip was described in "MMIC HEMT Power Amplifier for 140 to 170 GHz" (NPO-30127), NASA Tech Briefs, Vol. 27, No. 11, (November 2003), page 49. To recapitulate: This is a three-stage MMIC power amplifier that utilizes HEMTs as gain elements. The amplifier was originally designed to operate in the frequency range of 140 to 170 GHz. The waveguide module is based on a previously developed lower frequency module, redesigned to support operation in the frequency range of 140 to 220 GHz. Figure 2 presents results of one of several tests of the amplifier module - measurements of output power and gain as functions of input power at an output frequency of 150 GHz. Such an amplifier module has many applications to test equipment for power sources above 100 GHz.

Samoska, Lorene↗
NASA NTRS2010

Piezo activated mode tracking system for widely tunable mode-hop-free external cavity mid-IR semiconductor lasers

A widely tunable, mode-hop-free semiconductor laser operating in the mid-IR comprises a QCL laser chip having an effective QCL cavity length, a diffraction grating defining a grating angle and an external cavity length with respect to said chip, and means for controlling the QCL cavity length, the external cavity length, and the grating angle. The laser of claim 1 wherein said chip may be tuned over a range of frequencies even in the absence of an anti-reflective coating. The diffraction grating is controllably pivotable and translatable relative to said chip and the effective QCL cavity length can be adjusted by varying the injection current to the chip. The laser can be used for high resolution spectroscopic applications and multi species trace-gas detection. Mode-hopping is avoided by controlling the effective QCL cavity length, the external cavity length, and the grating angle so as to replicate a virtual pivot point.

Wysocki, Gerard↗
NASA NTRS2011

Surface acoustic wave coding for orthogonal frequency coded devices

Methods and systems for coding SAW OFC devices to mitigate code collisions in a wireless multi-tag system. Each device producing plural stepped frequencies as an OFC signal with a chip offset delay to increase code diversity. A method for assigning a different OCF to each device includes using a matrix based on the number of OFCs needed and the number chips per code, populating each matrix cell with OFC chip, and assigning the codes from the matrix to the devices. The asynchronous passive multi-tag system includes plural surface acoustic wave devices each producing a different OFC signal having the same number of chips and including a chip offset time delay, an algorithm for assigning OFCs to each device, and a transceiver to transmit an interrogation signal and receive OFC signals in response with minimal code collisions during transmission.

Malocha, Donald↗
NASA NTRS2012

Demonstration of the Wide-Field Imaging Interferometer Testbed Using a Calibrated Hyperspectral Image Projector

The Wide-field Imaging Interferometer testbed (WIIT) at NASA's Goddard Space Flight Center uses a dual-Michelson interferometric technique. The WIIT combines stellar interferometry with Fourier-transform interferometry to produce high-resolution spatial-spectral data over a large field-of-view. This combined technique could be employed on future NASA missions such as the Space Infrared Interferometric Telescope (SPIRIT) and the Sub-millimeter Probe of the Evolution of Cosmic Structure (SPECS). While both SPIRIT and SPECS would operate at far-infrared wavelengths, the WIIT demonstrates the dual-interferometry technique at visible wavelengths. The WIIT will produce hyperspectral image data, so a true hyperspectral object is necessary. A calibrated hyperspectral image projector (CHIP) has been constructed to provide such an object. The CHIP uses Digital Light Processing (DLP) technology to produce customized, spectrally-diverse scenes. CHIP scenes will have approximately 1.6-micron spatial resolution and the capability of . producing arbitrary spectra in the band between 380 nm and 1.6 microns, with approximately 5-nm spectral resolution. Each pixel in the scene can take on a unique spectrum. Spectral calibration is achieved with an onboard fiber-coupled spectrometer. In this paper we describe the operation of the CHIP. Results from the WIIT observations of CHIP scenes will also be presented.

Bolcar, Matthew R.↗
NASA NTRS2018

Challenges and Opportunities in Gen3 Embedded Cooling with High-Quality Microgap Flow

Gen3, Embedded Cooling, promises to revolutionize thermal management of advanced microelectronic systems by eliminating the sequential conductive and interfacial thermal resistances which dominate the present 'remote cooling' paradigm. Single-phase interchip microfluidic flow with high thermal conductivity chips and substrates has been used successfully to cool single transistors dissipating more than 40kW/sq cm, but efficient heat removal from transistor arrays, larger chips, and chip stacks operating at these prodigious heat fluxes would require the use of high vapor fraction (quality), two-phase cooling in intra- and inter-chip microgap channels. The motivation, as well as the challenges and opportunities associated with evaporative embedded cooling in realistic form factors, is the focus of this paper. The paper will begin with a brief review of the history of thermal packaging, reflecting the 70-year 'inward migration' of cooling technology from the computer-room, to the rack, and then to the single chip and multichip module with 'remote' or attached air- and liquid-cooled coldplates. Discussion of the limitations of this approach and recent results from single-phase embedded cooling will follow. This will set the stage for discussion of the development challenges associated with application of this Gen3 thermal management paradigm to commercial semiconductor hardware, including dealing with the effects of channel length, orientation, and manifold-driven centrifugal acceleration on the governing behavior.

microchannel↗