Search NASA⌕ Search

SEARCH · Search NASA

Results for “error correction”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 523 records · Page 29
All sourcesNASA NTRSDOE OSTI
NASA NTRS1984

ACTS TDMA network control

This paper presents basic network control concepts for the Advanced Communications Technology Satellite (ACTS) System. Two experimental systems, called the low-burst-rate and high-burst-rate systems, along with ACTS ground system features, are described. The network control issues addressed include frame structures, acquisition and synchronization procedures, coordinated station burst-time plan and satellite-time plan changes, on-board clock control based on ground drift measurements, rain fade control by means of adaptive forward-error-correction (FEC) coding and transmit power augmentation, and reassignment of channel capacities on demand. The NASA ground system, which includes a primary station, diversity station, and master control station, is also described.

Inukai, T.↗
NASA NTRS1986

Fast Reed-Solomon Decoder

High-speed decoder intended for use with Reed-Solomon (RS) codes of long code length and high error-correcting capability. Design based on algorithm that includes high-radix Fermat transform procedure, which is most efficient for high speeds. RS code in question has code-word length of 256 symbols, of which 224 are information symbols and 32 are redundant.

Liu, K. Y.↗
NASA NTRS1986

Systolic VLSI Reed-Solomon Decoder

Decoder for digital communications provides high-speed, pipelined ReedSolomon (RS) error-correction decoding of data streams. Principal new feature of proposed decoder is modification of Euclid greatest-common-divisor algorithm to avoid need for time-consuming computations of inverse of certain Galois-field quantities. Decoder architecture suitable for implementation on very-large-scale integrated (VLSI) chips with negative-channel metaloxide/silicon circuitry.

Shao, H. M.↗
NASA NTRS1986

Fast VLSI Viterbi Decoder

Fast Viterbi decoder with fully parallel, pipeline architecture implemented on two VLSI NMOS chips. Decoder used with constraint-length-7, rate-1/2, convolutional error-correcting code widely used by NASA for deepspace telemetry data. With this (7,1/2) code, bit stream contains 2 bits per original data bit, and information about 1 data bit distributed over 7 pairs of bits. Design principles of decoder also applicable to Viterbi codes of other lengths and rates.

Wang, C. C.↗
NASA NTRS1986

Coding for Efficient Image Transmission

NASA publication second in series on data-coding techniques for noiseless channels. Techniques used even in noisy channels, provided data further processed with Reed-Solomon or other error-correcting code. Techniques discussed in context of transmission of monochrome imagery from Voyager II spacecraft but applicable to other streams of data. Objective of this type coding to "compress" data; that is, to transmit using as few bits as possible by omitting as much as possible of portion of information repeated in subsequent samples (or picture elements).

Rice, R. F.↗
NASA NTRS1986

Multiplier Architecture for Coding Circuits

Multipliers based on new algorithm for Galois-field (GF) arithmetic regular and expandable. Pipeline structures used for computing both multiplications and inverses. Designs suitable for implementation in very-large-scale integrated (VLSI) circuits. This general type of inverter and multiplier architecture especially useful in performing finite-field arithmetic of Reed-Solomon error-correcting codes and of some cryptographic algorithms.

Wang, C. C.↗
NASA NTRS1984

MIDAS - A microcomputer-based image display and analysis system with full Landsat frame processing capabilities

Image Display and Analysis Systems (MIDAS) developed at NASA/Ames for the analysis of Landsat MSS images is described. The MIDAS computer power and memory, graphics, resource-sharing, expansion and upgrade, environment and maintenance, and software/user-interface requirements are outlined; the implementation hardware (including 32-bit microprocessor, 512K error-correcting RAM, 70 or 140-Mbyte formatted disk drive, 512 x 512 x 24 color frame buffer, and local-area-network transceiver) and applications software (ELAS, CIE, and P-EDITOR) are characterized; and implementation problems, performance data, and costs are examined. Planned improvements in MIDAS hardware and design goals and areas of exploration for MIDAS software are discussed.

Hofman, L. B.↗
NASA NTRS1986

Synchronization of Data Recorded on Different Recorders

Electrical and mechanical timing errors corrected. Electronic timing system enables time correlation of analog and digital signals recorded on different magnetic tapes or on different tracks of same tape. Recorded simultaneously on different magnetic-tape tracks along with data signals to enable subsequent time correlation of data. Concept improves analysis of Space Shuttle flight-data tapes containing signals with frequency components up to 50 Hz, used for higher frequencies, in kilohertz region. Useful in other applications requiring synchronization of data on different data tracks.

Wise, J. H.↗
NASA NTRS1986

VLSI Architectures for Computing DFT's

Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

Truong, T. K.↗
NASA NTRS1985

CARE 3, Version 4 enhancements

The enhancements and error corrections to CARE III Version 4 are listed. All changes to Version 4 with the exception of the internal redundancy model were implemented in Version 5. Version 4 is the first public release version for execution on the CDC Cyber 170 series computers. Version 5 is the second release version and it is written in ANSI standard FORTRAN 77 for execution on the DEC VAX 11/700 series computers and many others.

Bryant, L. A.↗
NASA NTRS1986

Error control techniques for satellite and space communications

The performance of NASA Telecommand System was analyzed. A random coding approach was taken to determine the optimum code rate to use in forward error correcting (FEC) system with a fixed signal energy to noise power density ration, but no bandwidth constraint. Capacity and cutoff rates of concatened coding systems were determined. A lower bound on the minium distance growth rate between unmerged codewords was obtained for time invarient convolutional codes.

Costello, D. J., Jr.↗
NASA NTRS1985

Contributions to workload of rotational optical transformations

An investigation of visuomotor adaptation to optical rotation and optical inversion was conducted. Experiment 1 examined the visuomotor adaptability of subjects to an optically rotating visual world with a univariate repeated measures design. Experiment 1A tested one major prediction of a model of adaptation put forth by Welch who predicted that the aversive drive state that triggers adaptation would be habituated to fairly rapidly. Experiment 2 was conducted to investigate the role of motor activity in adaptation to optical rotation. Specifically, this experiment contrasted the reafference hypothesis and the proprioceptive change hypothesis. Experiment 3 examined the role of cognition, error-corrective feedback, and proprioceptive and/or reafferent feedback in visuomotor adaptation to optical inversion. Implications for research and implications for practice were suggested for all experiments.

Atkinson, R. P.↗
NASA NTRS1986

On the effectiveness of onboard processing

The effectiveness of onboard processing in communications satellites is discussed, and the interrelationships between the various elements of onboard processing are described. An overview is given of NASA's Advanced Communications Technology Satellite (ACTS), emphasizing its baseboard processor. The onboard processing features of ACTS are described, including frequency reuse, signal regeneration, TDMA/FDMA demand assigned multiple access, forward error correction, routing, and dynamic reconfiguration. The terminals of the ACTS ground segment are described, and comparisons are made between satellite onboard processing and other technologies.

Moy, L. L.↗
NASA NTRS1987

Maximum-Likelihood Decoder on a Hypercube Multiprocessor

Efficient parallel processing used to implement complex decoders. Hypercube multiprocessor connection scheme practical to decode long convolutional codes with efficient use of hardware. Hypercube design reduces both communication time among processors and space needed for interconnection. Decoding concept applicable to concurrent processing of digital signals using convolutional codes for error correction.

Pollara, F.↗
NASA NTRS1987

Theory of Periodic-Binary-Sequence Generators

Algorithms yield feedback shift registers with maximum regularity. Report provides extensive mathematical treatment of new and previous results related to generation of pseudo-noise binary sequences by feedback shift registers. Generator architectures amenable to efficient implementation in very-large-scale integrated (VLSI) circuits. Report includes literature references to applications of such sequences in random-number generation, radar, VLSI testing, data encryption and decryption, algebraic error-detection and error-correction encoding and decoding, and feedback-shift-register synthesis of sequential machines.

Perlman, M.↗
NASA NTRS1987

Trellis-Coded Modulation for Fading Channels

In proposed communication system, digital signals transmitted efficiently over fading channel by combination of trellis coding and multiple-phase-shift keying with addition of asymmetry to signal set. Coding and modulation schemes not designed separately as in previous systems but integrated to yield bandwidth-efficient modulation and forward-error-correction coding. Helps to satisfy need for reliable high-quality transmission of voice and data between land-mobile units via satellites, where limitations of power and bandwidth imposed simultaneously. Also applicable to ionospheric communications between fixed or mobile units.

Simon, Marvin K.↗
NASA NTRS1986

A generalized algorithm to design finite field normal basis multipliers

Finite field arithmetic logic is central in the implementation of some error-correcting coders and some cryptographic devices. There is a need for good multiplication algorithms which can be easily realized. Massey and Omura recently developed a new multiplication algorithm for finite fields based on a normal basis representation. Using the normal basis representation, the design of the finite field multiplier is simple and regular. The fundamental design of the Massey-Omura multiplier is based on a design of a product function. In this article, a generalized algorithm to locate a normal basis in a field is first presented. Using this normal basis, an algorithm to construct the product function is then developed. This design does not depend on particular characteristics of the generator polynomial of the field.

Wang, C. C.↗
NASA NTRS1986

Local network interconnection through a satellite point-to-multipoint link

Four architectures to implement a point to multipoint satellite link protocol for communication services offered by the Telecom 1 satellite network are presented. A safe communication service with error correction and flow control facilities is described. It is shown that a time transparent communication system combines simplicity and cost advantages.

Duarte, O. Muniz Bandeira↗