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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 523 records · Page 29

Frequency domain laser velocimeter signal processor

A laser velocimeter frequency domain signal processor is described which utilizes smart instrumentation to configure itself to maximize measurement accuracy based on the determined characteristics of the input signals. The stystem provides the same measurement capabilities as the high-speed burst counter in instantaneous measurements of signal frequency, the same automatic gain control and automatic frequency control as the frequency tracker, and the same immunity to signal-to-noise derived errors as the photon correlator. Simulation results demonstrate measurement accuracies of better than 0.2 percent for signal frequencies up to 100 MHz.

Meyers, J. F.↗

Parallel Analog-to-Digital Image Processor

Proposed integrated-circuit network of many identical units convert analog outputs of imaging arrays of x-ray or infrared detectors to digital outputs. Converter located near imaging detectors, within cryogenic detector package. Because converter output digital, lends itself well to multiplexing and to postprocessing for correction of gain and offset errors peculiar to each picture element and its sampling and conversion circuits. Analog-to-digital image processor is massively parallel system for processing data from array of photodetectors. System built as compact integrated circuit located near local plane. Buffer amplifier for each picture element has different offset.

Lokerson, D. C.↗

Central Processor Acts as High-Speed DMA Controller

Computer-system architecture enables system host central processor (CP) to make high-speed, direct-memory-access (DMA) data transfers without cost and complexity of adding dedicated DMA controller. New system, CCP used as DMA controller, obviating need for dedicated DMA controller; yet maximum transfer rates equivalent to those obtained with dedicated DMA controller. Useful wherever dedicated DMA controller desired because of required data-transfer rates.

Blaha, Matthew S.↗

Numerical algorithms for finite element computations on concurrent processors

The work of several graduate students which relate to the NASA grant is briefly summarized. One student has worked on a detailed analysis of the so-called ijk forms of Gaussian elemination and Cholesky factorization on concurrent processors. Another student has worked on the vectorization of the incomplete Cholesky conjugate method on the CYBER 205. Two more students implemented various versions of Gaussian elimination and Cholesky factorization on the FLEX/32.

Ortega, J. M.↗

Roundoff noise analysis for digital Doppler processors in radar scatterometers

The noise due to finite word length effects for digital Doppler processors (DPP) in radar scatterometers, is analyzed. The roundoff noise-to-signal ratio in the measurement of the radar return signal power is derived. Computer simulations which validate the analytical results are presented. The results can be used in tradeoff studies of hardware design such as number of bits required at each processing stage. The results are used in the design of a DPP for the NASA scatterometer planned to be launched in 1990.

Chi, Chong-Yung↗

A dual-processor multi-frequency implementation of the FINDS algorithm

This report presents a parallel processing implementation of the FINDS (Fault Inferring Nonlinear Detection System) algorithm on a dual processor configured target flight computer. First, a filter initialization scheme is presented which allows the no-fail filter (NFF) states to be initialized using the first iteration of the flight data. A modified failure isolation strategy, compatible with the new failure detection strategy reported earlier, is discussed and the performance of the new FDI algorithm is analyzed using flight recorded data from the NASA ATOPS B-737 aircraft in a Microwave Landing System (MLS) environment. The results show that low level MLS, IMU, and IAS sensor failures are detected and isolated instantaneously, while accelerometer and rate gyro failures continue to take comparatively longer to detect and isolate. The parallel implementation is accomplished by partitioning the FINDS algorithm into two parts: one based on the translational dynamics and the other based on the rotational kinematics. Finally, a multi-rate implementation of the algorithm is presented yielding significantly low execution times with acceptable estimation and FDI performance.

Godiwala, Pankaj M.↗

Analysis of the Continuous Stellar Tracking Attitude Reference (CSTAR) attitude rate processor

The Continuous Stellar Tracking Attitude Reference (CSTAR) system is an in-house project for Space Station to provide high accuracy, drift free attitude and angular rate information for the GN&C system. The outputs of the solid state star trackers are processed to provide attitude information; rate data is then derived from the attitude. Rate derivation is based on discrete time polynomial approximation techniques. This gives simple algorithms which allow for interpolation by other users. Attitude rate is modeled as a constant with low amplitude, low frequency sinusoids superimposed. The rate processor is parameterized to account for the effects of random errors, sample rate, data processing rate and perturbation frequency. The baseline system may be characterized as follows: the three sigma attitude accuracy is 0.01 degrees, the three sigma rate accuracy is 0.0001 degrees per second, the sample rate is 100 Hertz, the sampled signal is bandlimited to 0.5 Hertz, and the data processing rate is 10 Hertz. The above system requires a differentiator of length 127. This will track rate perturbations of frequencies less than 0.01 Hertz with low systematic errors.

Uhde-Lacovara, J.↗

Block iterative restoration of astronomical images with the massively parallel processor

A method is described for algebraic image restoration capable of treating astronomical images. For a typical 500 x 500 image, direct algebraic restoration would require the solution of a 250,000 x 250,000 linear system. The block iterative approach is used to reduce the problem to solving 4900 121 x 121 linear systems. The algorithm was implemented on the Goddard Massively Parallel Processor, which can solve a 121 x 121 system in approximately 0.06 seconds. Examples are shown of the results for various astronomical images.

Heap, Sara R.↗

Contextual classification on the massively parallel processor

Classifiers are often used to produce land cover maps from multispectral Earth observation imagery. Conventionally, these classifiers have been designed to exploit the spectral information contained in the imagery. Very few classifiers exploit the spatial information content of the imagery, and the few that do rarely exploit spatial information content in conjunction with spectral and/or temporal information. A contextual classifier that exploits spatial and spectral information in combination through a general statistical approach was studied. Early test results obtained from an implementation of the classifier on a VAX-11/780 minicomputer were encouraging, but they are of limited meaning because they were produced from small data sets. An implementation of the contextual classifier is presented on the Massively Parallel Processor (MPP) at Goddard that for the first time makes feasible the testing of the classifier on large data sets.

Tilton, James C.↗

Animated computer graphics models of space and earth sciences data generated via the massively parallel processor

The capability was developed of rapidly producing visual representations of large, complex, multi-dimensional space and earth sciences data sets via the implementation of computer graphics modeling techniques on the Massively Parallel Processor (MPP) by employing techniques recently developed for typically non-scientific applications. Such capabilities can provide a new and valuable tool for the understanding of complex scientific data, and a new application of parallel computing via the MPP. A prototype system with such capabilities was developed and integrated into the National Space Science Data Center's (NSSDC) Pilot Climate Data System (PCDS) data-independent environment for computer graphics data display to provide easy access to users. While developing these capabilities, several problems had to be solved independently of the actual use of the MPP, all of which are outlined.

Treinish, Lloyd A.↗

Frequency domain laser velocimeter signal processor: A new signal processing scheme

A new scheme for processing signals from laser velocimeter systems is described. The technique utilizes the capabilities of advanced digital electronics to yield a smart instrument that is able to configure itself, based on the characteristics of the input signals, for optimum measurement accuracy. The signal processor is composed of a high-speed 2-bit transient recorder for signal capture and a combination of adaptive digital filters with energy and/or zero crossing detection signal processing. The system is designed to accept signals with frequencies up to 100 MHz with standard deviations up to 20 percent of the average signal frequency. Results from comparative simulation studies indicate measurement accuracies 2.5 times better than with a high-speed burst counter, from signals with as few as 150 photons per burst.

Meyers, James F.↗

Massively parallel processor

A brief description is given of the Massively Parallel Processor (MPP). Major applications of the MPP are in the area of image processing (where the operands are often very small integers) from very high spatial resolution passive image sensors, signal processing of radar data, and numerical modeling simulations of climate. The system can be programmed in assembly language or a high level language. Information on background, status, architecture, programming, hardware reliability, applications, and the MPP's development as a national resource for parallel algorithm research are presented in outline form.

Source record↗

A VHSIC general purpose processor

The very high speed integrated circuit (VHSIC) program offers NASA and its contractors assured availability of military specification embedded computer components and integrated computer aided design/computer aided engineering and software development support that result in low system life costs for data management systems on the space station and the Earth Observatory Satellite. Viewgraphs given review progress in both the Department of Defense VHSIC program and the NASA VHSIC related insertion development of a general purpose processor are presented.

Benz, H. F.↗

Flight array processor

Spaceflight applications for the NASA Scatterometer (NSCAT) , an ocean surface wind measuring system flown as part of the Navy Remote Ocean Sensing System (NROSS) are discussed in outline form, along with information on the Advanced Digital Synthetic aperture radar Processor (ADSP) that is being developed for ground-based processing of spacecraft Earth observations. Design considerations are listed. A block diagram of the scatterometer is given.

Source record↗

Advanced Digital SAR Processor (ADSP)

The objectives are to develop the technology required to meet the synthetic aperture radar (SAR) processing needs for missions in the late 1980's, and to build and demonstrate a high performance engineering model flexible enough to be easily adapted to a wide variety of SAR processing tasks and capable of real-time or near real-time throughput rates. Information on the Advanced Digital SAR Processor is given in the form of outlines, carts and diagrams.

Bicknell, Tom↗

Baseband processor development/test performance for 30/20 GHz SS-TDMA communication system

The baseband processor (BBP) development for the 30/20 GHz Satellite Communication System is described. The SS-TDMA concept for future satellite communications is reviewed, describing the overall system, the satellite payload, and the frequency plan. A brief general description of the BBP is given, and the proof-of-concept model of the BBP is summarized. Key technologies and custom LSI developed for the BBP are listed. Finally, key technology developments and test data are reported for the BBP.

Brown, L.↗

Optical linear algebra processors - Architectures and algorithms

Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.

Casasent, David↗