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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

Field deployable trace radioisotope analysis through combined electrochemical and alpha spectroscopy methods

A method for depositing actinides directly onto a 4H-SiC Schottky barrier diode (SBD) detector as a field deployable actinides sensor was developed to enable off-site analysis, shortening the time to obtain critical information such as elements, concentration, and/or isotopic ratio related to the radiological situation. A thin film of Hg was first electrodeposited onto the Pt contact of the SiC diode, followed by chronoamperometric deposition of microgram levels of actinides under conventional control conditions. The 4H-SiC diode maintained consistent functionality through the electrodeposition process and showed resolved alpha-energy spectra that contained accurate isotopic information demonstrating the feasibility of a combined chemical and radiological sensor for field actinide detection and quantification.

38 RADIATION CHEMISTRY, RADIOCHEMISTRY, AND NUCLEA↗
NASA NTRS1996

Effect of Tilt Angle on the Morphology of SiC Epitaxial Films Grown on Vicinal (0001) SiC Substrates

In this study of 4H-SiC and 6H-SiC epitaxial films we found that film morphology was strongly dependent on the tilt angle of the substrate. Large surface steps (up to 25 nm high) due to step bunching were more prevalent at smaller tilt angles. Also, 4H films were more susceptible than 6H to 3C-SiC inclusions during growth. The lateral growth of steps from screw dislocations in low-tilt-angle substrates demonstrated that step bunching on the atomic scale was anisotropic with respect to growth direction for both 4H-SiC and 6H-SiC. A model explaining this behavior is presented. We observed and directly measured the Burgers vector of a 'super' screw dislocation in a 6H-SiC epilayer.

Powell, J. A.↗
NASA NTRS1997

Process-Induced Morphological Defects in Epitaxial CVD Silicon Carbide

Silicon carbide (SiC) semiconductor technology has been advancing rapidly, but there are numerous crystal growth problems that need to be solved before SiC can reach its full potential. Among these problems is a need for an improvement in the surface morphology of epitaxial films that are grown to produce device structures. Various processes before and during epilayer growth lead to the formation of morphological defects observed in SiC epilayers grown on SiC substrates. In studies of both 6H and 4H-SiC epilayers, atomic force microscopy (AFM) and other techniques have been used to characterize SiC epilayer surface morphology. In addition to the well-known micropipe defect, SiC epilayers contain growth pits, triangular features (primarily) in 4H-SiC, and macro step due to step bunching. In work at NASA Lewis, it has been found that factors contributing to the formation of some morphological defects include: defects in the substrate bulk, defects in the substrate surface caused by cutting and polishing the wafer, the tilt angle of the wafer surface relative to the basal plane, and growth conditions. Some of these findings confirm results of other research groups. This paper presents a review of published and unpublished investigations into processes that are relevant to epitaxial film morphology.

Powell, J. A.↗
NASA NTRS2010

A Novel Tungsten-Nickel Alloy Ohmic Contact to SiC at 900 C

A novel tungsten-nickel ohmic contact metallization on 4H-SiC and 6H-SiC capable of surviving temperatures as high as 900 C is reported. Preliminary results revealed the following: 1) ohmic contact on n-type 4H-SiC having net doping levels (Nd's) of 1.4 and 2 x 10(exp 19) per cubic centimeter, with specific contact resistances rhosNd's of 7.69 x 10(exp -4) and 5.81 x 10(exp -4) OMEGA (raised dot) square centimeters, respectively, after rapid thermal annealing (RTA), and 5.9 x 10(exp -3) and 2.51 x 10(exp -4) OMEGA (raised dot) square centimeters, respectively, after subsequent soak at 900 C for 1 h in argon, and 2) ohmic contact on n- and p-type 6H-SiC having Nd > 2 x 10(exp 19) and Na > 1 x 10(exp 20) per cubic centimeter, with rhosNd = 5 x 10(exp -5) and rhosNa = 2 X 10(exp -4) OMEGA (raised dot) square centimeter, respectively, after RTA, and rhosNd = 2.5 x 10 (exp -5) and rhosNa = 1.5 x 10(exp -4) OMEGA (raised dot) square centimeter after subsequent treatment at 900 C for 1 h in argon, respectively.

Okojie, Robert S.↗
NASA NTRS2006

CFD Growth of 3C-SiC on 4H/6H Mesas

This article describes growth and characterization of the highest quality reproducible 3C-SiC heteroepitaxial films ever reported. By properly nucleating 3C-SiC growth on top of perfectly on-axis (0001) 4H-SiC mesa surfaces completely free of atomic scale steps and extended defects, growth of 3C-SiC mesa heterofilms completely free of extended crystal defects can be achieved. In contrast, nucleation and growth of 3C-SiC mesa heterofilms on top of 4H-SiC mesas with atomic-scale steps always results in numerous observable dislocations threading through the 3C-SiC epilayer. High-resolution X-ray diffraction and transmission electron microscopy measurements indicate non-trivial in-plane lattice mismatch between the 3C and 4H layers. This mismatch is somewhat relieved in the step-free mesa case via misfit dislocations confined to the 3C/4H interfacial region without dislocations threading into the overlying 3C-SiC layer. These results indicate that the presence or absence of steps at the 3C/4H heteroepitaxial interface critically impacts the quality, defect structure, and relaxation mechanisms of single-crystal heteroepitaxial 3C-SiC films.

Neudeck, Philip G.↗
DOE OSTI2025

Sub-2 Kelvin Characterization of Nitrogen-Vacancy Centers in Silicon Carbide Nanopillars

The development of efficient quantum communication technologies depends on the innovation in multiple layers of its implementation, a challenge we address from the fundamental properties of the physical system at the nanoscale to the instrumentation level at the macroscale. We select a promising near-infrared quantum emitter, the nitrogen-vacancy (NV) center in 4H-SiC, and integrate it, at an ensemble level, with nanopillar structures that enhance photon collection efficiency into an objective lens. Moreover, changes in collection efficiency in pillars compared to bulk can serve as indicators of color center orientation in the lattice. To characterize NV center properties at the unprecedented sub-2 K temperatures, we incorporate compatible superconducting nanowire single photon detectors inside the chamber of an optical cryostat and create the ICECAP, the Integrated Cryogenic system for Emission, Collection And Photon detection. ICECAP measurements show no significant line-width broadening of NV ensemble emission and up to 14-fold enhancement in collected emission. With additional filtering, we measure emitter lifetimes of NV centers in a basal ( hk ) and axial ( kk ) orientation, unveiling their cryogenic values of 2.2 and 2.8 ns.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2025

Pulsed laser deposition assisted epitaxial growth of cesium telluride photocathodes for high brightness electron sources

The development of high-brightness electron sources is critical to state-of-the-art electron accelerator applications like X-ray free electron laser (XFEL) and ultra-fast electron microscopy. Cesium telluride is chosen as the electron source material for multiple cutting-edge XFEL facilities worldwide. This manuscript presents the first demonstration of the growth of highly crystalized and epitaxial cesium telluride thin films on 4H-SiC and graphene/4H-SiC substrates with ultrasmooth film surfaces. The ordering of the film was characterized by in situ reflection high energy electron diffraction and multiple X-ray diagnostics. The results of the quantum efficiency performance for epitaxial cesium telluride photocathodes are also reported.

43 PARTICLE ACCELERATORS↗
DOE OSTI2024

SMART SiC Power ICs: Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (Final Technical Report)

This collaborative project was initiated with the goal of developing Scalable, Manufacturable, and Robust Technology for SiC Power Integrated Circuits (SMART SiC Power ICs). In pursuit of this objective, innovative designs and fabrication processes were implemented, enabling the development of large-scale (>1 cm²) SiC Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits and high-voltage (400–600 V) lateral power MOSFETs (HV-LDMOS) on 150 mm 4H-SiC substrates. The resulting SMART SiC Power ICs are tailored to support a wide range of applications requiring diverse voltage and power levels, including automotive systems, industrial equipment, electronic data processing, energy harvesting, and power conditioning. To achieve the proposed ‘SMART’ technology for SiC ICs, the team focused on 1) the Development of highly scalable CMOS (with high channel mobilities for n-type and p-type MOSFETs), LDMOS (~600V, 10A rated), and IC technologies, 2) Establishment of a manufacturable process baseline in a production-grade-, 150mm, SiC fabrication facility, and 3) Demonstration of SMART SiC ICs. The project initially comprised of fabricating 5 lots. In lot 1 monolithic integration using a single process was achieved. Here, we were able to successfully accomplish Integrated HV NMOSFET with LV CMOS on N-epi/N+ Substrate. The HV NMOS demonstrated a Breakdown Voltage (BV) more than 600V. Circuit demonstration of CMOS was also another achievement from this lot. In lot 2, priority was in place for isolation and integration. Here we addressed the isolation concerns and integrated the HV NMOS and LV CMOS using the N-epi/P-epi/N+ substrate. Similar to the lot 1, we were able to achieve a BV of 600 V for HV NMOS. Optimized gate oxide process with high channel mobilities, better gate oxide reliability, development of SPICE models, successful ohmic process development, novel wafer area saving design layouts, P+ isolation schemes with channeling implantations and high temperature operational circuits demonstrations are some of the key highlights from lot 1 and lot2. In lot 3, discrete device performances of HV NMOS with a BV ~700V and reliable LV CMOS performances were achieved. Also, novel architectural solutions were successfully implemented to suppress the electric field crowding at the gate oxide for reliable operations. In lot 4, half bridge power driver ICs with a conversion efficiency of (target 90% to 95%) in the 1-5MHz switching frequency range for output power between 25 W to 3 kW have been included in. However, due to the unfortunate events of sudden foundry shutdown (SiCamore Semi) the processing of lot 4 wafers came to a complete stop (January 2024). Arrangements have recently been made to shift the fabrication to another foundry, General Electric Aerospace. The fabrication process now on course (as of December 2024). Characterizations are delayed due to this unfortunate circumstance. The proposed trench architectural-based devices and ICs (lot 5) underwent modifications from the original project proposal. This change was necessitated by limitations in the availability of trench-based processes at commercial production-grade fabrication facilities in the US. Apart from above achievements, a Process Development Kit (PDK) was successfully developed for planar type SiC CMOS/LDMOS.

42 ENGINEERING↗
DOE OSTI2025

Investigation of the Effect of Gate Oxide Screening with Adjustment Pulse on Commercial SiC Power MOSFETs

This paper presents a method to recover the negative threshold voltage shift during high field gate oxide screening of 1.2 kV 4H-SiC MOSFETs with an additional adjustment gate voltage pulse. To reduce field failure rates of the MOSFETs in operation, manufacturers perform a screening treatment to remove devices with extrinsic defects in the oxide. Current gate oxide screening procedures are limited to oxide fields at or below ~9 MV/cm for short durations (<1 s), which is not enough to remove all the devices with extrinsic defects. The results show that by implementing a lower field gate pulse, the threshold voltage shift can be partially recovered, and therefore the maximum screening field and time can be increased. However, both the initial screening pulse and the adjustment pulse require careful calibration to prevent significant degradation of the device threshold voltage, on-resistance, interface state density, or intrinsic lifetime. With a well calibrated set of pulses, higher screening fields can be utilized without significantly damaging the devices. This leads to an improvement in the overall screening efficiency of the process, reducing the number of devices with extrinsic oxide defects entering the field, and improving the reliability of the SiC MOSFETs in operation.

42 ENGINEERING↗
NASA NTRS1998

Gaseous Etching for Characterization of Structural Defects in Silicon Carbide Single Crystals

Single crystal SiC substrates were subjected to high-temperature H2/C3H8 gaseous etches. The etches resulted in a variety of surface features on 4H-SiC substrates that included elongated hillocks from 10 to more than 100 microns in length by a few microns in width. In some 4H- and 6H-SiC substrates, the etches resulted in a continuous coverage of macrosteps. We conclude that the morphology observed after the etching process is influenced by the local Si-C bilayer stacking sequence on the surface of off-(0001)oriented substrates. A model is presented for the formation of the hillocks, based on localized transformations of the 4H substrates during the high temperature etch process.

Powell, J. A.↗
NASA NTRS2001

Ab-Initio Description and Prediction of Properties of Carbon-Based and Other Non-Metallic Materials

We have resolved the long-standing problem consisting of 30%-50% theoretical underestimates of the band gaps of non-metallic materials. We describe the Bagayoko, Zhao, and Williams (BZW) method that rigorously circumvents the basis-set and variational effect presumed to be a cause of these underestimates. We present ab-initio, computational results that are in agreement with experiment for diamond (C), silicon (Si), silicon carbides (3C-SiC and 4H-SiC), and other semiconductors (GaN, BaTiO3, AlN, ZnSe, ZnO). We illustrate the predictive capability of the BZW method in the case of the newly discovered cubic phase of silicon nitride (c-Si3N4) and of selected carbon nanotabes [(10,0), and (8,4)]. Our conclusion underscores the inescapable need for the BZW method in ab-initio calculations that employ a basis set in a variational approach. Current nanoscale trends amplify this need. We estimate that the potential impact of applications of the BZW method in advancing our understanding of nonmetallic materials, in informing experiment, and particularly in guiding device design and fabrication is simply priceless.

Bagayoko, D.↗
NASA NTRS2002

Method for Growing Low-Defect Single Crystal Heteroepitaxial Films

A method is disclosed for growing high-quality low-defect crystal films heteroepitaxially on substrates that are different than the crystal films. The growth of the first two heteroepitaxial bilayers is performed on a first two-dimensional nucleate island before a second growth of two-dimensional nucleation is allowed to start. The method is particularly suited for the growth of 3C-SiC, 2H-AlN, or 2H-GaN on 6H-SiC, 4H-SiC, or silicon substrates.

Powell, J. Anthony↗
NASA NTRS2002

Growth of Defect-Free 3C-Sic on 4H- and 6H-SIC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3C-SiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (Delta/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗
NASA NTRS2004

Measurement of Thin Film Integrated Passive Devices on SiC through 500 C

Wireless communication in jet engines and high temperature industrial applications requires FD integrated circuits (RFICs) on wide bandgap semiconductors such as Silicon Carbide (SiC). In this paper, thin-film NiCr resistors, MIM capacitors, and spiral inductors are fabricated on a high purity semi-insulating 4H-SiC substrate. The devices are experimentally characterized through 50 GHz at temperatures of up to 500 C and the equivalent circuits are deembedded from the measured data. It is shown that the NiCr resistors are stable within 10% to 300 C while the capacitors have a value stable within 10% through 500 C.

Schwartz, Zachary D.↗
NASA NTRS2004

Growth and Characterization of Silicon-Carbide Hetero-Polytype Structures

Films discussed in this repok were deposited at NASA Glenn Research Center on on- orientation 4H-Sic substrates. Substrates were patterned in order to form mesa structures of different shapes and sizes. The nominal thickness of the 3C-Sic film was approximately 10 microns although the thickness could change considerably between defect-free and defected mesa structures. The primary objective was to identify defect structures in defect-free mesas and in particular determine the degree and mode of strain relaxation in 3C films with thickness exceeding critical thickness.

Skowronski, Marek↗
NASA NTRS2005

Static and Turn-on Switching Characteristics of 4H-Silicon Carbide SITs to 200 deg C

Test results are presented for normally-off 4H-SiC Static Induction Transistors (SITs) intended for power switching and are among the first normally-off such devices realized in SiC. At zero gate bias, the gate p-n junction depletion layers extend far enough into the conduction channel to cut off the channel. Application of forward gate bias narrows the depletion regions, opening up the channel to conduction by majority carriers. In the present devices, narrow vertical channels get pinched by depletion regions from opposite sides. Since the material is SiC, the devices are usable at temperatures above 150 C. Static curve and pulse mode switching observations were done at selected temperatures up to 200 C on a device with average static characteristics from a batch of similar devices. Gate and drain currents were limited to about 400 mA and 3.5 A, respectively. The drain voltage was limited to roughly 300 V, which is conservative for this 600 V rated device. At 23 C, 1 kW, or even more, could be pulse mode switched in 65 ns (10 to 90 percent) into a 100 load. But at 200 C, the switching capability is greatly reduced in large part by the excessive gate current required. Severe collapse of the saturated drain-to-source current was observed at 200 C. The relation of this property to channel mobility is reviewed.

Niedra, Janis M.↗
NASA NTRS2005

Improved Method of Manufacturing SiC Devices

The phrase, "common-layered architecture for semiconductor silicon carbide" ("CLASSiC") denotes a method of batch fabrication of microelectromechanical and semiconductor devices from bulk silicon carbide. CLASSiC is the latest in a series of related methods developed in recent years in continuing efforts to standardize SiC-fabrication processes. CLASSiC encompasses both institutional and technological innovations that can be exploited separately or in combination to make the manufacture of SiC devices more economical. Examples of such devices are piezoresistive pressure sensors, strain gauges, vibration sensors, and turbulence-intensity sensors for use in harsh environments (e.g., high-temperature, high-pressure, corrosive atmospheres). The institutional innovation is to manufacture devices for different customers (individuals, companies, and/or other entities) simultaneously in the same batch. This innovation is based on utilization of the capability for fabrication, on the same substrate, of multiple SiC devices having different functionalities (see figure). Multiple customers can purchase shares of the area on the same substrate, each customer s share being apportioned according to the customer s production-volume requirement. This makes it possible for multiple customers to share costs in a common foundry, so that the capital equipment cost per customer in the inherently low-volume SiC-product market can be reduced significantly. One of the technological innovations is a five-mask process that is based on an established set of process design rules. The rules provide for standardization of the fabrication process, yet are flexible enough to enable multiple customers to lay out masks for their portions of the SiC substrate to provide for simultaneous batch fabrication of their various devices. In a related prior method, denoted multi-user fabrication in silicon carbide (MUSiC), the fabrication process is based largely on surface micromachining of poly SiC. However, in MUSiC one cannot exploit the superior sensing, thermomechanical, and electrical properties of single-crystal 6H-SiC or 4H-SiC. As a complement to MUSiC, the CLASSiC five-mask process can be utilized to fabricate multiple devices in bulk single-crystal SiC of any polytype. The five-mask process makes fabrication less complex because it eliminates the need for large-area deposition and removal of sacrificial material. Other innovations in CLASSiC pertain to selective etching of indium tin oxide and aluminum in connection with multilayer metallization. One major characteristic of bulk micromachined microelectromechanical devices is the presence of three-dimensional (3D) structures. Any 3D recesses that already exist at a given step in a fabrication process usually make it difficult to apply a planar coat of photoresist for metallization and other subsequent process steps. To overcome this difficulty, the CLASSiC process includes a reversal of part of the conventional flow: Metallization is performed before the recesses are etched.

Okojie, Robert S.↗
NASA NTRS2001

Growth of Defect-Free 3C-SiC on 4H- and 6H-SiC Mesas Using Step-Free Surface Heteroepitaxy

A new growth process, herein named step-free surface heteroepitaxy, has achieved 3CSiC films completely free of double positioning boundaries and stacking faults on 4H-SiC and 6H-SiC substrate mesas. The process is based upon the initial 2-dimensional nucleation and lateral expansion of a single island of 3C-SiC on a 4H- or 6H-SiC mesa surface that is completely free of bilayer surface steps. Our experimental results indicate that substrate-epilayer in-plane lattice mismatch (delta a/a = 0.0854% for 3C/4H) is at least partially relieved parallel to the interface in the initial bilayers of the heterofilm, producing an at least partially relaxed 3C-SiC film without dislocations that undesirably thread through the thickness of the epilayer. This result should enable realization of improved 3C-SiC devices.

Neudeck, Philip G.↗