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Characterization and QC practice of 16-channel ADC ASIC at cryogenic temperature for Liquid Argon TPC front-end readout electronics system in DUNE experiment
ColdADC is a low-noise 16-channel analog-to-digital converter ASIC designed for cold readout electronics of Liquid Argon Time Projection Chambers (LArTPCs) in the Deep Underground Neutrino Experiment (DUNE). ColdADC was specifically designed for operation at cryogenic temperatures (77 K–89 K). Cold electronics is considered to be an enabling technology for liquid argon detectors in neutrino experiments. The main function of the chip is to digitize signals from the 16-channel charge-sensitive amplifier designed at BNL (LArASIC) and send digitized signals to the data aggregator and serializer chip (COLDATA). ColdADC operates with a resolution of 12 bits and a sampling rate of 2 MS/s per channel. A complete characterization of prototype chips was conducted at cryogenic temperature, involving power consumption, noise and linearity performance. In the first DUNE Far-Detector module, 384000 data channels will be read out, corresponding to 24000 ColdADC chips. Therefore, systematic testing of ColdADC chips at cryogenic temperature is vital for the quality and reliability of DUNE Single-Phase modules. We have developed a Quality Control (QC) test stand that includes ColdADC evaluation and characterization at cryogenic temperature. The QC procedure was applied to a first batch of 33 chips, corresponding to 528 data channels. The obtained results meet all the required DUNE specifications for ColdADC. Moreover, the testing outcome allowed us to identify possibilities of performance optimization that are currently being addressed in the design of the next version of the chip. The Quality Control procedure is proved to be successful and will be a reference design for future large-batch production testing of final ColdADC ASICs.
A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS
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A 2.1 GS/s 2-Channel Pipeline-SAR ADC With Speed-Enhanced Bootstrap Switch and Low-Latency SAR Logic
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ColdADC_P2: A 16-Channel Cryogenic ADC ASIC for the Deep Underground Neutrino Experiment
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Structural Insights into Inhibition of the Acinetobacter-Derived Cephalosporinase ADC-7 by Ceftazidi
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A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors [Poster]
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Chip Development Toward 12 bit 10 GSPS Cryogenic ADC for Multiplexed Quantum Readout
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A High Framerate Readout IC with in-Pixel ADC for X-Ray Detectors
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Readout IC with 40 MSPS in-pixel ADC for future vertex detector upgrades of Large Hadron Collider
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Design of a 12-bit 10-GSPS Cryogenic ADC for Quantum Readout
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Design of a Low-Jitter 10 GHz PLL for a 12-bit 10-GSPS Cryogenic ADC for Quantum Readout in 22FDX
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Attitude Determination and Control System (ADCS) and Maintenance and Diagnostic System (MDS): A maintenance and diagnostic system for Space Station Freedom
The Maintenance and Diagnostic System (MDS) that is being developed at Honeywell to enhance the Fault Detection Isolation and Recovery system (FDIR) for the Attitude Determination and Control System on Space Station Freedom is described. The MDS demonstrates ways that AI-based techniques can be used to improve the maintainability and safety of the Station by helping to resolve fault anomalies that cannot be fully determined by built-in-test, by providing predictive maintenance capabilities, and by providing expert maintenance assistance. The MDS will address the problems associated with reasoning about dynamic, continuous information versus only about static data, the concerns of porting software based on AI techniques to embedded targets, and the difficulties associated with real-time response. An initial prototype was built of the MDS. The prototype executes on Sun and IBM PS/2 hardware and is implemented in the Common Lisp; further work will evaluate its functionality and develop mechanisms to port the code to Ada.
Smithsonian Astrophysical Observatory (SAO) star catalog (Sao staff 1966, edition ADC 1989): Documentation for the machine-readable version
An updated, corrected, and extended machine readable version of the catalog is described. Published and unpublished errors discovered in the previous version were corrected, and multiple star and supplemental BD identifications were added to stars where more than one SAO entry has the same Durchmusterung number. Henry Draper Extension (HDE) numbers were added for stars found in both volumes of the extension. Data for duplicate SAO entries (those referring to the same star) were flagged. J2000 positions in usual units and in radians were added.
An Set-Free, All Digital Controlled Point-of-Load Regulator for Next Generation Power Systems: ADC-POL
This paper presents a digitally controlled programmable point-of-load regulator for next-generation power systems. A novel digital control scheme was designed to minimize single-event effect (SEE)-induced transient effects. By effectively programming the loop transmission, the POL can trade off transient response time with SET robustness. The IC works with 1 to 5.5 V input voltage, 1-4.5V regulated output voltage, high efficiency (peak efficiency at 94%) and power of up to 5 W. The design was fabricated in the AMI i2t100 0.7 mu m complimentary, metal-oxide semiconductor (CMOS) process and characterized with the Jet Propulsion Laboratory (JPL) pulsed laser system.
Radiation Hardening of a Wilkinson ADC for Distributed Motor Controller
No abstract available