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Appropriateness of the stimulus-reinforcement contingency in instrumental differential conditioning of the eyelid response to the arithmetic concepts of ''right and ''wrong.
Appropriateness of stimulus-reinforcement contingency in instrumental differential conditioning of eyelid response to arithmetic concepts of right and wrong
Arithmetic correctness as the discriminandum in classical and differential eyelid conditioning.
Arithmetic correctness as discriminandum in classical and differential eyelid conditioning
Hardware /or software/ provisions for multiple precision floating-point arithmetic
Hardware-software provisions for multiple precision floating point arithmetic
Arithmetic correctness as the discriminandum in classical and differential eyelid conditioning.
Classical and differential conditioning of eyelid response with correctness of solutions of arithmetic problems as discriminandum
Constrained Chebyshev approximations to some elementary functions suitable for evaluation with floating point arithmetic
Approximations which can be evaluated with precision using floating-point arithmetic are presented. The particular set of approximations thus far developed are for the function TAN and the functions of USASI FORTRAN excepting SQRT and EXPONENTIATION. These approximations are, furthermore, specialized to particular forms which are especially suited to a computer with a small memory, in that all of the approximations can share one general purpose subroutine for the evaluation of a polynomial in the square of the working argument.
Instabilities caused by floating-point arithmetic quantization.
It is shown that an otherwise stable digital control system can be made unstable by signal quantization when the controller operates on floating-point arithmetic. Sufficient conditions of instability are determined, and an example of loss of stability is treated when only one quantizer is operated.
Development of ferrite logic devices for an arithmetic processor
A number of fundamentally ultra-reliable, all-magnetic logic circuits are developed using as a basis a single element ferrite structure wired as a logic delay element. By making minor additions or changes to the basic wiring pattern of the delay element other logic functions such as OR, AND, NEGATION, MAJORITY, EXCLUSIVE-OR, and FAN-OUT are developed. These logic functions are then used in the design of a full-adder, a set/reset flip-flop, and an edge detector. As a demonstration of the utility of all the developed devices, an 8-bit, all-magnetic, logic arithmetic unit capable of controlled addition, subtraction, and multiplication is designed. A new basic ferrite logic element and associated complementary logic scheme with the potential of improved performance is also described. Finally, an improved batch process for fabricating joint-free power drive and logic interconnect conductors for this basic class of all-magnetic logic is presented.
Modular arithmetic weight and cyclic shifting.
This note shows that the modular arithmetic weight of an integer is invariant to the cyclic shifts of its radix-2 form. This result leads to a reduced search for the minimum weight codeword in a cyclic AN-code as well as to a better understanding of previous work.
Modular polynomial arithmetic in partial fraction decomposition
Algorithms for general partial fraction decomposition are obtained by using modular polynomial arithmetic. An algorithm is presented to compute inverses modulo a power of a polynomial in terms of inverses modulo that polynomial. This algorithm is used to make an improvement in the Kung-Tong partial fraction decomposition algorithm.
Optical systolic array processor using residue arithmetic
The use of residue arithmetic to increase the accuracy and reduce the dynamic range requirements of optical matrix-vector processors is evaluated. It is determined that matrix-vector operations and iterative algorithms can be performed totally in residue notation. A new parallel residue quantizer circuit is developed which significantly improves the performance of the systolic array feedback processor. Results are presented of a computer simulation of this system used to solve a set of three simultaneous equations.
A VLSI architecture for performing finite field arithmetic with reduced table look-up
A new table look-up method for finding the log and antilog of finite field elements has been developed by N. Glover. In his method, the log and antilog of a field element is found by the use of several smaller tables. The method is based on a use of the Chinese Remainder Theorem. The technique often results in a significant reduction in the memory requirements of the problem. A VLSI architecture is developed for a special case of this new algorithm to perform finite field arithmetic including multiplication, division, and the finding of an inverse element in the finite field.
Implementation of a fast digital optical matrix-vector multiplier using a holographic look-up table and residue arithmetic
The design and implementation of a digital (numerical) optical matrix-vector multiplier are presented. A Hughes liquid crystal light valve, the residue arithmetic representation, and a holographic optical memory are used to construct position coded optical look-up tables. All operations are performed in effectively one light valve response time with a potential for a high information density.
Vector-matrix-quaternion, array and arithmetic packages: All HAL/S functions implemented in Ada
The HAL/S avionics programmers have enjoyed a variety of tools built into a language tailored to their special requirements. Ada is designed for a broader group of applications. Rather than providing built-in tools, Ada provides the elements with which users can build their own. Standard avionic packages remain to be developed. These must enable programmers to code in Ada as they have coded in HAL/S. The packages under development at JPL will provide all of the vector-matrix, array, and arithmetic functions described in the HAL/S manuals. In addition, the linear algebra package will provide all of the quaternion functions used in Shuttle steering and Galileo attitude control. Furthermore, using Ada's extensibility, many quaternion functions are being implemented as infix operations; equivalent capabilities were never implemented in HAL/S because doing so would entail modifying the compiler and expanding the language. With these packages, many HAL/S expressions will compile and execute in Ada, unchanged. Others can be converted simply by replacing the implicit HAL/S multiply operator with the Ada *. Errors will be trapped and identified. Input/output will be convenient and readable.
Paranoia.Ada: A diagnostic program to evaluate Ada floating-point arithmetic
Many essential software functions in the mission critical computer resource application domain depend on floating point arithmetic. Numerically intensive functions associated with the Space Station project, such as emphemeris generation or the implementation of Kalman filters, are likely to employ the floating point facilities of Ada. Paranoia.Ada appears to be a valuabe program to insure that Ada environments and their underlying hardware exhibit the precision and correctness required to satisfy mission computational requirements. As a diagnostic tool, Paranoia.Ada reveals many essential characteristics of an Ada floating point implementation. Equipped with such knowledge, programmers need not tremble before the complex task of floating point computation.
A VLSI implementation of a correlator/digital-filter based on distributed arithmetic
The design of a VLSI chip which applies the ideas of distributed arithmetic to a nonrecursive digital filter is described. The main features of this design are very high precision and a high degree of flexibility, which allows one chip to implement a large number of quite different digital filters and correlators.
Floating point arithmetic in future supercomputers
Considerations in the floating-point design of a supercomputer are discussed. Particular attention is given to word size, hardware support for extended precision, format, and accuracy characteristics. These issues are discussed from the perspective of the Numerical Aerodynamic Simulation Systems Division at NASA Ames. The features believed to be most important for a future supercomputer floating-point design include: (1) a 64-bit IEEE floating-point format with 11 exponent bits, 52 mantissa bits, and one sign bit and (2) hardware support for reasonably fast double-precision arithmetic.