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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2015

Ground-referenced single-ended signaling connected graphics processing unit multi-chip module

A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Dally, William J.↗
DOE OSTI2015

How chip size impacts steam pretreatment effectiveness for biological conversion of poplar wood into fermentable sugars

We report that woody biomass is highly recalcitrant to enzymatic sugar release and often requires significant size reduction and severe pretreatments to achieve economically viable sugar yields in biological production of sustainable fuels and chemicals. However, because mechanical size reduction of woody biomass can consume significant amounts of energy, it is desirable to minimize size reduction and instead pretreat larger wood chips prior to biological conversion. To date, however, most laboratory research has been performed on materials that are significantly smaller than applicable in a commercial setting. As a result, there is a limited understanding of the effects that larger biomass particle size has on the effectiveness of steam explosion pretreatment and subsequent enzymatic hydrolysis of wood chips. To address these concerns, novel downscaled analysis and high throughput pretreatment and hydrolysis (HTPH) were applied to examine whether differences exist in the composition and digestibility within a single pretreated wood chip due to heterogeneous pretreatment across its thickness. Heat transfer modeling, Simons’ stain testing, magnetic resonance imaging (MRI), and scanning electron microscopy (SEM) were applied to probe the effects of pretreatment within and between pretreated wood samples to shed light on potential causes of variation, pointing to enzyme accessibility (i.e., pore size) distribution being a key factor dictating enzyme digestibility in these samples. Application of these techniques demonstrated that the effectiveness of pretreatment of Populus tremuloides can vary substantially over the chip thickness at short pretreatment times, resulting in spatial digestibility effects and overall lower sugar yields in subsequent enzymatic hydrolysis. Finally, these results indicate that rapid decompression pretreatments (e.g., steam explosion) that specifically alter accessibility at lower temperature conditions are well suited for larger wood chips due to the non-uniformity in temperature and digestibility profiles that can result from high temperature and short pretreatment times. Furthermore, this study also demonstrated that wood chips were hydrated primarily through the natural pore structure during pretreatment, suggesting that preserving the natural grain and transport systems in wood during storage and chipping processes could likely promote pretreatment efficacy and uniformity.

09 BIOMASS FUELS↗
DOE OSTI2016

Pyrolysis of ground pine chip and ground pellet particles

In addition to particle size, biomass density influences heat and mass transfer rates during the thermal treatment processes. In this research, thermal behaviour of ground pine chip particles and ground pine pellet particles in the range of 0.25–5 mm was investigated. A single particle from ground pellets was almost 3 to 4 times denser than a single particle from ground chips at a similar size and volume of particle. Temperature was ramped up from room temperature (~25 °C) to 600 °C with heating rates of 10, 20, 30, and 50 °C/min. Pellet particles took 25–88 % longer time to dry than the chip particles. Microscopic examination of 3 mm and larger chip particles showed cracks during drying. No cracks were observed for pellet particles. The mass loss due to treatment at temperatures higher than 200 °C was about 80% both for chip and pellet particles. It took 4 min for chip and pellet particles to lose roughly 63% of their dry mass at a heating rate of 50 °C/min. The SEM structural analysis showed enlarged pores and cracks in cell walls of the pyrolyzed wood chips. As a result, these pores were not observed in pyrolyzed pellet particles.

09 BIOMASS FUELS↗
DOE OSTI2018

Correlation between failure and local material property in chopped carbon fiber chip-reinforced sheet molding compound composites under tensile load

To develop further understanding towards the role of a heterogeneous microstructure on tensile crack initiation and failure behavior in chopped carbon fiber chip-reinforced composites, uni-axial tensile tests are performed on coupons cut from compression molded plaque with varying directions. Our experimental results indicate that failure initiation is relevant to the strain localization, and a new criterion with the nominal modulus to predict the failure location is proposed based on the strain analysis. Furthermore, optical microscopic images show that the nominal modulus is determined by the chip orientation distribution. At the area with low nominal modulus, it is found that chips are mostly aligning along directions transverse to loading direction and/or less concentrated, while at the area with high nominal modulus, more chips are aligning to tensile direction. On the basis of failure mechanism analysis, it is concluded that transversely-oriented chips or resin-rich regions are easier for damage initiation, while longitudinally-oriented chips postpone the fracture. Good agreement is found among failure mechanism, strain localization and chip orientation distribution.

36 MATERIALS SCIENCE↗
NASA NTRS1988

Programmable synaptic chip for electronic neural networks

A binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.

Moopenn, A.↗
NASA NTRS1992

Design and qualification of the SEU/TD Radiation Monitor chip

This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX). The Radiation Monitor chip consists of a custom-designed 4-bit SRAM for heavy ion detection and three MOSFET's for monitoring total dose. In addition the Radiation Monitor chip was tested along with three diagnostic chips: the processor monitor and the reliability and fault chips. These chips revealed the quality of the CMOS fabrication process. The SEU/TD Radiation Monitor chip had an initial functional yield of 94.6 percent. Forty-three (43) SEU SRAM's and 14 Total Dose MOSFET's passed the hermeticity and final electrical tests and were delivered to LL.

Buehler, Martin G.↗
NASA NTRS2001

Chip packaging technique

A hermetically sealed package for at least one semiconductor chip is provided which is formed of a substrate having electrical interconnects thereon to which the semiconductor chips are selectively bonded, and a lid which preferably functions as a heat sink, with a hermetic seal being formed around the chips between the substrate and the heat sink. The substrate is either formed of or includes a layer of a thermoplastic material having low moisture permeability which material is preferably a liquid crystal polymer (LCP) and is a multiaxially oriented LCP material for preferred embodiments. Where the lid is a heat sink, the heat sink is formed of a material having high thermal conductivity and preferably a coefficient of thermal expansion which substantially matches that of the chip. A hermetic bond is formed between the side of each chip opposite that connected to the substrate and the heat sink. The thermal bond between the substrate and the lid/heat sink may be a pinched seal or may be provided, for example by an LCP frame which is hermetically bonded or sealed on one side to the substrate and on the other side to the lid/heat sink. The chips may operate in the RF or microwave bands with suitable interconnects on the substrate and the chips may also include optical components with optical fibers being sealed into the substrate and aligned with corresponding optical components to transmit light in at least one direction. A plurality of packages may be physically and electrically connected together in a stack to form a 3D array.

Jayaraj, Kumaraswamy↗
NASA NTRS2006

Single-Chip T/R Module for 1.2 GHz

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Moussessian, Alina↗
DOE OSTI2018

Senescence chips for ultrahigh-throughput isolation and removal of senescent cells

Cellular senescence plays an important role in organismal aging and age-related diseases. However, it is challenging to isolate low numbers of senescent cells from small volumes of biofluids for downstream analysis. Furthermore, there is no technology that could selectively remove senescent cells in a high-throughput manner. In this work, we developed a novel microfluidic chip platform, termed senescence chip, for ultrahigh-throughput isolation and removal of senescent cells. The core component of our senescence chip is a slanted and tunable 3D micropillar array with a variety of shutters in the vertical direction for rapid cell sieving, taking advantage of the characteristic cell size increase during cellular senescence. The 3D configuration achieves high throughput, high recovery rate, and device robustness with minimum clogging. We demonstrated proof-of-principle applications in isolation and enumeration of senescent mesenchymal stem cells (MSCs) from undiluted human whole blood, and senescent cells from mouse bone marrow after total body irradiation, with the single cell resolution. After scale-up to a multilayer and multichannel structure, our senescence chip achieved ultrahigh-throughput removal of senescent cells from human whole blood with an efficiency of over 70% at a flow rate of 300 ml/hr. Sensitivity and specificity of our senescence chips could be augmented with implementation of multiscale size separation, and identification of background white blood cells using their cell surface markers such as CD45. With the advantages of high throughput, robustness, and simplicity, our senescence chips may find wide applications and contribute to diagnosis and therapeutic targeting of cellular senescence.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2026

Directional dependence of equilibrated TLD-400 chips in multiple radiation fields

Fielding of thermoluminescent dosimeters (TLDs) for measurement of photon radiation dose in experiments is the standard practice for γ-irradiation facilities, pulsed power x-ray facilities, and reactor facilities at Sandia National Laboratories (SNL). Due to the high-dose experimental conditions and the mixed ( 1 n, γ) fields in these facilities, SNL radiation metrologists have historically used CaF 2 :Mn TLDs (also known as TLD-400). Recent inquiries to the radiation metrology staff have raised concerns that the aluminum-equilibrated TLD-400 chips may exhibit a directionally dependent response. The metrologists were asked whether the dose measured by the chip may be impacted by the angle of incidence on the equilibrated TLD. To provide a thorough answer to this query, a set of adjoint Monte Carlo radiation transport calculations was performed for three different equilibrated TLDs as well as bare TLD chips using the Integrated Tiger Series (ITS) code. The key feature of the adjoint calculations performed in this study is that each photon escaping the modeled geometry was tallied into angular bins to provide information on both the energy and angular dependence of the equilibrated chip. After the adjoint Monte Carlo calculations were completed, the resulting energy-dependent response function for each angular bin was convolved with multiple photon energy spectra representing various radiation facilities at SNL. The radiation facilities selected for analysis span a range of photon energies from approximately 1 keV up to approximately 20 MeV. Thus, the presented results are applicable to a wide variety of radiation facilities around the world. Although the bare TLD-400 chip was expected to display the largest variation due to the photon angle of impact on the dosimeter, the dosimeter with the thinnest aluminum equilibrator (SNL thin equilibrated TLD-400) was determined to have the biggest differential between the impact angle with the maximum dose ( D max ) and the impact angle with the minimum dose ( D min ). However, the SNL normal equilibrated TLD-400 chip demonstrated a dramatic reduction in that differential between maximum and minimum dose angles. The reduction in this differential is one of the dominant factors in experimenters’ choice to field these dosimeters at SNL radiation facilities. The results from the PNNL (Hanford) energy-flattening field capsule are consistent with the previous publications. The differential dose responses due to the photon impact angle indicate that experimenters should strive to field their TLD-400 dosimeters in a consistent manner to avoid additional uncertainty in the measurements based on dosimeter orientation.

Adjoint radiation transport↗
DOE OSTI2015

Method of mechanical holding of cantilever chip for tip-scan high-speed atomic force microscope

In tip-scan atomic force microscopy (AFM) that scans a cantilever chip in the three dimensions, the chip body is held on the Z-scanner with a holder. However, this holding is not easy for high-speed (HS) AFM because the holder that should have a small mass has to be able to clamp the cantilever chip firmly without deteriorating the Z-scanner’s fast performance, and because repeated exchange of cantilever chips should not damage the Z-scanner. This is one of the reasons that tip-scan HS-AFM has not been established, despite its advantages over sample stage-scan HS-AFM. Here, we present a novel method of cantilever chip holding which meets all conditions required for tip-scan HS-AFM. The superior performance of this novel chip holding mechanism is demonstrated by imaging of the α{sub 3}β{sub 3} subcomplex of F{sub 1}-ATPase in dynamic action at ∼7 frames/s.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Atom-resolved imaging with a silicon tip integrated into an on-chip scanning tunneling microscope

Limited throughput is a shortcoming of the Scanning Tunneling Microscope (STM), particularly when used for atomically precise lithography. To address this issue, we have developed an on-chip STM based on Microelectromechanical-Systems (MEMS) technology. The device reported here has one degree of freedom, replacing the Z axis in a conventional STM. The small footprint of the on-chip STM provides a great opportunity to increase STM throughput by incorporating a number of on-chip STMs in an array to realize parallel STM. The tip methodology adopted for the on-chip STM presented here, which is a batch-fabricated Si tip, makes our design conducive to this goal. In this work, we investigate the capability of this on-chip STM with an integrated Si tip for STM imaging. We integrate the on-chip STM into a commercial ultrahigh-vacuum STM system and perform imaging with atomic resolution on par with conventional STMs but at higher scan speeds due to the higher sensitivity of the MEMS actuator relative to a piezotube. The results attest that it is possible to achieve a parallel and high-throughput STM platform, which is a fully batch-fabricated MEMS STM nanopositioner capable of performing atomic-resolution STM imaging.

Instruments & Instrumentation↗
DOE OSTI2025

Productivity and cost of energy chipping with non-integrated harvesting systems in the Coastal Plain of the US south

Research from the 1980s–2010s suggested that integrated harvesting systems that harvest conventional products (e.g., sawtimber, pulpwood) and energy chips simultaneously were the most effective solution to produce energy chips in the US South. Alternatives, such as biomass-only systems, have important advantages in forest stands with low volumes of merchantable timber. The goal of this study was to estimate the productivity and cost of producing energy chips using non-integrated systems. Innovative chipping contractors using non-integrated systems were identified through contacts with procurement foresters responsible for purchasing energy chips. Elemental time-and-motion studies were conducted to estimate harvesting productivity on five operations, including one clearcut harvest and four first thinnings in overstocked stands. The hourly cost of equipment was estimated using the machine rate method. Cost per tonne was estimated by combining hourly productivity and hourly costs in a modified version of the Auburn Harvesting Analyzer. System productivity averaged 37 tonnes per scheduled machine hour (smh) and cut-and-haul costs averaged $33.86 t −1 (USD), which was comparable to previous estimates from integrated systems. In conclusion, this study suggests there are viable alternatives to integrated harvesting systems to produce energy chips, especially in stands with low volumes of merchantable timber.

09 BIOMASS FUELS↗
NASA NTRS1991

Test chips and ASIC qualification

A test chip set being developed to aid in the qualification of spaceborne Application Specific Integrated Circuits (ASICs) is described. The chip set consists of a process monitor for process parameter verification, a fault chip for yield analysis, a reliability chip for ASIC failure rate analysis, and total ionizing dose and single event upset chips for radiation effect analysis. The test structures contained in these chips are discussed along with representative test results.

Buehler, M. G.↗
NASA NTRS1994

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗
NASA NTRS2010

Quad-Chip Double-Balanced Frequency Tripler

Solid-state frequency multipliers are used to produce tunable broadband sources at millimeter and submillimeter wavelengths. The maximum power produced by a single chip is limited by the electrical breakdown of the semiconductor and by the thermal management properties of the chip. The solution is to split the drive power to a frequency tripler using waveguides to divide the power among four chips, then recombine the output power from the four chips back into a single waveguide. To achieve this, a waveguide branchline quadrature hybrid coupler splits a 100-GHz input signal into two paths with a 90 relative phase shift. These two paths are split again by a pair of waveguide Y-junctions. The signals from the four outputs of the Y-junctions are tripled in frequency using balanced Schottky diode frequency triplers before being recombined with another pair of Y-junctions. A final waveguide branchline quadrature hybrid coupler completes the combination. Using four chips instead of one enables using four-times higher power input, and produces a nearly four-fold power output as compared to using a single chip. The phase shifts introduced by the quadrature hybrid couplers provide isolation for the input and output waveguides, effectively eliminating standing waves between it and surrounding components. This is accomplished without introducing the high losses and expense of ferrite isolators. A practical use of this technology is to drive local oscillators as was demonstrated around 300 GHz for a heterodyne spectrometer operating in the 2-3-THz band. Heterodyne spectroscopy in this frequency band is especially valuable for astrophysics due to the presence of a very large number of molecular spectral lines. Besides high-resolution radar and spectrographic screening applications, this technology could also be useful for laboratory spectroscopy.

Lin, Robert H.↗
NASA NTRS2013

Automated, Ultra-Sterile Solid Sample Handling and Analysis on a Chip

There are no existing ultra-sterile lab-on-a-chip systems that can accept solid samples and perform complete chemical analyses without human intervention. The proposed solution is to demonstrate completely automated lab-on-a-chip manipulation of powdered solid samples, followed by on-chip liquid extraction and chemical analysis. This technology utilizes a newly invented glass micro-device for solid manipulation, which mates with existing lab-on-a-chip instrumentation. Devices are fabricated in a Class 10 cleanroom at the JPL MicroDevices Lab, and are plasma-cleaned before and after assembly. Solid samples enter the device through a drilled hole in the top. Existing micro-pumping technology is used to transfer milligrams of powdered sample into an extraction chamber where it is mixed with liquids to extract organic material. Subsequent chemical analysis is performed using portable microchip capillary electrophoresis systems (CE). These instruments have been used for ultra-highly sensitive (parts-per-trillion, pptr) analysis of organic compounds including amines, amino acids, aldehydes, ketones, carboxylic acids, and thiols. Fully autonomous amino acid analyses in liquids were demonstrated; however, to date there have been no reports of completely automated analysis of solid samples on chip. This approach utilizes an existing portable instrument that houses optics, high-voltage power supplies, and solenoids for fully autonomous microfluidic sample processing and CE analysis with laser-induced fluorescence (LIF) detection. Furthermore, the entire system can be sterilized and placed in a cleanroom environment for analyzing samples returned from extraterrestrial targets, if desired. This is an entirely new capability never demonstrated before. The ability to manipulate solid samples, coupled with lab-on-a-chip analysis technology, will enable ultraclean and ultrasensitive end-to-end analysis of samples that is orders of magnitude more sensitive than the ppb goal given in the Science Instruments.

Mora, Maria F.↗
NASA NTRS2015

Ion Chromatography-on-a-chip for Water Quality Analysis

We report progress towards developing a Micro-Electro-Mechanical Systems (MEMS)- based ion chromatograph (IC) for crewed spacecraft water analysis. This IC-chip is an offshoot of a NASA-funded effort to produce a high performance liquid chromatograph (HPLC)-chip. This HPLC-chip system would require a desalting (i.e. ion chromatography) step. The complete HPLC instrument consists of the Jet Propulsion Labortory's (JPL's) quadrupole ion trap mass spectrometer integrated with a state-of-the-art MEMS liquid chromatograph (LC) system developed by the California Institute of Technology's (Caltech's) Micromachining Laboratory. The IC version of the chip consist of an electrolysis-based injector, a separation column, two electrolysis pumps for gradient generation, mixer, and a built-in conductivity detector. The HPLC version of the chip also includes a nanospray tip. The low instrument mass, coupled with its high analytical capabilities, makes the LC chip ideally suitable for wide range of applications such as trace contaminant, inorganic analytical science and, when coupled to a mass spectrometer, a macromolecular detection system for either crewed space exploration vehicles or robotic planetary missions.

Kidd, R. D.↗