DC Modeling of 4H-SiC JFET Gate Length Reduction at 500°C
The development of robust, high-performance integrated circuits (ICs) will enable numerous potential NASA missions of current interest, including long-duration robotic missions exploring the 460 °C surface of Venus. Currently, NASA is looking towards SiC-based devices to provide such a solution. However, the current NASA silicon carbide (SiC) JFET device with a channel length of 6μm (for recently fabricated Gen. 11 ICs) limits on mission relevant circuit capabilities [1]. In this study, we combined experiments with simulations to explore two straightforward fabrication strategies to reduce the SiC JFET channel length while maintaining turn-off behavior (Fig. 1a) needed to realize 500 °C circuit operation. The first fabrication strategy uses a shallow self-align nitrogen implant (Figure 1b) along the device's top surface but not below the gate combined with a high-dose phosphorous implant directly below the source and drain contacts. For the second fabrication strategy (Figure 1c), the high-dose phosphorous implants extended from below the contacts all the way up to the gate edges. Simulations guided gate length reductions without significant degradation in the turn-off performance. In total 12 SiC JFET variants implementing using the different fabrication strategies, gate lengths, and n-channel epilayer thickness were implemented in our simulation framework implemented in COMSOL. Since the COMSOL database does not have the material properties for 4H-SiC, these parameters were taken from the literature and implemented in COMSOL. The empirical models [2] for incomplete ionization, Auger recombination, low field mobility, and Shockley-Read-Hall recombination were implemented to account for material-specific device behavior.