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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Evaluation of the DC bus link capacitors and power transistor modules in the qualification testing of PV inverters

To achieve useful, fair, and cost-effective design qualification and type approval testing for PV inverters, two procedures were developed and demonstrated to evaluate the bus link capacitors and power transistor—and where applicable, its module—for long-term reliability. We evaluate the inverter under simulated use conditions with heat run tests to find the highest operating temperatures reached by these components. The procedures are demonstrated in this study with a 4-kVA class string inverter. The maximum temperature of the DC bus link capacitors was determined to be 76.4°C when the ambient temperature was at the inverter's maximum rated temperature of 60°C with derating occurring. On the other hand, the power transistor module's maximum temperature using the heat sink temperature as the index, 92.6°C, occurred in an ambient of 40.8°C when derating was not occurring. The conditions found for upper temperatures exhibited by these components are, respectively, proposed for implementation in the dry heat and thermal cycling tests in the IEC 62093 “Power conversion equipment for photovoltaic systems – Design qualification testing” international standard draft so that the levels applied in the tests are in proportion to those experienced in the field. Finally as a result, fairer evaluation of inverter reliability is realized.

14 SOLAR ENERGY↗
DOE OSTI2023

A Reconfigurable Planar Capacitor Sensor for Thru the Jacket Dielectric Constant Measurement of Cable Insulation

Planar capacitor sensors have been proposed to measure the aging-related dielectric constant variation of the jacket or insulation materials of cables. Although capacitor sensors have been used to monitor the aging of cable insulation by removing the jacket, through the jacket measurement of cable insulation dielectric constant variation is difficult because once the sensor is placed on the jacket it would either measure the aging of the jacket or that of the jacket and insulation together. A reconfigurable sensor along with innovative cable-specific models could be used to determine the jacket and insulation aging using the same sensor. For the proposed novel reconfigurable sensor, the electric field penetration depth is changed by activating and deactivating PIN diode switches. In one instance, the sensor measures the dielectric constant variation of the jacket, while in the next, it measures the dielectric constant variation of both the jacket and the insulation. Here, by leveraging previously developed capacitance estimation models from large-scale finite element simulations for a specific cable, these two sets of measurement data are used to evaluate the aging-related dielectric constant variation of the insulation. Experimental data from aged cable specimens are presented to demonstrate the operation of the sensor.

47 OTHER INSTRUMENTATION↗
DOE OSTI2025

Upcycling Polyethylene Waste Into Hybrid Graphitic Porous Carbon Materials Used in High-Performance Zinc-Ion Hybrid Capacitors

Polyethylene (PE) waste is a challenge to upcycle into useful materials because this plastic tends to decompose into volatile compounds when heated at relatively low temperatures. In this work, we report a chemical process that addresses this challenge by converting mixtures of linear low-density polyethylene (LLDPE), low-density polyethylene (LDPE), and high-density polyethylene (HDPE) waste into a hybrid graphitic porous carbon (HGPC) that can be used as a zinc-ion hybrid capacitor cathode. The process uses a low temperature thermal oxidation pre-treatment step, with assistance of an inert solid additive (KCl) to increase the effective surface area of the PE melt, to functionalize, cross-link, and stabilize the PE waste followed by carbonization and catalytic graphitization steps at higher temperatures with a potassium carbonate (K2CO3) catalyst. The PE waste derived HPGC (PW-HPGC) has a hybrid structure composed of graphene-like carbon nanosheets grown on the surface of carbon particles, high porosity with the Brunauer–Emmett–Teller (BET) specific surface area up to 1,763 m2g-1, and good graphitic degree with average Raman I2D/IG ratios of 0.53. When used as a cathode material for zinc-ion hybrid capacitors, this PW-HGPC exhibits an excellent specific capacity up to 126.7 mAhg-1 at high mass loading of 10 mgcm-2. Moreover, PW-HGPC exhibits remarkable cycling stability with capacity retention of >94% after 10,000 cycles at a current density of 2.0 A g-1.

hybrid graphitic porous carbon↗
DOE OSTI2020

DC Link Capacitor Reduction with Feedforward Control in Series-Series Compensated Wireless Power Transfer Systems

This paper presents the use of feedforward control to reduce the input side DC link capacitance of series-series compensated wireless power transfer (WPT) systems. Compared to conventional control schemes for WPT systems, the proposed feedforward-based approach achieves significant reduction in the DC link capacitor without any complicated voltage or current sensing requirements from the secondary side. This results in more compact hardware architecture. The proposed method shows minimal increase in the turn-on switching loss of the inverter. The switching loss is analyzed, and detailed results are presented relating the switching loss to the DC link capacitance and voltage ripple for proper tradeoff between losses and capacitor size. Simulation and experimental results presented validate the proposed scheme.

Mukherjee, Subho↗
DOE OSTI2021

Efficiency Optimization of Dual Active Bridge Converter Based on dV/dt Snubber Capacitors

This paper presents a lossless regenerative dV/dt snubber circuit for PWM converters to achieve high-efficiency high power-density without significant cost and reliability penalties. The dV/dt snubber employs lossless capacitors for each MOSFET device in a converter to provide an additional path to store the switching energy during turn-off transient and decrease the actual turn-off loss of the MOSFET channel. A novel mathematical turn-off loss model is built to separate the actual turn-off loss of the MOSFET channel and the recycling switching energy stored in the total equivalent output capacitance including Coss, the dV/dt snubber, and etc. Necessary snubber optimization strategy is proposed in order to balance the turn-off loss with ZVS operation range and deadtime conduction loss, and thereby achieving an optimal efficiency performance. To prove the validity and accuracy of the novel turn-off loss model and optimization strategy, the dV/dt snubber has been incorporated into a 1.3kV/200kW DC/DC and a 1kV/70kVA DC/AC PWM converters. Experimental results are given to demonstrate the validity of the proposed dV/dt snubber capacitors and optimization strategy.

Xu, Wei↗
DOE OSTI2024

Predictive Control to Further Reduce DC-Link Capacitor Current Stress for Segmented Inverter

Two three-phase interleaved inverters have been used in traction drive applications to reduce the current stress in a DC link capacitor bank. In such applications, either carrier-based or space vector modulation is used to select the optimum switching sequences, and the results show 50% less capacitor current than that of a single three-phase inverter. The switching state selection process for this inverter is tedious, and there has been no research to find the optimal switching state. To overcome this challenge, this research employed a simple finite set model predictive control to select the optimum switching sequence for a dual three-phase interleaved topology, called a segmented inverter. The results show that the predictive control algorithm can provide a simple solution and can reduce the current stress by 27% compared with traditional modulation techniques for the segmented inverters.

Ribeiro, Pedro↗
DOE OSTI2024

Increasing Multilayer Ceramic Capacitor Lifetime With Bipolar Voltage Cycling

Enhancing the lifetime of multilayer ceramic capacitors (MLCCs) is critical in many aerospace, naval, or electrical grid applications, where device failure could lead to catastrophic consequences. The migration of oxygen vacancies from the ceramic to the electrode interface under constant bias is known to reduce the lifetime of oxide-based MLCCs. Bias cycling presents an opportunity to enhance MLCC lifetime by reducing oxygen vacancy migration. The ideal frequency range is expected to lie between frequencies low enough to avoid self-heating but high enough to avoid interfacial defect formation. However, the impact of low-frequency bipolar voltage cycling (BVC) on MLCC degradation mechanisms has not been well studied. This work investigates the impact of periodic BVC on the degradation of MLCCs through highly accelerated lifetime testing (HALT) on X7R capacitors. HALT tests were conducted at 255 °C and 60 V using different switching frequencies: 0 (dc), 0.1, 2.5, and 10 Hz. BVC was found to improve the lifetime of MLCCs compared to dc test conditions. MLCCs tested at 10-Hz BVC showed a 311% increase in average time to failure compared to the dc case. Impedance spectroscopy shows that BVC decreases the rate of resistance degradation within MLCCs, indicating that oxygen vacancy migration to the electrodes is mitigated. The impedance spectra taken on BVC samples highlight how grain boundaries play a vital role in trapping oxygen vacancies. Periodic cycling causes oxygen vacancies to become trapped at grain boundaries, resulting in oxygen vacancies taking longer to reach the electrode interface and thus increasing MLCC lifetime. This work highlights not only how BVC can be used to increase MLCC lifetime but also how periodically cycling MLCCs could increase lifetime in extreme environments, such as at elevated temperatures and electric fields.

Chuong, Kayla Y.↗
DOE OSTI2025

Demonstration of Vertical 2T-nC FeRAM Hybrid Cell and Its Scalability for High-Density 3-D Ferroelectric Capacitor Memory

In this work, we present a comprehensive experimental and modeling study on the scaling of vertical 2T-nC ferroelectric random access memory (FeRAM) hybrid cells, comprising n metal-ferroelectric–metal (MFM) capacitors, to demonstrate a high-performance and high-density 3-D capacitor memory. Our contributions include: 1) successful process integration of vertical 2T-3C FeRAM cells by stacking MFM structures on top of Si CMOS transistors; 2) experimental validation of memory cell functionality, confirming the feasibility of the vertical 2T-nC FeRAM architecture; 3) an analysis of scaling effects on parasitic capacitance in densely integrated 3-D arrays, using 3-D technology computer-aided design (TCAD) simulations; 4) exploration of aggressive stacking of write bitlines (WBLs) to enhance memory density, where ferroelectric linear capacitance ( C FE ) enables self-boosted inhibition under the V W /2 scheme, but renders the V W /3 scheme ineffective due to intolerable write disturbances; and 5) assessment of horizontal scaling, revealing significant increases in read disturbances caused by interplane capacitance between adjacent WBLs ( C Z ). This work represents an early exploration into the potential of 2T-nC FeRAM as a scalable and efficient 3-D memory solution.

42 ENGINEERING↗
DOE OSTI2019

Reduced Common-Mode Voltage PWM Scheme for Full-SiC Three-Level Uninterruptible Power Supply With Small DC-Link Capacitors

In this article, a pulsewidth modulation (PWM) scheme for three-level full-SiC uninterruptible power supplies is developed to achieve a high power density. Two key passive components are selected for size reduction of the ac-ac stage: common-mode (CM) EMI filter, and dc-link capacitors. To reduce the CM noise, a new vector combination is proposed based on synchronous switching among three-phases. The proposed combinations align CM voltage (CMV) to be a single pulse per switching period. Owing to the simple shape, CMV cancellation between a three-level rectifier and inverter can be maximally utilized. A transition between the three combinations can control the drift of neutral point voltage. An equivalent carrier-based implementation is developed. Second, a simple algorithm to compensate neutral point voltage fluctuation is proposed both for differential mode (DM) and CM output voltage. Low-order harmonics on three-phase currents and an additional high-frequency CM noise by misaligned switching instant can be eliminated. The proposed compensation can be implemented by a simple correction on carrier slopes and injected zero-sequence voltage. The proposed PWM scheme is verified with 20-kW full-SiC UPS switching at 60 kHz with 140 μF dc-link capacitors.

42 ENGINEERING↗
DOE OSTI2022

Medium voltage planar DC bus distributed capacitor array

An inverter with a modular bus assembly is described. In various embodiments, the modular bus assembly includes a laminated motherboard and a plurality of capacitor daughtercards. The laminated motherboard can be configured to interface a plurality of phase-leg modules and a plurality of capacitor daughtercards through a plurality of terminals and connectors located on a bottom side or a top side of the laminated motherboard. The laminated motherboard includes a layer stack with a plurality of conductor layers. Each of the plurality of conductor layers is implemented with a net spacing from a neighboring plated through hole (PTH) based at least in part on differences in potential to be applied to each of the plurality of conductor layers as compared to a potential to be applied to the PTH. Embedded shield polygons can be implemented on the laminated motherboard to mitigate surface discharge at surface terminal (PTH/SMT) triple junctions.

Ravi, Lakshmi↗
DOE OSTI2024

Multi-resonant switched capacitor power converter architecture

A switched-capacitor (SC) network in an SC converter is controlled to operate at varying resonant modes to achieve high conversion ratio efficiency, at a low circuit component count. These power converters are suited to numerous application areas including improving energy efficiency of data centers. A family of resonant switched capacitor (SC) converters with multiple operating phases are presented “Multi-Resonant SC Converters”. Described in detail are an 8-to-1 Multi-Resonant-Doubler (MRD) converter and a 6-to-1 Cascaded Series-Parallel (CaSP). The topology of these converters make them amenable to combining like units in parallel toward reaching higher power levels.

Ye, Zichao↗
DOE OSTI2021

A machine learning degradation model for electrochemical capacitors operated at high temperature

Electrochemical capacitors (ECs) have only recently been considered as an alternative power source for telemetry sensors of drilling equipment for geothermal or oil and gas exploration. The lifecycle analysis and modelling of ECs is underrepresented in literature in comparison to other storage devices e.g. Li-ion batteries. This paper investigates the degradation of ECs when cycled outside the manufacturer-specified operating temperature envelope and proposes a machine learning-based approach for modelling the degradation. Experimental results show that end of life, defined as a 30% decrease in capacitance, occurs at 1,000 cycles when the environmental temperature exceeds the maximum operating temperature by 30%. The life-cycle test data is then used as an input to a Gaussian process regression (GPR) algorithm to predict the capacitance fade trend. The GPR is validated on a total of nine commercial cells from two different manufacturers, achieving an average root mean squared percent error of less than 2% and a mean calibration score of 93% when referenced to a 95% confidence interval. The model can be utilized to determine the EC degradation rate at a range of operating temperature values.

42 ENGINEERING↗
DOE OSTI2023

In Situ Observation of Domain Wall Lateral Creeping in a Ferroelectric Capacitor

As a promising candidate for next-generation nonvolatile memory devices, ferroelectric oxide films exhibit many emergent phenomena with functional applications, making understanding polarization switching and domain evolution behaviors of fundamental importance. However, tracking domain wall motion in ferroelectric oxide films with high spatial resolution remains challenging. Here, in this study, an in situ biasing approach for direct atomic-scale observations of domain nucleation and sideways motion is presented. By accurately controlling the applied electric field, the lateral translational speed of the domain wall can decrease to less than 2.2 Å s −1 , which is observable with atomic resolution STEM imaging. In situ observations on a capacitor structured PbZr 0.1 Ti 0.9 O 3 /La 0.7 Sr 0.3 MnO 3 heterojunction demonstrate the unique creeping behavior of a domain wall under a critical electric field, with the atomic structure of the creeping domain wall revealed. Moreover, the evolution of the metastable domain wall forms an elongated morphology, which contains a large proportion of charged segments. Phase-field simulations unveil the competition between gradient, elastic, and electrostatic energies that decide this unique domain wall creeping and morphology variation. This work paves the way toward a complete fundamental understanding of domain wall physics and potential modulations of domain wall properties in real devices.

36 MATERIALS SCIENCE↗
DOE OSTI2021

Controlling MoO 2 and MoO 3 phases in MoO x /CNTs nanocomposites and their application to anode materials for lithium-ion batteries and capacitors

Molybdenum oxides (MoO 2 and MoO 3 ) are attractive anode materials for Li- and Na- ion batteries. Although there have been extensive studies on them individually, systematic and comparative studies are still lacking. Here, we demonstrate a facile and straightforward synthesis method to control the phase and oxidation state in the MoO x /CNTs nanocomposites via hydrothermal reaction followed by heat-treatment. By changing the gas atmosphere during the annealing process, well-dispersed MoO 2 /CNTs and MoO 3 /CNTs nanocomposites are formed without altering their overall morphology. This strategy enables us to investigate the true structure-property correlation of MoO x /CNTs nanocomposites by comparing the structure and electrochemical properties of MoO 2 /CNTs and MoO 3 /CNTs. When tested as anode materials for lithium-ion batteries, both HT-MoO 2&3 /CNTs electrodes show much-improved cycling stability and rate performance compared to the rod-shaped bulk MoO 3 electrode. In situ Mo K-edge x-ray absorption spectroscopy (XAS) has been further employed to compare and elucidate Li + storage mechanisms of both electrodes. When employed to the negative electrode of a high-power lithium-ion capacitor (LIC), the LIC full-cell composed of HT-MoO 3 /CNTs negative and activated carbon positive electrodes demonstrates impressive energy and power densities (~ 90 Wh kg –1 with 2000 W kg –1 ) and excellent cycling stability (96.8 % capacity retention after 300 cycles), revealing the versatility of the MoO x /CNTs electrodes in energy applications.

25 ENERGY STORAGE↗
DOE OSTI2022

Effect of oxide layer growth conditions on radiation detection performance of Ni/SiO 2 /epi-4H-SiC MOS capacitors

We report high resolution radiation detection has been demonstrated using Ni/SiO2/n-4H-SiC metal-oxidesemiconductor vertical capacitors fabricated using highly crystalline 4H-SiC epilayers. The oxide layers have been grown thermally using two different approaches: i) in-air, and ii) oxygen-ambience oxidation. The devices fabricated using the former method exhibited dark currents one order of magnitude higher than that in the latter. The observed difference has been attributed to the back-contact series resistance and capacitance. Regardless of the difference in the device parameters, detectors prepared using both of the methods exhibited very high energy resolutions of ≤ 0.5% for 5486 keV alpha particles emitted by an 241Am radioisotope. Capacitance mode deep level transient spectroscopic (DLTS) studies revealed similar type of electrically active defects along with Z1/2 and EH5 deep level defects in both the types of devices. The DLTS scans also revealed positive polarity peaks in these devices which indicate emission from minority carrier trap centers. The activation energy corresponding to the peak was found to be ~1.2 eV which has been assigned to HK3 defects responsible for hole trapping in 4H-SiC. The possibility of appearance of the positive peak due to non-negligible impedance of the back-contact has been ruled out based on the observation that the centroid of the observed peak did not change with detectors having different device parameters.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Effect of fabrication processes on BaTiO 3 capacitor properties

There is an increasing desire to utilize complex functional electronic materials such as ferroelectrics in next-generation microelectronics. As new materials are considered or introduced in this capacity, an understanding of how we can process these materials into those devices must be developed. Here, the effect of different fabrication processes on the ferroelectric and related properties of prototypical metal oxide (SrRuO 3 )/ferroelectric (BaTiO 3 )/metal oxide (SrRuO 3 ) heterostructures is explored. Two different types of etching processes are studied, namely, wet etching of the top SrRuO 3 using a NaIO 4 solution and dry etching using an Ar + -ion beam (i.e., ion milling). Polarization-electric-field hysteresis loops for capacitors produced using both methods are compared. For the ion-milling process, it is found that the Ar + beam can introduce defects into the SrRuO 3 /BaTiO 3 /SrRuO 3 devices and that the milling depth strongly influences the defect level and can induce a voltage imprint on the function. Realizing that such processing approaches may be necessary, work is performed to ameliorate the imprint of the hysteresis loops via ex situ “healing” of the process-induced defects by annealing the ferroelectric material in a barium-and-oxygen-rich environment via a chemical-vapor-deposition-style process. This work provides a pathway for the nanoscale fabrication of these candidate materials for next-generation memory and logic applications.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Spontaneous Polarization in an Ultrathin Improper-Ferroelectric/Dielectric Bilayer in a Capacitor Structure at Cryogenic Temperatures

To determine the effect of depolarization and the critical thickness in improper-ferroelectric hexagonal-ferrite thin films, we investigate the polarization switching of a ferroelectric/dielectric bilayer in capacitor structures at 20 K. Experimentally, we show that the spontaneous polarization persists throughout the studied thickness range (3 to 80 unit cell), even with a thick (10-nm) dielectric layer, suggesting no practical thickness limit for applications. By fitting the effect of depolarization using the phenomenological theory, we show that the spontaneous polarization remains finite when the thickness of the ferroelectric layer approaches zero, providing a hint for the absence of critical thickness. We also find that the interfacial effects limit the multidomain formation and govern the polarization switching mechanisms.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2020

Enhanced Performance of Dual Inverter with a Floating Capacitor for Motor Drive Applications

This paper studies a dual inverter supplied by a DC-link and a floating capacitor (FC), emerged as a promising inverter topology for motor drive applications. For this type of inverter, the voltage ratio between the DC-link and the FC can be actively controlled. This ratio design is crucial as it essentially defines both the DC-link voltage utilization and the inverter output quality. Several voltage ratios have previously been discussed to enhance the dual inverter performance, but only one aspect, either the voltage utilization or the output quality, is investigated. As a result, although one performance aspect can be improved, the other aspect has been adversely affected. In this work, a comparative study considering both aspects is carried out for all the possible voltage ratios. Based on this analysis, the optimal ratios for different inverter modulation indices are identified. This is followed by proposing a ratio selection strategy to double the voltage utilization without degrading the output quality. Furthermore, this strategy enables an electric drive to work at a higher maximum speed without flux weakening for a given DC-link voltage. The claimed advantages have been proved by experimental tests on an open-end windings induction motor drive.

42 ENGINEERING↗