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Results for “Complementary Metal Oxide Semiconductor (CMOS)”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2011

Architecture for a 1-GHz Digital RADAR

An architecture for a Direct RF-digitization Type Digital Mode RADAR was developed at GSFC in 2008. Two variations of a basic architecture were developed for use on RADAR imaging missions using aircraft and spacecraft. Both systems can operate with a pulse repetition rate up to 10 MHz with 8 received RF samples per pulse repetition interval, or at up to 19 kHz with 4K received RF samples per pulse repetition interval. The first design describes a computer architecture for a Continuous Mode RADAR transceiver with a real-time signal processing and display architecture. The architecture can operate at a high pulse repetition rate without interruption for an infinite amount of time. The second design describes a smaller and less costly burst mode RADAR that can transceive high pulse repetition rate RF signals without interruption for up to 37 seconds. The burst-mode RADAR was designed to operate on an off-line signal processing paradigm. The temporal distribution of RF samples acquired and reported to the RADAR processor remains uniform and free of distortion in both proposed architectures. The majority of the RADAR's electronics is implemented in digital CMOS (complementary metal oxide semiconductor), and analog circuits are restricted to signal amplification operations and analog to digital conversion. An implementation of the proposed systems will create a 1-GHz, Direct RF-digitization Type, L-Band Digital RADAR--the highest band achievable for Nyquist Rate, Direct RF-digitization Systems that do not implement an electronic IF downsample stage (after the receiver signal amplification stage), using commercially available off-the-shelf integrated circuits.

Mallik, Udayan↗
NASA NTRS2011

Rad-Hard, Miniaturized, Scalable, High-Voltage Switching Module for Power Applications Rad-Hard, Miniaturized

A paper discusses the successful development of a miniaturized radiation hardened high-voltage switching module operating at 2.5 kV suitable for space application. The high-voltage architecture was designed, fabricated, and tested using a commercial process that uses a unique combination of 0.25 micrometer CMOS (complementary metal oxide semiconductor) transistors and high-voltage lateral DMOS (diffusion metal oxide semiconductor) device with high breakdown voltage (greater than 650 V). The high-voltage requirements are achieved by stacking a number of DMOS devices within one module, while two modules can be placed in series to achieve higher voltages. Besides the high-voltage requirements, a second generation prototype is currently being developed to provide improved switching capabilities (rise time and fall time for full range of target voltages and currents), the ability to scale the output voltage to a desired value with good accuracy (few percent) up to 10 kV, to cover a wide range of high-voltage applications. In addition, to ensure miniaturization, long life, and high reliability, the assemblies will require intensive high-voltage electrostatic modeling (optimized E-field distribution throughout the module) to complete the proposed packaging approach and test the applicability of using advanced materials in a space-like environment (temperature and pressure) to help prevent potential arcing and corona due to high field regions. Finally, a single-event effect evaluation would have to be performed and single-event mitigation methods implemented at the design and system level or developed to ensure complete radiation hardness of the module.

Adell, Philippe C.↗
NASA NTRS2012

Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

Duong, Tuan A.↗
NASA NTRS2012

Compact Autonomous Hemispheric Vision System

Solar System Exploration camera implementations to date have involved either single cameras with wide field-of-view (FOV) and consequently coarser spatial resolution, cameras on a movable mast, or single cameras necessitating rotation of the host vehicle to afford visibility outside a relatively narrow FOV. These cameras require detailed commanding from the ground or separate onboard computers to operate properly, and are incapable of making decisions based on image content that control pointing and downlink strategy. For color, a filter wheel having selectable positions was often added, which added moving parts, size, mass, power, and reduced reliability. A system was developed based on a general-purpose miniature visible-light camera using advanced CMOS (complementary metal oxide semiconductor) imager technology. The baseline camera has a 92 FOV and six cameras are arranged in an angled-up carousel fashion, with FOV overlaps such that the system has a 360 FOV (azimuth). A seventh camera, also with a FOV of 92 , is installed normal to the plane of the other 6 cameras giving the system a > 90 FOV in elevation and completing the hemispheric vision system. A central unit houses the common electronics box (CEB) controlling the system (power conversion, data processing, memory, and control software). Stereo is achieved by adding a second system on a baseline, and color is achieved by stacking two more systems (for a total of three, each system equipped with its own filter.) Two connectors on the bottom of the CEB provide a connection to a carrier (rover, spacecraft, balloon, etc.) for telemetry, commands, and power. This system has no moving parts. The system's onboard software (SW) supports autonomous operations such as pattern recognition and tracking.

Pingree, Paula J.↗
NASA NTRS2013

High-Speed, High-Resolution Time-to-Digital Conversion

This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

Katz, Richard↗
NASA NTRS2013

Millimeter-Wave Localizers for Aircraft-to-Aircraft Approach Navigation

Aerial refueling technology for both manned and unmanned aircraft is critical for operations where extended aircraft flight time is required. Existing refueling assets are typically manned aircraft, which couple to a second aircraft through the use of a refueling boom. Alignment and mating of the two aircraft continues to rely on human control with use of high-resolution cameras. With the recent advances in unmanned aircraft, it would be highly advantageous to remove/reduce human control from the refueling process, simplifying the amount of remote mission management and enabling new operational scenarios. Existing aerial refueling uses a camera, making it non-autonomous and prone to human error. Existing commercial localizer technology has proven robust and reliable, but not suited for aircraft-to-aircraft approaches like in aerial refueling scenarios since the resolution is too coarse (approximately one meter). A localizer approach system for aircraft-to-aircraft docking can be constructed using the same modulation with a millimeterwave carrier to provide high resolution. One technology used to remotely align commercial aircraft on approach to a runway are ILS (instrument landing systems). ILS have been in service within the U.S. for almost 50 years. In a commercial ILS, two partially overlapping beams of UHF (109 to 126 MHz) are broadcast from an antenna array so that their overlapping region defines the centerline of the runway. This is called a localizer system and is responsible for horizontal alignment of the approach. One beam is modulated with a 150-Hz tone, while the other with a 90-Hz tone. Through comparison of the modulation depths of both tones, an autopilot system aligns the approaching aircraft with the runway centerline. A similar system called a glide-slope (GS) exists in the 320-to-330MHz band for vertical alignment of the approach. While this technology has been proven reliable for millions of commercial flights annually, its UHF nature limits its ability to operate beyond the 1-to-2-meter precisions associated with commercial runway width. A prototype ILS-type system operates at millimeter-wave frequencies to provide automatic and robust approach control for aerial refueling. The system allows for the coupling process to remain completely autonomous, as a boom operator is no longer required. Operating beyond 100 GHz provides enough resolution and a narrow enough beamwidth that an approach corridor of centimeter scales can be maintained. Two modules were used to accomplish this task. The first module is a localizer/glide-slope module that can be fitted on a refueling aircraft. This module provides the navigation beams for aligning the approaching aircraft. The second module is navigational receiver fitted onto the approaching aircraft to be re fueled that can detect the approach beams. Since unmanned aircraft have a limited payload size and limited electrical power, the receiver portion was implemented in CMOS (complementary metal oxide semiconductor) technology based on a super-regenerative receiver (SRR) architecture. The SRR achieves mW-level power consumption and chip sizes less than l mm2. While super-regenerative techniques have small bandwidths that limit use in communication systems, their advantages of high sensitivity, low complexity, and low power make them ideal in this situation where modulating tones of less than 1 kHz are used.

Tang, Adrian J.↗
NASA NTRS2014

Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

We report low-energy proton and low-energy alpha particle single-event effects (SEE) data on a 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) latches and static random access memory (SRAM) that demonstrates the criticality of using low-energy protons for SEE testing of highly-scaled technologies. Low-energy protons produced a significantly higher fraction of multi-bit upsets relative to single-bit upsets when compared to similar alpha particle data. This difference highlights the importance of performing hardness assurance testing with protons that include energy distribution components below 2 megaelectron-volt. The importance of low-energy protons to system-level single-event performance is based on the technology under investigation as well as the target radiation environment.

random access memory↗
NASA NTRS2008

Radiation effects assessment of MRAM devices

The Magneto-resistive Random Access Memory (MRAM) from Freescale Semiconductor, MR2A16A, was subjected to heavy ion single event testing. Test results show that this device is sensitive to Single Event Latchup (SEL). The sensitivity of the MRAM was attributed to the complementary metal oxide semiconductor (CMOS) process in which the active portion of this device is constructed. Therefore, the device must be used with caution and may require mitigation techniques if used in a space environment. There was no indication that the MRAM technology itself, the memory element construction, is subject to damage from heavy ions.

McClure, Steve↗
NASA NTRSDate not supplied

Developing the Future of Gamma-ray Astrophysics with Monolithic Silicon Pixels

This paper explores the potential of AstroPix, a project to develop Complementary Metal Oxide Semiconductor (CMOS) pixels for the next generation of space-based high-energy astrophysics experiments. Multimessenger astrophysics is a rapidly developing field whose upcoming missions need support from new detector technology such as AstroPix. ATLASPix, a monolithic silicon detector optimized for the ATLAS particle detector at CERN, is the beginning of the larger AstroPix project. Energy resolution is a driving parameter in the reconstruction of gamma-ray events, and therefore the characterization of ATLASPix energy resolution is the focus of this paper. The intrinsic energy resolution of the detector exceeded our baseline requirements of 10% at 60 keV. The digital output of ATLASPix results in energy resolutions insufficient to advance gamma-ray astronomy. However, the results from the intrinsic energy resolution indicate the digital capability of the detector can be redesigned, and the next generation of pixels for the larger AstroPix project have already been constructed. Iterations of AstroPix-type pixels are an exciting new technology candidate to support new space-based missions.

Isabella Brewer↗
NASA NTRS1996

CMOS Active Pixel Sensors for Low Power, Highly Miniaturized Imaging Systems

The complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) technology has been developed over the past three years by NASA at the Jet Propulsion Laboratory, and has reached a level of performance comparable to CCDs with greatly increased functionality but at a very reduced power level.

CMOS complementary metal-oxide-semiconductor activ↗
NASA NTRS1979

CMOS circuit-fabrication handbook

Report describes complementary metal-oxide-semiconductor (CMOS) process used to fabricate integrated circuits at Marshall Space Flight Center. It also presents general discussions of circuit design, mask making packaging, and testing.

Bouldin, D. L.↗
DOE OSTI2024

Soft X-ray quantum efficiency of a commercial CMOS imaging sensor

The demonstrated performance and cost-effectiveness of complementary metal-oxide-semiconductor (CMOS) sensors make them a potentially attractive option for low-cost space-based X-ray observatories. We have previously reported on the performance of a commercially available backside-illuminated Sony IMX290LLR-C CMOS sensor and found it to offer X-ray spectral resolutions comparable to the charged coupled devices (CCDs) aboard Suzaku and Chandra and to have a sufficient radiation hardness for use in low Earth orbit. Here, in this work, we report on the quantum efficiency (QE) of this sensor, an essential metric for modeling the sensitivity of an instrument as an X-ray detector. Using the Advanced Photon Source at Argonne National Laboratory, we measure the soft X-ray QE of this CMOS sensor to be 0.28 ± 0.02 at a photon energy of 490.5 eV. This energy was chosen for its proximity to the astrophysically important O VII triplet emission lines (~574 eV) studied by the HaloSat mission. Although not surpassing that of the back-illuminated CCDs aboard Suzaku and Chandra, this QE compares favorably to that of the front-illuminated CCDs aboard the same observatories and is competitive with that of the silicon drift detectors used aboard HaloSat, making it a strong candidate for use on future X-ray small satellite (SmallSat) missions.

47 OTHER INSTRUMENTATION↗
NASA NTRS2003

Low-Power SOI CMOS Transceiver

The work aims at developing a low-power Silicon on Insulator Complementary Metal Oxide Semiconductor (SOI CMOS) Transceiver for deep-space communications. RF Receiver must accomplish the following tasks: (a) Select the desired radio channel and reject other radio signals, (b) Amplify the desired radio signal and translate them back to baseband, and (c) Detect and decode the information with Low BER. In order to minimize cost and achieve high level of integration, receiver architecture should use least number of external filters and passive components. It should also consume least amount of power to minimize battery cost, size, and weight. One of the most stringent requirements for deep-space communication is the low-power operation. Our study identified that two candidate architectures listed in the following meet these requirements: (1) Low-IF receiver, (2) Sub-sampling receiver. The low-IF receiver uses minimum number of external components. Compared to Zero-IF (Direct conversion) architecture, it has less severe offset and flicker noise problems. The Sub-sampling receiver amplifies the RF signal and samples it using track-and-hold Subsampling mixer. These architectures provide low-power solution for the short- range communications missions on Mars. Accomplishments to date include: (1) System-level design and simulation of a Double-Differential PSK receiver, (2) Implementation of Honeywell SOI CMOS process design kit (PDK) in Cadence design tools, (3) Design of test circuits to investigate relationships between layout techniques, geometry, and low-frequency noise in SOI CMOS, (4) Model development and verification of on-chip spiral inductors in SOI CMOS process, (5) Design/implementation of low-power low-noise amplifier (LNA) and mixer for low-IF receiver, and (6) Design/implementation of high-gain LNA for sub-sampling receiver. Our initial results show that substantial improvement in power consumption is achieved using SOI CMOS as compared to standard CMOS process. Potential advantages of SOI CMOS for deep-space communication electronics include: (1) Radiation hardness, (2) Low-power operation, and (3) System-on-Chip (SOC) solutions.

Fujikawa, Gene↗
NASA NTRS1995

JPL CMOS Active Pixel Sensor Technology

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

Space Microelectronics Image Sensors APS Digital I↗
NASA NTRS2010

Interim test status report for NEPP scaled CMOS

This document serves as the fiscal year end report for the NEPP scaled complementary metal-oxide semiconductor (CMOS) task. Much of the effort this year focused on development of test capability and initial collection of data on SDRAM devices. Since the system has only just begun (in the last four weeks) to gather data, this report focuses on the test system and preliminary results.

Guertin, Steven M.↗
NASA NTRS1985

Latchup in CMOS Integrated Circuits

Sensitivity to ion beams is studied. Latchup effect subject of paper presenting results of testing 19 types of complementary metal-oxide semiconductor (CMOS) chips from six manufacturers. Report gives details of sensitivity of chips to latchup caused by argon and krypton ion beams. Identifies parasitic npnp paths and proides latchup cross section and qualitative explanation of latchup sensitivity for each chip type.

Soliman, K. A.↗
NASA NTRS1984

Finding Open Faults In CMOS Circuits

Algorithm specifies sequence of input test signals and interpretation of resulting output signals for identifying stuck-open faults in complementary metal-oxide semiconductor (CMOS) integrated logic circuits. Incorporated in software for online production testing of CMOS circuits.

Chandramouli, R.↗