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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3

A microbenchmark characterization of the Emu chick

The Emu Chick is a prototype system designed around the concept of migratory memory-side processing. Rather than transferring large amounts of data across power-hungry, high-latency interconnects, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each memory read. The current prototype hardware uses FPGAs to implement cache-less “Gossamer” cores for computational work and rely on a typical stationary core (PowerPC) to run basic operating system functions and migrate threads between nodes. In this multi-node characterization of the Emu Chick, we extend an earlier single-node investigation of the the memory bandwidth characteristics of the system through benchmarks like STREAM, pointer chasing, and sparse matrix-vector multiplication. Here, we compare the Emu Chick hardware to architectural simulation and an Intel Xeon-based platform. Our results demonstrate that for many basic operations the Emu Chick can use available memory bandwidth more efficiently than a more traditional, cache-based architecture although bandwidth usage suffers for computationally intensive workloads like SpMV. Moreover, the Emu Chick provides stable, predictable performance with up to 65% of the peak bandwidth utilization on a random-access pointer chasing benchmark with weak locality.

97 MATHEMATICS AND COMPUTING↗

QCOR; A Language Extension Specification for the Heterogeneous Quantum-Classical Model of Computation

Quantum computing (QC) is an emerging computational paradigm that leverages the laws of quantum mechanics to perform elementary logic operations. Existing programming models for QC were designed with fault-tolerant hardware in mind, envisioning stand-alone applications. However, the susceptibility of near-term quantum computers to noise limits their stand-alone utility. To better leverage limited computational strengths of noisy quantum devices, hybrid algorithms have been suggested whereby quantum computers are used in tandem with their classical counterparts in a heterogeneous fashion. This modus operandi calls out for a programming model and a high-level programming language that natively and seamlessly supports heterogeneous quantum-classical hardware architectures in a single-source-code paradigm. Motivated by the lack of such a model, we introduce a language extension specification, called QCOR, which enables single-source quantum-classical programming. Programs written using the QCOR library–based language extensions can be compiled to produce functional hybrid binary executables. After defining QCOR’s programming model, memory model, and execution model, we discuss how QCOR enables variational, iterative, and feed-forward QC. Additionally, QCOR approaches quantum-classical computation in a hardware-agnostic heterogeneous fashion and strives to build on best practices of high-performance computing. The high level of abstraction in the language extension is intended to accelerate the adoption of QC by researchers familiar with classical high-performance computing.

97 MATHEMATICS AND COMPUTING↗

Workshop on Advanced Computing for Connected and Automated Vehicles

To safely and reliably operate without a human driver, connected and automated vehicles (CAVs) require more advanced computing hardware and software solutions than are implemented today in vehicles that provide driver-assistance features. A workshop was held to discuss advanced microelectronics and computing approaches that can help meet future energy and computational requirements for CAVs. Workshop questions were posed as follows: will highly automated vehicles be viable with conventional computing approaches or will they require a step-change in computing; what are the energy requirements to support on-board sensing and computing; and what advanced computing approaches could reduce the energy requirements while meeting their computational requirements? At present, there is no clear convergence in the computing architecture for highly automated vehicles. However, workshop participants generally agreed that there is a need to improve the computing performance per watt by at least 10x to advance the degree of automation. Participants suggested that DOE and the national laboratories could play a near-term role by developing benchmarks for determining and comparing CAV computing performance, developing public data sets to support algorithm and software development, and contributing precompetitive advancements in energy efficient computing.

33 ADVANCED PROPULSION SYSTEMS↗

Evaluating the Effects of Transient Purge Flow on Stator-Rotor Seal Performance

Abstract As modern engine designs target higher efficiencies through increased turbine inlet temperatures, critical turbine components are at increased risk of damage from conditions exceeding material melting temperatures. In particular, improperly designed underplatform hardware components are susceptible to damage when hot main gas path flow is ingested into the stator-rotor cavity. While all turbines inherently experience transients during operation, a majority of publicly available turbine studies have been executed using steady operating conditions or inherently transient “blowdown” rigs. For this reason, routine transient events are not well understood. To address this need, the present study utilized a combined experimental and computational approach. The test article is a continuous-duration, one-stage test turbine operating with true-scale engine hardware and seal geometries at engine-representative flow conditions. The nature of the continuous-duration facility uniquely supports the direct assessment of transient events through its ability to transition between steady-state operating conditions. The effects of a transient purge flow were investigated in this study to identify general trends for transient events in a full-scale engine. Results from multiple measurement techniques in the wheelspace region show an interdependence of transient purge flow with a thermal lag of the underplatform hardware. Through experiments conducted at different coolant-to-main gas path temperature ratios, the use of pressure measurements as an indicator of fully purged behavior was introduced, and a thermally driven influence on rim seal performance was quantified. The computational results show good agreement with experimental pressure measurements and provide insight into the physical mechanisms that drive the relationship between pressure and sealing effectiveness measurements observed for the tested geometry.

Engineering↗

Performance Characteristics of the BlueField-2 SmartNIC

High-performance computing (HPC) researchers have long envisioned scenarios where application workflows could be improved through the use of programmable processing elements embedded in the network fabric. Recently, vendors have introduced programmable Smart Network Interface Cards (SmartNICs) that enable computations to be offloaded to the edge of the network. There is great interest in both the HPC and high-performance data analytics (HPDA) communities in understanding the roles these devices may play in the data paths of upcoming systems. This paper focuses on characterizing both the networking and computing aspects of NVIDIA’s new BlueField-2 SmartNIC when used in a 100Gb/s Ethernet environment. For the networking evaluation we conducted multiple transfer experiments between processors located at the host, the SmartNIC, and a remote host. These tests illuminate how much effort is required to saturate the network and help estimate the processing headroom available on the SmartNIC during transfers. For the computing evaluation we used the stress-ng benchmark to compare the BlueField-2 to other servers and place realistic bounds on the types of offload operations that are appropriate for the hardware. Our findings from this work indicate that while the BlueField-2 provides a flexible means of processing data at the network’s edge, great care must be taken to not overwhelm the hardware. While the host can easily saturate the network link, the SmartNIC’s embedded processors may not have enough computing resources to sustain more than half the expected bandwidth when using kernel-space packet processing. From a computational perspective, encryption operations, memory operations under contention, and on-card IPC operations on the SmartNIC perform significantly better than the general-purpose servers used for comparisons in our experiments. Therefore, applications that mainly focus on these operations may be good candidates for offloading to the SmartNIC.

97 MATHEMATICS AND COMPUTING↗

Efficient Simulation of Open Quantum Systems on NISQ Trapped‐Ion Hardware

Abstract Simulating open quantum systems, which interact with external environments, presents significant challenges on noisy intermediate‐scale quantum (NISQ) devices due to limited qubit resources and noise. In this study, an efficient framework is proposed for simulating open quantum systems on NISQ hardware by leveraging a time‐perturbative Kraus operator representation of the system's dynamics. This approach avoids the computationally expensive Trotterization method and exploits the Lindblad master equation to represent time evolution in a compact form, particularly for systems satisfying specific commutation relations. The efficiency of this method is demonstrated by simulating quantum channels, such as the continuous‐time Pauli channel and damped harmonic oscillators, on NISQ trapped‐ion hardware, including IonQ Harmony and Quantinuum H1‐1. Additionally, hardware‐agnostic error mitigation techniques are introduced, including Pauli channel fitting and quantum depolarizing channel inversion, to enhance the fidelity of quantum simulations. These results show strong agreement between the simulations on real quantum hardware and exact solutions, highlighting the potential of Kraus‐based methods for scalable and accurate simulation of open quantum systems on NISQ devices. This framework opens pathways for simulating more complex systems under realistic conditions in the near term.

Burdine, Colin [Department of Electrical and Compu↗

Building an Integrated Ecosystem of Computational and Observational Facilities to Accelerate Scientific Discovery

Future scientific discoveries will rely on flexible ecosystems that incorporate modern scientific instruments, high performance computing resources, parallel distributed data storage, and performant networks across multiple, independent facilities. In addition to connecting physical resources, such an ecosystem presents many challenges in logistics and accessibility, especially in orchestrating computations and experiments that span across leadership computing systems and experimental instruments. Past efforts have typically been application-specific or limited to interfaces for computing resources. This paper proposes a general framework for integrating computation resources and instrument operations, addressing challenges in code development/execution, data staging and collection, software stack, control mechanisms, resource authorization and governance, and hardware integration. We also describe a demonstration use case wherein a Bayesian optimization algorithm running on an edge computing resource guides a scanning probe microscope to autonomously and intelligently characterize a material sample. This science edge ecosystem framework will provide a blueprint for federating multi-institutional, disparate resources and orchestrating scientific workflows across them to enable next-generation discoveries.

Somnath, Suhas↗

Improvement in the Accuracy of Flux Measurement of Radio Sources by Exploiting an Arithmetic Pattern in Photon Bunching Noise

A hierarchy of statistics of increasing sophistication and accuracy is proposed to exploit an interesting and fundamental arithmetic structure in the photon bunching noise of incoherent light of large photon occupation number, with the purpose of suppressing the noise and rendering a more reliable and unbiased measurement of the light intensity. The method does not require any new hardware, rather it operates at the software level with the help of high-precision computers to reprocess the intensity time series of the incident light to create a new series with smaller bunching noise coherence length. The ultimate accuracy improvement of this method of flux measurement is limited by the timing resolution of the detector and the photon occupation number of the beam (the higher the photon number the better the performance). The principal application is accuracy improvement in the signal-limited bolometric flux measurement of a radio source.

79 ASTRONOMY AND ASTROPHYSICS↗

CMOS-Based Single-Cycle in-Memory XOR/XNOR

Big data applications are on the rise, and so is the number of data centers. The ever-increasing massive data pool needs to be periodically backed up in a secure environment. Moreover, a massive amount of securely backed-up data is required for training binary convolutional neural networks for image classification. XOR and XNOR operations are essential for large-scale data copy verification, encryption, and classification algorithms. The disproportionate speed of existing compute and memory units makes the von Neumann architecture inefficient to perform these Boolean operations. Compute-in-memory (CiM) has proved to be an optimum approach for such bulk computations. The existing CiM-based XOR/XNOR techniques either require multiple cycles for computing or add to the complexity of the fabrication process. Here, we propose a CMOS-based hardware topology for single-cycle in-memory XOR/XNOR operations. Our design provides at least 2× improvement in the latency compared with other existing CMOS-compatible solutions. We verify the proposed system through circuit/system-level simulations and evaluate its robustness using a 5000-point Monte Carlo variation analysis. This all-CMOS design paves the way for practical implementation of CiM XOR/XNOR at scaled technology nodes.

97 MATHEMATICS AND COMPUTING↗

SUNDIALS time integrators for exascale applications with many independent systems of ordinary differential equations

Many complex systems can be accurately modeled as a set of coupled time-dependent partial differential equations (PDEs). However, solving such equations can be prohibitively expensive, easily taxing the world’s largest supercomputers. One pragmatic strategy for attacking such problems is to split the PDEs into components that can more easily be solved in isolation. This operator splitting approach is used ubiquitously across scientific domains, and in many cases leads to a set of ordinary differential equations (ODEs) that need to be solved as part of a larger “outer-loop” time-stepping approach. The SUNDIALS library provides a plethora of robust time integration algorithms for solving ODEs, and the U.S. Department of Energy Exascale Computing Project (ECP) has supported its extension to applications on exascale-capable computing hardware. In this paper, we highlight some SUNDIALS capabilities and its deployment in combustion and cosmology application codes (Pele and Nyx, respectively) where operator splitting gives rise to numerous, small ODE systems that must be solved concurrently.

97 MATHEMATICS AND COMPUTING↗

xesn: Echo state networks powered by Xarray and Dask

Xesn is a Python package that allows scientists to easily design Echo State Networks (ESNs) for forecasting problems. ESNs are a Recurrent Neural Network architecture introduced by Jaeger (2001) that are part of a class of techniques termed Reservoir Computing. One defining characteristic of these techniques is that all internal weights are determined by a handful of global, scalar parameters, thereby avoiding problems during backpropagation and reducing training time significantly. Because this architecture is conceptually simple, many scientists implement ESNs from scratch, leading to questions about computational performance. Xesn offers a straightforward, standard implementation of ESNs that operates efficiently on CPU and GPU hardware. The package leverages optimization tools to automate the parameter selection process, so that scientists can reduce the time finding a good architecture and focus on using ESNs for their domain application. Importantly, the package flexibly handles forecasting tasks for out-of-core, multi-dimensional datasets, eliminating the need to write parallel programming code. Xesn was initially developed to handle the problem of forecasting weather dynamics, and so it integrates naturally with Python packages that have become familiar to weather and climate scientists such as Xarray (Hoyer & Hamman, 2017). However, the software is ultimately general enough to be utilized in other domains where ESNs have been useful, such as in signal processing (Jaeger & Haas, 2004).

97 MATHEMATICS AND COMPUTING↗

Innovative Natural Gas Technologies For Efficiency Gain In Reliable And Affordable Thermochemical Electricity Generation (INTEGRATE)

Hyper is a cutting-edge system that pairs computational models that simulate the response of different systems with physical components such as sensors and actuators to transfer said calculated response to the HyPer facility. Computational models must operate in real-time in order to resolve the system response when coupled to physical hardware. Real-time is defined by the minimal HyPer system response time of Δt = 0.080 s. The integration of these models serves as a foundation for performance characterization based on real-world SOFC hardware and paves the way for comprehensive fuel flexibility studies. This report underscores the innovative approach to cyber-physical system deployment at NETL’s HyPer Facility, highlighting the critical role of computational models in enhancing the performance and adaptability of energy technologies.

03 NATURAL GAS↗

Generic Discretization Library

The GenDiL library is a collection of C++ software abstractions designed to discretize and solve partial differential equations (PDEs) for high-performance computing (HPC) applications. Its primary focus is on modern C++ generic programming, which helps ensure portability across various hardware architectures. The central idea behind the library is to provide building blocks for numerical algorithms-such as discretization methods and iteration patterns-so that domain experts can focus on the math, rather than the low-level details of hardware or implementation. By defining abstractions for data types, iteration over computational grids, and scheduling of operations, the library isolates the high-level PDE algorithms from the platform-specific optimizations needed to achieve efficient performance.

Dudouit, Yohann [Lawrence Livermore National Labor↗

A Benchmark Suite for Evaluating Scientific AI Workloads on GPUs

AI applications have been steadily increasing in the allocation portfolio among leadership computing facilities. These applications depend on deep learning frameworks with hardware acceleration and underlying software systems. With the rapid development of applications, software stacks, and hardware devices, it is essential to evaluate the performance of core operations in AI workloads for direction of optimizations and procurement of next-generation high-performance computing (HPC) infrastructures. Currently, most benchmarks lack scientific AI workloads. So, we present DeepKernelBench and the experimental results of evaluating the benchmark suite for early observations and performance comparisons on datacenter GPUs using representative workloads for scientific AI, including Attentions, General matrix multiplications, Geometrics and Fourier neural operations.

Jin, Zheming [Advanced Micro Devices (AMD)]↗

Designing FAIR Workflows at OLCF: Building Scalable and Reusable Ecosystems for HPC Science

High Performance Computing (HPC) centers, such as the Oak Ridge Leadership Computing Facility (OLCF), provide advanced infrastructure that enables scientific research at extreme scale. These centers operate with unique hardware configurations, specialized software environments, and elevated security re quirements that differ substantially from what most users encounter on their local systems. As a result, users often develop customized digital artifacts that are tightly coupled to the specific configuration of a given HPC center. Although necessary, this practice can lead to significant duplication of effort as multiple users independently create similar solutions to common problems.

97 MATHEMATICS AND COMPUTING↗

Glovebox Handling of High-Consequence Materials with Super Baxter and Gesture-Based Programming - 18598

The handling of high-consequence materials is a difficult task requiring safe object manipulation while avoiding the risk of contamination or spillage. Specific operations including opening containers, segregating the wastes, and repackaging are required to be safely executed inside contained spaces such as gloveboxes. However, the workers' ability and dexterity to manipulate objects through thick protective gloves are compromised in many aspects. The fixed position of the glovebox arm ports restricts the movements of the workers' arms, which also makes it hard to lift heavy objects. Further, the operational workspace inside the glovebox is restricted by the gloves' reachability. Safety of workers is the paramount concern in glovebox operations and the very reason for their existence. Sharp edges and tools increases the risk of glove punctures, which may expose the operator to chemicals and radiation and risks contamination in the vicinity outside the glovebox. The operators are also affected by ergonomic stressors due to prolonged and repetitive operations. To achieve a high degree of human safety, robotic solutions to handle high-consequence materials inside the glovebox are desirable, as they remove the operators from the hazards listed above. However, robots, in general, lack the degree of adaptability necessary for most high-consequence material handling tasks as these tasks are often unstructured or highly variable. Likewise, most human operators, while highly skilled in the tasks at hand (task expertise), lack the robot programming skills necessary to adapt the robot's motions to the variations (programming expertise). A way to bridge this divide is to make robot programming more intuitive to human operators. Since humans naturally teach one another through demonstration and learning, robotic 'programming by demonstration' paradigms have begun to appear to reduce the burden of robot reprogramming. Gesture-Based Programming attempts to achieve that by enabling a robot to observe the normal actions and affordances of a human performing a task to learn to map those onto the skills of the robot. In the end, this approach permits benefits from both the human and the robot: the human's adaptive decision making and the robot's resilience to high-consequence material. Robotic solutions assuringly provide protection for the operators, however their autonomy brings about other potential risks. Artificial Intelligence is not perfect; it is a black box, which can produce results, but the full extent of those results may not be known precisely. In self-driving cars, a hypothetical AI problem is the 'green man detector'. Since self-driving cars have presumably never seen a green man, how can we know it won't veer toward him the first time it sees a green man? Likewise, even though GbP provides an open method for safe task execution replicating a human, incorrect task inferences can lead to potential collisions or unintended operations. Thus, a hardware safety measure is proposed to provide reliable operation inside the glovebox, and true safe operations are achieved by mechanically limiting the operational range of each arm link. The operational range is computed and validated through exhaustive offline simulations, which can be streamlined by affordable computing power. Super Baxter is one such robot which incorporates these capabilities. It is a human-like, bimanual robot, being developed at the Collaborative Robotics Lab (CRL) in conjunction with the Dept. of Energy/Environmental Management, Rethink Robotics, Barrett Technology, and the NSF Center for Robots and Sensors for the Human Well-Being (RoSe-HUB). Super Baxter is envisioned to represent the next generation of collaborative robots that will be intrinsically human-safe, as well as exceptionally human-intuitive. In summary, Super Baxter will enable safe glovebox operations through low-shot Gesture based Programming incorporated with hardware safety measures. Two aspects of safety will be discussed in the paper. First, the safety of the operator achieved by allowing him to program Super Baxter remotely through Gesture based Programming. Second, the safety of the glovebox, achieved by incorporating hardware safety measures using joint limits. Further, the capability of Super Baxter on Gesture based Programming is demonstrated through typical object manipulation tasks in glovebox operations. (authors)

42 ENGINEERING↗

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

42 ENGINEERING↗

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Asaad, Sameh W.↗