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At least 55 records · Page 3

Single phase dynamic CMOS PLA using charge sharing technique

A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic CMOS NOR structure, a cascading AND gate can be implemented. The proposed PLA's are presented with a delay-time of 15.95 and 18.05 nsec, respectively, which compare with a conventional single phase PLA with 35.5 nsec delay-time. For a typical example of PLA like the Signetics 82S100 with 16 inputs, 48 input minterms (m) and 8 output minterms (n), the 2-SOP PLA using the triggered 2-bit decoder is 2.23 times faster and has 2.1 times less power dissipation than the conventional PLA. These results are simulated using maximum drain current of 600 micro-A, gate length of 2.0 micron, V sub DD of 5 V, the capacitance of an input miniterm of 1600 fF, and the capacitance of an output minterm of 1500 fF.

Dhong, Y. B.↗

Maximum aposteriori joint source/channel coding

A maximum aposteriori probability (MAP) approach to joint source/channel coder design is presented in this paper. This method attempts to explore a technique for designing joint source/channel codes, rather than ways of distributing bits between source coders and channel coders. For a nonideal source coder, MAP arguments are used to design a decoder which takes advantage of redundancy in the source coder output to perform error correction. Once the decoder is obtained, it is analyzed with the purpose of obtaining 'desirable properties' of the channel input sequence for improving overall system performance. Finally, an encoder design which incorporates these properties is proposed.

Sayood, Khalid↗

A high-speed lossless data compression system for space applications

This paper reports on the integration of a lossless data compression/decompression chipset into a space data system architecture. For its compression engine, the data system incorporates the Universal Source Encoder (USE) designed for the NASA/Goddard Space Flight Center. Currently, the data compression testbed generates video frames consisting of 512 lines of 512 pixels having 8-bit resolution. Each image is passed through the USE where the lines are internally partitioned into 16-word blocks. These blocks are adaptively encoded across widely varying entropy levels using a Rice 12-option set coding algorithm. The current system operates at an Input/Output rate of 10 Msamples/s or 80 Mbits/s for each buffered input line. Frame and line synchronization for each image are maintained through the use of uniquely decodable command words. Length information of each variable length compressed image line is also included in the output stream. The data and command information are passed to the next stage of the system architecture through a serial fiber-optic transmitter. The initial segment of this stage consists of packetizer hardware which adds an appropriate CCSDS header to the received source data. An uncompressed mode is optionally available to pass image lines directly to the packetizer hardware. A data decompression testbed has also been developed to confirm the data compression operation.

Miko, Joe↗

Airoscope command system

A PCM telemetry command system is presented having a capacity of 256 unique commands, an end-to-end actuation time of less than 250 milliseconds, and an address plus complementary command code to provide security against the acceptance of anything but intended commands. The system consists of a ground-based encoder and a balloon-borne decoder, both built using low-current drain, high reliability CMOS logic elements. Commands are normally issued by a simple switch closure to +5VDC on the appropriate input line, however as a backup mode, the 8-bit command may be entered manually on 8 toggle switches and executed via a SEND button. In any case, the command is then serialized into a PCM bit stream and sent via a P-Band radio link to the DECODER aloft. All 256 outputs from the DECODER are buffered through drivers and thus may be used to drive CMOS, TTL, or DTL logic.

Barrows, W.↗

Big Viterbi Decoder (BVD) results for (7,1/2) convolutional code

The Big Viterbi Decoder (BVD), capable of decoding convolutional codes with constraint lengths of up to 15, is under development for the Deep Space Network (DSN). As part of the development, a commercial single-chip (7,1/2) Viterbi decoder is used to enable early start of system integration. Tests of the integrated partial system (including simulator, input systems, output interfaces, and computer controls) were recently completed at the DSN Compatibility Test Area (CTA-21) at JPL. The system elements used for the demonstration and test results are described.

Statman, J.↗

Node synchronization schemes for the Big Viterbi Decoder

The Big Viterbi Decoder (BVD), currently under development for the DSN, includes three separate algorithms to acquire and maintain node and frame synchronization. The first measures the number of decoded bits between two consecutive renormalization operations (renorm rate), the second detects the presence of the frame marker in the decoded bit stream (bit correlation), while the third searches for an encoded version of the frame marker in the encoded input stream (symbol correlation). A detailed account of the operation is given, as well as performance comparison, of the three methods.

Cheung, K.-M.↗

A programmable microcomputer for real time speech processing

The implementation of a programmable microprocessor for real time speech processing is described. The design of a fast special-purpose computer operating at 150 nsec per instruction time reduces the problem of speech encoding and decoding to a software problem. Each instruction is a twelve-bit word, and the information conveyed by a word is explained. The microprocessor is controlled by two clocks - the A/D clock, or input sampling clock, which loads the digital input into the input register and presets the counter to a value set by the external switches; and the instruction clock, or system clock, which operates at 6 MHz. At this system clock rate and a sampling clock rate of 30 KHz, 200 instructions can be executed between samples, and for many speech encoding and decoding algorithms, 200 instructions are more than enough. The microcomputer is being used to test various delta modulator encoding algorithms.

Apelewicz, T.↗

Bandwidth efficient trellis-coded modulation with prescribed decoding delay - new interpretations and results

Motivated by previous work of Li and Rimoldi for obtaining bandwidth efficient TCM signals with finite decoding delay, we present an alternative representation for their encoder/signal mapper transmitter structure which merely consists of a single filter having an input equal to the equivalent of the inoput data bits in their implementation.

trellis coding bandwidth efficient modulation digi↗

Microprocessor control for phase-lock receiver

Subsystem facilities flexible data acquisition by combining hardware and software processing. Device controls complex signal acquisition sequence and assists in precise phase locking to received signal. Key features include software system and code-generator initialization routines, executive routine, utility subroutines, control sequence routines for each receiver acquisition state, control-command decoding routine, and look-up tables for code-generator configuration versus code-set number. Steps can be added to extend input signal dynamic range.

Carson, L. M.↗

Robust incoherent fiber optic bundle decoder

Apparatus and method for calibrating an incoherent fiber optic bundle for use in transmitting visual or infrared coherent images. The apparatus includes a computer, a computer video monitor, an objective lens adjacent to the input end of the bundle, a second lens adjacent the output end of the bundle, and a CCD camera. The camera transmits video data to the monitor to produce an illuminated fiber optic image. The coordinates for the center of each fiber is found through an imaging process and the output fibers coordinates are related to the input fiber coordinates and processed in the computer to produce a mapping lookup-table (LUT) unique to the specific fiber bundle. Remapping of the LUT due to changes in the lens focus, CCD camera, or the addition of an infrared filter is accomplished by a software utility in the computer.

Roberts, Hilary E.↗

Information-reduced Carrier Synchronization of Iterative Decoded BPSK and QPSK using Soft Decision (Extrinsic) Feedback

This paper addresses the carrier-phase estimation problem under low SNR conditions as are typical of turbo- and LDPC-coded applications. In previous publications by the first author, closed-loop carrier synchronization schemes for error-correction coded BPSK and QPSK modulation were proposed that were based on feeding back hard data decisions at the input of the loop, the purpose being to remove the modulation prior to attempting to track the carrier phase as opposed to the more conventional decision-feedback schemes that incorporate such feedback inside the loop. In this paper, we consider an alternative approach wherein the extrinsic soft information from the iterative decoder of turbo or LDPC codes is instead used as the feedback.

carrier synchronization↗

Gain-adaptive vector quantization for medium-rate speech coding

A class of adaptive vector quantizers (VQs) that can dynamically adjust the 'gain' of codevectors according to the input signal level is introduced. The encoder uses a gain estimator to determine a suitable normalization of each input vector prior to VQ coding. The normalized vectors have reduced dynamic range and can then be more efficiently coded. At the receiver, the VQ decoder output is multiplied by the estimated gain. Both forward and backward adaptation are considered and several different gain estimators are compared and evaluated. An approach to optimizing the design of gain estimators is introduced. Some of the more obvious techniques for achieving gain adaptation are substantially less effective than the use of optimized gain estimators. A novel design technique that is needed to generate the appropriate gain-normalized codebook for the vector quantizer is introduced. Experimental results show that a significant gain in segmental SNR can be obtained over nonadaptive VQ with a negligible increase in complexity.

Chen, J.-H.↗

Frequency-Accommodating Manchester Decoder

No adjustment necessary to cover a 10:1 frequency range. Decoding circuit converts biphase-level pulse-code modulation to nonreturn-to-zero (NRZ)-level pulse-code modulation plus clock signal. Circuit accommodates input data rate of 50 to 500 kb/s. Tracks gradual changes in rate automatically, eliminating need for extra circuits and manual switching to adjust to different rates.

Vasquez, Mario J.↗

Vector adaptive predictive coder for speech and audio

A real-time vector adaptive predictive coder which approximates each vector of K speech samples by using each of M fixed vectors in a first codebook to excite a time-varying synthesis filter and picking the vector that minimizes distortion. Predictive analysis for each frame determines parameters used for computing from vectors in the first codebook zero-state response vectors that are stored at the same address (index) in a second codebook. Encoding of input speech vectors s.sub.n is then carried out using the second codebook. When the vector that minimizes distortion is found, its index is transmitted to a decoder which has a codebook identical to the first codebook of the decoder. There the index is used to read out a vector that is used to synthesize an output speech vector s.sub.n. The parameters used in the encoder are quantized, for example by using a table, and the indices are transmitted to the decoder where they are decoded to specify transfer characteristics of filters used in producing the vector s.sub.n from the receiver codebook vector selected by the vector index transmitted.

Chen, Juin-Hwey↗

Rate-Compatible LDPC Codes with Linear Minimum Distance

A recently developed method of constructing protograph-based low-density parity-check (LDPC) codes provides for low iterative decoding thresholds and minimum distances proportional to block sizes, and can be used for various code rates. A code constructed by this method can have either fixed input block size or fixed output block size and, in either case, provides rate compatibility. The method comprises two submethods: one for fixed input block size and one for fixed output block size. The first mentioned submethod is useful for applications in which there are requirements for rate-compatible codes that have fixed input block sizes. These are codes in which only the numbers of parity bits are allowed to vary. The fixed-output-blocksize submethod is useful for applications in which framing constraints are imposed on the physical layers of affected communication systems. An example of such a system is one that conforms to one of many new wireless-communication standards that involve the use of orthogonal frequency-division modulation

Divsalar, Dariush↗

Optical Communications Channel Combiner

NASA has identified deep-space optical communications links as an integral part of a unified space communication network in order to provide data rates in excess of 100 Mb/s. The distances and limited power inherent in a deep-space optical downlink necessitate the use of photon-counting detectors and a power-efficient modulation such as pulse position modulation (PPM). For the output of each photodetector, whether from a separate telescope or a portion of the detection area, a communication receiver estimates a log-likelihood ratio for each PPM slot. To realize the full effective aperture of these receivers, their outputs must be combined prior to information decoding. A channel combiner was developed to synchronize the log-likelihood ratio (LLR) sequences of multiple receivers, and then combines these into a single LLR sequence for information decoding. The channel combiner synchronizes the LLR sequences of up to three receivers and then combines these into a single LLR sequence for output. The channel combiner has three channel inputs, each of which takes as input a sequence of four-bit LLRs for each PPM slot in a codeword via a XAUI 10 Gb/s quad optical fiber interface. The cross-correlation between the channels LLR time series are calculated and used to synchronize the sequences prior to combining. The output of the channel combiner is a sequence of four-bit LLRs for each PPM slot in a codeword via a XAUI 10 Gb/s quad optical fiber interface. The unit is controlled through a 1 Gb/s Ethernet UDP/IP interface. A deep-space optical communication link has not yet been demonstrated. This ground-station channel combiner was developed to demonstrate this capability and is unique in its ability to process such a signal.

Quirk, Kevin J.↗