Behavioral Emulation Methodology for Fast Design Space Exploration.
Abstract not provided.
Kumar, Nalini↗
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Results for “Design Space Exploration”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Computer Architecture Laboratory for Design Space Exploration: CAL Goals and Objectives.
Abstract not provided.
Ang, James A↗
Design Space Exploration with Proxy/Proto Architecture Models and miniApps.
Abstract not provided.
Ang, James A↗
Design Space Exploration with Proxy/Proto Architecture Models and miniApps.
Abstract not provided.
Ang, James A↗
Unsupervised Neural Network Adaptation at the Edge: A Design Space Exploration
Explore the source record for details and available documents.
Computer science↗
Adrastea: An Efficient FPGA Design Environment for Heterogeneous Scientific Computing and Machine Learning
We present Adrastea, an efficient FPGA design environment for developing scientific machine learning applications. FPGA development is challenging, from deployment, proper toolchain setup, programming methods, interfacing FPGA kernels, and more importantly, the need to explore design space choices to get the best performance and area usage from the FPGA kernel design. Adrastea provides an automated and scalable design flow to parameterize, implement, and optimize complex FPGA kernels and associated interfaces. We show how virtualization of the development environment via virtual machines is leveraged to simplify the setup of the FPGA toolchain while deploying the FPGA boards and while scaling up the automated design space exploration to leverage multiple machines concurrently. Adrastea provides an automated build and test environment of FPGA kernels. By exposing design space hyper-parameters, Adrastea can automatically search the design space in parallel to optimize the FPGA design for a given metric, usually performance or area. Adrastea simplifies the task of interfacing with the FPGA kernels with a simplified interface API. To demonstrate the capabilities of Adrastea, we implement a complex random forest machine learning kernel with 10,000 input features while achieving extremely low computing latency without loss of prediction accuracy, which is required by a scientific edge application at SNS. We also demonstrate Adrastea using an FFT kernel and show that for both applications Adrastea is able to systematically and efficiently evaluate different design options, which reduced the time and effort required to develop the kernel from months of manual work to days of automatic builds.
Young, Aaron↗
Scientific instruments in space exploration.
Design of instrumentation to meet requirements of space exploration, centering discussion around mariner ii
MARINER II SPACE PROBE↗
Model-Based Engineering Design for Trade Space Exploration throughout the Design Cycle
This paper presents ongoing work to standardize model-based system engineering as a complement to point design development in the conceptual design phase of deep space missions. It summarizes two first steps towards practical application of this capability within the framework of concurrent engineering design teams and their customers. The first step is standard generation of system sensitivities models as the output of concurrent engineering design sessions, representing the local trade space around a point design. A review of the chosen model development process, and the results of three case study examples, demonstrate that a simple update to the concurrent engineering design process can easily capture sensitivities to key requirements. It can serve as a valuable tool to analyze design drivers and uncover breakpoints in the design. The second step is development of rough-order- of-magnitude, broad-range-of-validity design models for rapid exploration of the trade space, before selection of a point design. At least one case study demonstrated the feasibility to generate such models in a concurrent engineering session. The experiment indicated that such a capability could yield valid system-level conclusions for a trade space composed of understood elements. Ongoing efforts are assessing the practicality of developing end-to-end system-level design models for use before even convening the first concurrent engineering session, starting with modeling an end-to-end Mars architecture.
models↗
Co-design of Advanced Architectures for Graph Analytics using Machine Learning
A graph is an excellent way of representing relationships among entities. We can use graph analytics to synthesize and analyze such relational data, and extract relevant features that are useful for various tasks such as machine learning. Considering the crucial role of graph analytics in various domains, it is important and timely to investigate the right hardware configurations that can achieve optimal performance for graph workloads on future high-performance computing systems. Design space exploration studies facilitate the selection of appropriate configurations (e.g. memory) to achieve a desired system performance. Recently, the approach of accelerating graph analytics using persistent non-volatile memory has gained a lot of attention. Traditional system simulators such as Gem5 and NVMain can be used to explore the design space of these advanced memory architectures for graph workloads. However, these simulators are slow in execution thus limiting the efficiency of design space exploration studies. To overcome this challenge, we proposed a machine learning based approach to co-design advanced memory architectures for graph workloads. We tested our approach with DRAM, non-volatile memory, and hybrid memory (DRAM+NVM) using a breadth first search benchmark algorithm. Our results showed the applicability of the proposed machine learning based approach to the co-design of the advanced memory architectures. In this paper, we provide recommendations on selecting advanced memory architectures to achieve desired performance for graph workloads. We also discuss the performances of different machine learning models that were considered in this study.
Kurte, Kuldeep↗
LENS: Learning Enabled Network Synthesis
RTRC and UMD have developed novel machine learning based methods under the ARPA-E DIFFERENTIATE program for rapid acceleration of hypothesis generation in complex architecture design spaces involving both discrete choices of component inclusion and interconnection and continuous parametric decisions. The project named Learning Enabled Network Synthesis (LENS) further demonstrated the developed methods on challenging electrical power converter design problems by identifying the most suitable circuit topologies and simultaneously selecting the most appropriate components to achieve optimized design of power converter with improved performances. We demonstrated that LENS could enable exploration of very large design space of circuit topologies and components by addressing the limitations of conventional design process in non-linear, high switching speed, multi-dimensional power converter design and optimization. The key innovation developed in LENS is the seamless integration of statistical learning and logical reasoning techniques and building on the individual strengths of these techniques for rapid hypothesis discovery. The main component of LENS comprises of: 1) Graph Reasoning Engine (GRE) to enforce composition rules that rapidly reject all discrete architectures that are composed incorrectly and generates an adaptive database of feasible designs which can be used by ML modules, 2) Graph Generative Learning module which is a deep neural network based generative model for graph architectures which can enable design space exploration beyond the dataset generated by the GRE, 3) Graph Reduced Order Model (ROM) for graph domains for accelerating computation of output metrics, and 4) Active learning and Rule Discovery module for sample efficient learning and extracting logical rules from the learned ML models which will be integrated in the GRE to enhance the filtering effectiveness. LENS approach can be applied to any design domains where designs can be represented as multi-attribute graphs. The LENS team integrated the various technical innovations listed above into an optimization pipeline and exercised the optimization pipeline on the converter design problem. The LENS project demonstrated that the developed AI/ML technologies can be used to generate novel converter circuits >45x faster than experts on chosen use-cases. This can enable faster design space exploration and identification of new designs which are not considered by experts due to the increasing design space complexity. This has significant potential impact on the public and energy needs of the country. It is currently estimated that 30% of all electrical powers generated passes through power converters. The future estimate is that 80% of all power generated would be passing through converters. LENS fills a critical gap in this space since by accelerating the design process the designers would be able to generate more efficient converters which can lead to significant energy savings for the country.
42 ENGINEERING↗
Continued Exploration of the Electrified Aircraft Propulsion Design Space
A previous electrified aircraft propulsion (EAP) design space exploration study was continued to investigate the impact of mission constraints, further explore the design space of different sized aircraft, and improve the modeling process. Three aircraft were investigated, 18- and 48-passenger turboprops, and a 78-passenger turbofan. Baseline aircraft models were inherited from the earlier study and were hybridized by applying EAP technologies. A parametric study varying motor power and battery specific energy was conducted. For the 78-passenger turbofan, design range was also introduced as a parametric parameter. Key metrics for the study included equivalent lifecycle CO2 emissions and direct operating cost plus interest. Both turboprop aircraft demonstrated significant potential savings in block fuel consumption and CO2 emissions, but at increased operating costs compared to their baseline models. As the 78-passenger turbofan had shown no improvements in any metrics under reasonable technology assumptions, design range was shortened in an attempt to obtain performance benefits. When designed for a shorter range, the 78-passenger EAP vehicle showed potential improvements in block fuel when compared to a baseline with a similarly shortened design range, but not in any other metrics. Operating cost reductions were not achieved for any aircraft, but several designs came close to breaking even with their baselines. Smaller, shorter range aircraft and turboprops demonstrated larger performance benefits and smaller operating cost penalties, but a simple trade of electric energy storage in batteries for fuel is generally insufficient to produce a viable aircraft concept.
Electrified Aircraft Propulsion↗
A Multi-Disciplinary Analysis Framework for the Design of Small Launch Vehicles
The decisions made in the conceptual design phase have large impacts on the resulting vehicle capability and cost. With the large and varied design space of Small Launch Vehicles(SLVs), it is even more important to have the data necessary to make informed design choices during the conceptual design phase. To enable extensive exploration of the SLV design space, a multi-disciplinary design framework was created. The design framework consists of trajectory, aerodynamics, propulsion, and structures disciplines. The framework then integrates and automates these tools, thus allowing for rapid design space exploration at the conceptual design phase. The outputs of the framework provide preliminary information on SLV size and structural configurations as well as propulsion and aerodynamic characteristics. Finally, the framework provides information necessary for the designer to make informed decisions on what variables lead to the desired performance characteristics and what segment of the design space would benefit from more detailed exploration.
Nikita Birbasov↗
Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems
Summary of technical results of Blackcomb Memory Devices We explored various different memory technologies (STTRAM, PCRAM, FeRAM, and ReRAM). The progress can be classified into three categories, below. Modeling and Tool Releases Various modeling tools have been developed over the last decade to help in the design of SRAM or DRAM-based memory hierarchies. To explore new design opportunities that NVM technologies can bring to the designers, we have developed similar high-level models for NVM, including PCRAMsim [Dong 2009], NVSim [Dong 2012], and NVMain [Poremba 2012]. NVSim is a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies. On the other side, NVMain is a cycle accurate main memory simulator designed to simulate emerging nonvolatile memories at the architectural level. We have released these models as open source tools and provided contiguous support to them. We also proposed PS3-RAM, which is a fast, portable and scalable statistical STT-RAM reliability analysis model [Wen 2012]. Design Space Exploration and Optimization With the support of these models, we explore different device/circuit optimization techniques. For example, in [Niu 2012a] we studied the power reduction technique for the application of ECC scheme in ReRAM designs and proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both 1T1R and cross-point ReRAM designs. In [Xu 2011], we proposed a methodology to design STT-RAM for different optimization goals such as read performance, write performance and write energy by leveraging the trade-off between write current and write time of MTJ. We also studied the tradeoffs in building a reliable crosspoint ReRAM array [Niu 2012b]. We have conducted an in depth analysis of the circuit and system level design implications of multi-layer cross-point Resistive RAM (MLCReRAM) from performance, power and reliability perspectives [Xu 2013]. The objective of this study is to understand the design trade-offs of this technology with respect to the MLC Phase Change Memory (MLCPCM).Our MLC ReRAM design at the circuit and system levels indicates that different resistance allocation schemes, programming strategies, peripheral designs, and material selections profoundly affect the area, latency, power, and reliability of MLC ReRAM. Based on this analysis, we conduct two case studies: first we compare MLC ReRAM design against MLC phase-change memory (PCM) and multi-layer cross-point ReRAM design, and point out why multi-level ReRAM is appealing; second we further explore the design space for MLC ReRAM. Architecture and Application We explored hybrid checkpointing using phase-change memory for future exascale systems [Dong 2011] and showed that the use of nonvolatile memory for local checkpointing significantly increases the number of faults covered by local checkpoints and reduces the probability of a global failure in the middle of a global checkpoint to less than 1%. We also proposed a technique called i2WAP to mitigate the write variations in NVM-based last-level cache for the improvement of the NVM lifetime [Wang 2013]. Our wear leveling technique attempts to work around the limitations of write endurance by arranging data access so that write operations can be distributed evenly across all the storage cells. During our intensive research on fault-tolerant NVM design, we found that ECC cannot effectively tolerate hard errors from limited write endurance and process imperfection. Therefore, we devised a novel Point and Discard (PAD) architecture in in [ 2012] as a hard-error-tolerant architecture for ReRAM-based Last Level Caches. PAD improves the lifetime of ReRAM caches by 1.6X-440X under different process variations without performance overhead in the system's early life. We have investigated the applicability of NVM for persistent memory design [Zhao 2013]. New byte addressable NVM enables fast persistent memory that allows in-memory persistent data objects to be updated with much higher throughput. Despite the significant improvement, the performance of these designs is only 50% of the native system with no persistence support, due to the logging or copy-on-write mechanisms used to update the persistent memory. A challenge in this approach is therefore how to efficiently enable atomic, consistent, and durable updates to ensure data persistence that survives application and/or system failures. We have designed a persistent memory system, called Klin, that can provide performance as close as that of the native system. The Klin design adopts a non-volatile cache and a non-volatile main memory for constructing a multi-versioned durable memory system, enabling atomic updates without logging or copy-on-write. Our evaluation shows that the proposed Kiln mechanism can achieve up to 2X of performance improvement to NVRAM-based persistent memory employing write-ahead logging. In addition, our design has numerous practical advantages: a simple and intuitive abstract interface, microarchitecture-level optimizations, fast recovery from failures, and no redundant writes to slow non-volatile storage media. The work was published in MICRO 2013 and received Best Paper Honorable Mentioned Award.
97 MATHEMATICS AND COMPUTING↗
Enabling parallel simulation of large-scale HPC network systems
Here, with the increasing complexity of today’s high-performance computing (HPC) architectures, simulation has become an indispensable tool for exploring the design space of HPC systems—in particular, networks. In order to make effective design decisions, simulations of these systems must possess the following properties: (1) have high accuracy and fidelity, (2) produce results in a timely manner, and (3) be able to analyze a broad range of network workloads. Most state-of-the-art HPC network simulation frameworks, however, are constrained in one or more of these areas. In this work, we present a simulation framework for modeling two important classes of networks used in today’s IBM and Cray supercomputers: torus and dragonfly networks. We use the Co-Design of Multi-layer Exascale Storage Architecture (CODES) simulation framework to simulate these network topologies at a flit-level detail using the Rensselaer Optimistic Simulation System (ROSS) for parallel discrete-event simulation. Our simulation framework meets all the requirements of a practical network simulation and can assist network designers in design space exploration. First, it uses validated and detailed flit-level network models to provide an accurate and high-fidelity network simulation. Second, instead of relying on serial time-stepped or traditional conservative discrete-event simulations that limit simulation scalability and efficiency, we use the optimistic event-scheduling capability of ROSS to achieve efficient and scalable HPC network simulations on today’s high-performance cluster systems. Third, our models give network designers a choice in simulating a broad range of network workloads, including HPC application workloads using detailed network traces, an ability that is rarely offered in parallel with high-fidelity network simulations
97 MATHEMATICS AND COMPUTING↗
QASMTrans: A QASM Quantum Transpiler Framework for NISQ Devices
In quantum computing, transpilation plays a crucial role in converting high-level, machine-independent quantum circuits into circuits specially for a quantum device, considering factors such as basis gate set, topology, error profile, etc. Yet, the efficiency of transpilation remains a significant bottleneck, particularly when dealing with very large QASM level input files. In this paper, we present QASMTrans, a C++ based high-performance quantum transpiler framework that can demonstrate on average 50-100× speedups compared to the internal transpiler of Qiskit. Particularly, for large dense circuits such as ’uccsd n24’ and ’qft n320’ incorporating millions of gates, QASMTrans can successfully transpile in 69s and 31s, respectively, while Qiskit failed to finish in one hour. Using QASMTrans as the baseline, it becomes more feasible to explore much larger design space and impose more comprehensive compiler optimizations.
Hua, Fei↗
Baseline antenna design for space exploration initiative
A key element of the future NASA Space Exploration Initiative (SEI) mission is the lunar and Mars telecommunication system. This system will provide voice, image, and data transmission to monitor unmanned missions to conduct experiments, and to provide radiometric data for navigation. In the later half of 1991, a study was conducted on antennas for the Mars Exploration Communication. Six antenna configurations were examined: three reflector and three phased array. The conclusion was that due to wide-angle scan requirement, and multiple simultaneous tracking beams, phased arrays are more suitable. For most part, this report studies phased array antenna designs for two different applications for Space Exploration Initiative. It also studies one design for a tri-reflector type antenna. These antennas will be based on a Mars orbiting satellite.
Chen, Y. L.↗