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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

Testing interconnected VLSI circuits in the Big Viterbi Decoder

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Onyszchuk, I. M.↗
NASA NTRS1998

An emerging network storage management standard: Media error monitoring and reporting information (MEMRI) - to determine optical tape data integrity

Sophisticated network storage management applications are rapidly evolving to satisfy a market demand for highly reliable data storage systems with large data storage capacities and performance requirements. To preserve a high degree of data integrity, these applications must rely on intelligent data storage devices that can provide reliable indicators of data degradation. Error correction activity generally occurs within storage devices without notification to the host. Early indicators of degradation and media error monitoring 333 and reporting (MEMR) techniques implemented in data storage devices allow network storage management applications to notify system administrators of these events and to take appropriate corrective actions before catastrophic errors occur. Although MEMR techniques have been implemented in data storage devices for many years, until 1996 no MEMR standards existed. In 1996 the American National Standards Institute (ANSI) approved the only known (world-wide) industry standard specifying MEMR techniques to verify stored data on optical disks. This industry standard was developed under the auspices of the Association for Information and Image Management (AIIM). A recently formed AIIM Optical Tape Subcommittee initiated the development of another data integrity standard specifying a set of media error monitoring tools and media error monitoring information (MEMRI) to verify stored data on optical tape media. This paper discusses the need for intelligent storage devices that can provide data integrity metadata, the content of the existing data integrity standard for optical disks, and the content of the MEMRI standard being developed by the AIIM Optical Tape Subcommittee.

Podio, Fernando↗
NASA NTRS1982

Study of and proposals for the correction of errors in a radar ranging device designed to facilitate docking of a teleoperator maneuvering system

A frequency modulated continuous wave radar system was developed. The system operates in the 35 gigahertz frequency range and provides millimeter accuracy range and range rate measurements. This level of range resolution allows soft docking for the proposed teleoperator maneuvering system (TMS) or other autonomous or robotic space vehicles. Sources of error in the operation of the system which tend to limit its range resolution capabilities are identified. Alternative signal processing techniques are explored with emphasis on determination of the effects of inserting various signal filtering circuits in the system. The identification and elimination of an extraneous low frequency signal component created as a result of zero range immediate reflection of radar energy from the surface of the antenna dish back into the mixer of the system is described.

Mcdonald, M. W.↗
DOE OSTI2024

Error field detection and correction studies towards ITER operation

In magnetic fusion devices, error field (EF) sources, spurious magnetic field perturbations, need to be identified and corrected for safe and stable (disruption-free) tokamak operation. Within Work Package Tokamak Exploitation RT04, a series of studies have been carried out to test the portability of the novel non-disruptive method, designed and tested in DIII-D (Paz-Soldan et al 2022 Nucl. Fusion62 126007), and to perform an assessment of model-based EF control strategies towards their applicability in ITER. In this paper, the lessons learned, the physical mechanism behind the magnetic island healing, which relies on enhanced viscous torque that acts against the static electro-magnetic torque, and the main control achievements are reported, together with the first design of the asynchronous EF correction current/density controller for ITER.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
NASA NTRS2006

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

Shuler, Robert L.↗
DOE OSTI2024

Group-theoretic error mitigation enabled by classical shadows and symmetries

Abstract Estimating expectation values is a key subroutine in quantum algorithms. Near-term implementations face two major challenges: a limited number of samples required to learn a large collection of observables, and the accumulation of errors in devices without quantum error correction. To address these challenges simultaneously, we develop a quantum error-mitigation strategy called symmetry-adjusted classical shadows , by adjusting classical-shadow tomography according to how symmetries are corrupted by device errors. As a concrete example, we highlight global U(1) symmetry, which manifests in fermions as particle number and in spins as total magnetization, and illustrate their group-theoretic unification with respective classical-shadow protocols. We establish rigorous sampling bounds under readout errors obeying minimal assumptions, and perform numerical experiments with a more comprehensive model of gate-level errors derived from existing quantum processors. Our results reveal symmetry-adjusted classical shadows as a low-cost strategy to mitigate errors from noisy quantum experiments in the ubiquitous presence of symmetry.

Zhao, Andrew (ORCID:0000000202990277)↗
DOE OSTI2023

Soft syndrome iterative decoding of quantum LDPC codes and hardware architectures

In practical quantum error correction implementations, the measurement of syndrome information is an unreliable step—typically modeled as a binary measurement outcome flipped with some probability. However, the measured syndrome is in fact a discretized value of the continuous voltage or current values obtained in the physical implementation of the syndrome extraction. In this paper, we use this “soft” or analog information to benefit iterative decoders for decoding quantum low-density parity-check (QLDPC) codes. Syndrome-based iterative belief propagation decoders are modified to utilize the soft syndrome to correct both data and syndrome errors simultaneously. We demonstrate the advantages of the proposed scheme not only in terms of comparison of thresholds and logical error rates for quasi-cyclic lifted-product QLDPC code families but also with faster convergence of iterative decoders. Additionally, we derive hardware (FPGA) architectures of these soft syndrome decoders and obtain similar performance in terms of error correction to the ideal models even with reduced precision in the soft information. The total latency of the hardware architectures is about 600 ns (for the QLDPC codes considered) in a 20 nm CMOS process FPGA device, and the area overhead is almost constant—less than 50% compared to min-sum decoders with noisy syndromes.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2020

Virtualized Logical Qubits: A 2.5D Architecture for Error-Corrected Quantum Computing

Current, near-term quantum devices have shown great progress in the last several years culminating recently with a demonstration of quantum supremacy. In the medium-term, however, quantum machines will need to transition to greater reliability through error correction, likely through promising techniques like surface codes which are well suited for near-term devices with limited qubit connectivity. We discover quantum memory, particularly resonant cavities with transmon qubits arranged in a 2.5D architecture, can efficiently implement surface codes with substantial hardware savings and performance/fidelity gains. Specifically, we virtualize logical qubits by storing them in layers of qubit memories connected to each transmon. Surprisingly, distributing each logical qubit across many memories has a minimal impact on fault tolerance and results in substantially more efficient operations. Our design permits fast transversal application of CNOT operations between logical qubits sharing the same physical address (same set of cavities) which are 6x faster than standard lattice surgery CNOTs. We develop a novel embedding which saves approximately 10x in transmons with another 2x savings from an additional optimization for compactness. Although qubit virtualization pays a 10x penalty in serialization, advantages in the transversal CNOT and in area efficiency result in fault-tolerance and performance comparable to conventional 2D transmon-only architectures. Our simulations show our system can achieve fault tolerance comparable to conventional two-dimensional grids while saving substantial hardware. Furthermore, our architecture can produce magic states at 1.22x the baseline rate given a fixed number of transmon qubits. Here, this is a critical benchmark for future fault-tolerant quantum computers as magic states are essential and machines will spend the majority of their resources continuously producing them. This architecture substantially reduces the hardware requirements for fault-tolerant quantum computing and puts within reach a proof-of-concept experimental demonstration of around 10 logical qubits, requiring only 11 transmons and 9 attached cavities in total.

quantum computing↗
DOE OSTI2021

Hybrid Quantum-Classical Eigensolver without Variation or Parametric Gates

The use of near-term quantum devices that lack quantum error correction, for addressing quantum chemistry and physics problems, requires hybrid quantum-classical algorithms and techniques. Here, we present a process for obtaining the eigenenergy spectrum of electronic quantum systems. This is achieved by projecting the Hamiltonian of a quantum system onto a limited effective Hilbert space specified by a set of computational bases. From this projection, an effective Hamiltonian is obtained. Furthermore, a process for preparing short depth quantum circuits to measure the corresponding diagonal and off-diagonal terms of the effective Hamiltonian is given, whereby quantum entanglement and ancilla qubits are used. The effective Hamiltonian is then diagonalized on a classical computer using numerical algorithms to obtain the eigenvalues. The use case of this approach is demonstrated for ground state and excited states of BeH2 and LiH molecules, and the density of states, which agrees well with exact solutions. Additionally, hardware demonstration is presented using IBM quantum devices for H2 molecule.

Jouzdani, Pejman (ORCID:0000000256470381)↗
DOE OSTI2020

Request for the establishment of quantum information foundries

Quantum information science still requires basic science research to achieve its full potential. However, scientists require access to fabricated device samples if we are to utilize the full toolset for solving the pressing issues in the field such as materials, device layout, or optimal error correction methods.Currently, access to samples is either prohibitively expensive, or requires close collaboration with one of the few groups in the world developing these systems. A dedicated quantum foundry could,in principle,provide affordable samples designed with current best practices to a host of scientists who otherwise do not have access. We detail several different foundry models which we believe will assist the community in developing the science for both the underlying processes, as well as the more advanced chip layout and circuit design. Opening access to the broader community has the potential to significantly lower the barrier to entry and vastly improve the ability for researchers in fields ranging from condensed matter to materials characterization to systems engineering to contribute to accelerating the advance of quantum information science and technology.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS1999

SRAM Based Re-programmable FPGA for Space Applications

An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

Wang, J. J.↗
NASA NTRS1986

A generalized algorithm to design finite field normal basis multipliers

Finite field arithmetic logic is central in the implementation of some error-correcting coders and some cryptographic devices. There is a need for good multiplication algorithms which can be easily realized. Massey and Omura recently developed a new multiplication algorithm for finite fields based on a normal basis representation. Using the normal basis representation, the design of the finite field multiplier is simple and regular. The fundamental design of the Massey-Omura multiplier is based on a design of a product function. In this article, a generalized algorithm to locate a normal basis in a field is first presented. Using this normal basis, an algorithm to construct the product function is then developed. This design does not depend on particular characteristics of the generator polynomial of the field.

Wang, C. C.↗
NASA NTRS1989

Improved Algorithm For Finite-Field Normal-Basis Multipliers

Improved algorithm reduces complexity of calculations that must precede design of Massey-Omura finite-field normal-basis multipliers, used in error-correcting-code equipment and cryptographic devices. Algorithm represents an extension of development reported in "Algorithm To Design Finite-Field Normal-Basis Multipliers" (NPO-17109), NASA Tech Briefs, Vol. 12, No. 5, page 82.

Wang, C. C.↗
DOE OSTI2020

Error field correction strategies in preparation to MAST-U operation

In magnetic fusion devices, unwanted non-axisymmetric magnetic field perturbations, known as error fields (EF), can have detrimental effects on plasma stability and confinement. Such EFs may originate from several sources, such as axi-symmetric coil misalignments, coil feeds, 3D structures in the wall surrounding the plasma, presence of ferromagnetic materials near the plasma surface, blanket materials in future devices. To minimize their impact on plasma performance and on the available operational space, it is important to identify the EF sources and develop EF control strategies. MAST Upgrade (MAST-U) is a spherical tokamak which will operate in the near future after a series of enhancements from the previous MAST experiment. To deliver a machine with EF amplitude low enough to allow a high quality experimental programme, systematic analysis of the intrinsic EF sources has been carried out for poloidal eld (P) and divertor (D) coils. To deliver a machine with EF amplitude low enough to allow a high quality experimental programme, systematic analysis of the intrinsic EF sources has been carried out for poloidal field (P) and divertor (D) coils, whose magnetic eld measurements were available when writing this paper. Such measurements reveal that P and D coils are 3D deformed and thus are responsible for intrinsic EFs, with mainly n=1 and n=2 toroidal mode numbers. In preparation to MAST-U operation, both passive and active EF control strategies have been adopted for n=1 and n=2 EFs compensation. Passive EF control consisted of installing finely each D and P coil within MAST-U device so as to minimize the intrinsic n=1 EF amplitude. The optimal coil alignment has been determined based on magnetic eld measurements and the corresponding 3D electro-magnetic modelling, and envisaged coil shift and tilt of 3.2 mm and 0.7 mrad, respectively, in the case of P coil named P4. Conversely, active control will be use during MAST-U operation to reduce the n=2 EF which is associated mainly with P4 and P5, as well. Since these coils have been re-used from the MAST device, studies attempting n=2 EF control, based on MAST plasmas, have been modelled utilizing the MARS-F code to interpret experimental results in MAST and to give hints for future n=2 EF control studies in MAST-U. Here, a model-based control set for n=2 EF control has been identified which would allow for the minimization of rotation braking, of the resonant magnetic field at the q=2 and of the plasma displacement in MAST-U, simultaneously.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
NASA NTRS1968

Self-correcting, synchronizing ring counter using integrated circuit devices

Three nand gate circuits are used to add error detection and reset logic circuitry for initiating and retaining the correct binary state in the flip-flop circuits of a ring counter. As the input signals are counted, the position of the specified state moves in ordered sequence around circuit loop.

Maasberg, W. A.↗
NASA NTRS1985

Correcting for particle counting bias error in turbulent flow

An ideal seeding device is proposed generating particles that exactly follow the flow out are still a major source of error, i.e., with a particle counting bias wherein the probability of measuring velocity is a function of velocity. The error in the measured mean can be as much as 25%. Many schemes have been put forward to correct for this error, but there is not universal agreement as to the acceptability of any one method. In particular it is sometimes difficult to know if the assumptions required in the analysis are fulfilled by any particular flow measurement system. To check various correction mechanisms in an ideal way and to gain some insight into how to correct with the fewest initial assumptions, a computer simulation is constructed to simulate laser anemometer measurements in a turbulent flow. That simulator and the results of its use are discussed.

Edwards, R. V.↗
DOE OSTI2023

Sample-efficient verification of continuously-parameterized quantum gates for small quantum processors

Most near-term quantum information processing devices will not be capable of implementing quantum error correction and the associated logical quantum gate set. Instead, quantum circuits will be implemented directly using the physical native gate set of the device. These native gates often have a parameterization (e.g., rotation angles) which provide the ability to perform a continuous range of operations. Verification of the correct operation of these gates across the allowable range of parameters is important for gaining confidence in the reliability of these devices. In this work, we demonstrate a procedure for sample-efficient verification of continuously-parameterized quantum gates for small quantum processors of up to approximately 10 qubits. This procedure involves generating random sequences of randomly-parameterized layers of gates chosen from the native gate set of the device, and then stochastically compiling an approximate inverse to this sequence such that executing the full sequence on the device should leave the system near its initial state. We show that fidelity estimates made via this technique have a lower variance than fidelity estimates made via cross-entropy benchmarking. This provides an experimentally-relevant advantage in sample efficiency when estimating the fidelity loss to some desired precision. We describe the experimental realization of this technique using continuously-parameterized quantum gate sets on a trapped-ion quantum processor from Sandia QSCOUT and a superconducting quantum processor from IBM Q, and we demonstrate the sample efficiency advantage of this technique both numerically and experimentally.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗