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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2004

Four-Channel PC/104 MIL-STD-1553 Circuit Board

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Cox, Gary L.↗
NASA NTRS2006

Acceleration of Stereo Correlation in Verilog

To speed up vision processing in low speed, low power devices, embedding FPGA hardware is becoming an effective way to add processing capability. FPGAs offer the ability to flexibly add parallel and/or deeply pipelined computation to embedded processors without adding significantly to the mass and power requirements of an embedded system. This paper will discuss the JPL stereo vision system, and describe how a portion of that system was accelerated by using custom FPGA hardware to process the computationally intensive portions of JPL stereo. The architecture described takes full advantage of the ability of an FPGA to use many small computation elements in parallel. This resulted in a 16 times speedup in real hardware over using a simple linear processor to compute image correlation and disparity.

machine vision↗
DOE OSTI2026

Gaia: segmented germanium detector for high-energy X-ray fluorescence and spectroscopic imaging

We present Gaia, a monolithic array of 96 high-purity germanium pixel detectors integrated with a custom low-noise application-specific integrated circuit (ASIC) and a field-programmable gate array (FPGA)-based data acquisition system. The sensor operates at ∼100 K using a commercial closed-cycle cryocooler, with the in-vacuum electronics thermally isolated from the cold finger to ensure thermal stability. The system demonstrates an average energy resolution of 711 eV at 122 keV, measured using a 57 Co source, and 253 eV at 5.89 keV, measured with 55 Fe across all channels. The readout architecture incorporates a high-performance FPGA paired with a dual-core ARM processor, forming a complete embedded Linux-based computing platform. Communication between the processor and FPGA is handled via memory-mapped I/O, and data are streamed over high-speed gigabit Ethernet. A full-scale 384-pixel Gaia detector, based on this 96-element module, is currently under fabrication.

36 MATERIALS SCIENCE↗
NASA NTRS2005

Reconfigurable Processing Module

To accommodate a wide spectrum of applications and technologies, NASA s Exploration System's Missions Directorate has called for reconfigurable and modular technologies to support future missions to the moon and Mars. In response, Langley Research Center is leading a program entitled Reconfigurable Scaleable Computing (RSC) that is centered on the development of FPGA-based computing resources in a stackable form factor. This paper details the architecture and implementation of the Reconfigurable Processing Module (RPM), which is the key element of the RSC system. The RPM is an FPGA-based, space-qualified printed circuit assembly leveraging terrestrial/commercial design standards into the space applications domain. The form factor is similar to, and backwards compatible with, the PCI-104 standard utilizing only the PCI interface. The size is expanded to accommodate the required functionality while still better than 30% smaller than a 3U CompactPCI(TradeMark)card and without the overhead of the backplane. The architecture is built around two FPGA devices, one hosting PCI and memory interfaces, and another hosting mission application resources; both of which are connected with a high-speed data bus. The PCI interface FPGA provides access via the PCI bus to onboard SDRAM, flash PROM, and the application resources; both configuration management as well as runtime interaction. The reconfigurable FPGA, referred to as the Application FPGA - or simply "the application" - is a radiation-tolerant Xilinx Virtex-4 FX60 hosting custom application specific logic or soft microprocessor IP. The RPM implements various SEE mitigation techniques including TMR, EDAC, and configuration scrubbing of the reconfigurable FPGA. Prototype hardware and formal modeling techniques are used to explore the performability trade space. These models provide a novel way to calculate quality-of-service performance measures while simultaneously considering fault-related behavior due to SEE soft errors.

Somervill, Kevin↗
DOE OSTI2026

Berkeley eXtensible Environment (BXE) v3

The Berkeley eXtensible Environment (BXE) provides a cloud environment for hardware designers and computer architects to design, build, and simulate their custom architectures on an on-premises FPGA cluster. Utilizing the Chipyard, MoSAIC, and FireSim frameworks, users are provided an environment where they can assemble SoC designs from an existing library of components or import their own source code. Once their designs are ready, they can utilize the FireSim framework provided by BXE to deploy and simulate their designs on the FPGA. Users aren't limited to a single FPGA; they can deploy multiple instances across multiple FPGAs, acting like a rack of servers, or partition their large design across multiple FPGAs, ganging multiple FPGAs into a single simulated system.

Fatollahi-Fard, Farzin↗
NASA NTRS2010

Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for the Federal fiscal year of 2010 are: Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments, Modeling of Radiation Effects on Electronics, Radiation Hardened High Performance Processors (HPP), and and Reconfigurable Computing.

Keys, Andrew S.↗
NASA NTRS2004

FPGA-Based, Self-Checking, Fault-Tolerant Computers

A proposed computer architecture would exploit the capabilities of commercially available field-programmable gate arrays (FPGAs) to enable computers to detect and recover from bit errors. The main purpose of the proposed architecture is to enable fault-tolerant computing in the presence of single-event upsets (SEUs). [An SEU is a spurious bit flip (also called a soft error) caused by a single impact of ionizing radiation.] The architecture would also enable recovery from some soft errors caused by electrical transients and, to some extent, from intermittent and permanent (hard) errors caused by aging of electronic components. A typical FPGA of the current generation contains one or more complete processor cores, memories, and highspeed serial input/output (I/O) channels, making it possible to shrink a board-level processor node to a single integrated-circuit chip. Custom, highly efficient microcontrollers, general-purpose computers, custom I/O processors, and signal processors can be rapidly and efficiently implemented by use of FPGAs. Unfortunately, FPGAs are susceptible to SEUs. Prior efforts to mitigate the effects of SEUs have yielded solutions that degrade performance of the system and require support from external hardware and software. In comparison with other fault-tolerant- computing architectures (e.g., triple modular redundancy), the proposed architecture could be implemented with less circuitry and lower power demand. Moreover, the fault-tolerant computing functions would require only minimal support from circuitry outside the central processing units (CPUs) of computers, would not require any software support, and would be largely transparent to software and to other computer hardware. There would be two types of modules: a self-checking processor module and a memory system (see figure). The self-checking processor module would be implemented on a single FPGA and would be capable of detecting its own internal errors. It would contain two CPUs executing identical programs in lock step, with comparison of their outputs to detect errors. It would also contain various cache local memory circuits, communication circuits, and configurable special-purpose processors that would use self-checking checkers. (The basic principle of the self-checking checker method is to utilize logic circuitry that generates error signals whenever there is an error in either the checker or the circuit being checked.) The memory system would comprise a main memory and a hardware-controlled check-pointing system (CPS) based on a buffer memory denoted the recovery cache. The main memory would contain random-access memory (RAM) chips and FPGAs that would, in addition to everything else, implement double-error-detecting and single-error-correcting memory functions to enable recovery from single-bit errors.

Some, Raphael↗
DOE OSTI2024

Neuro-Spark: A Submicrosecond Spiking Neural Networks Architecture for In-Sensor Filtering

Neuro-Spark, which is a new neuromorphic architecture with a field-programmable gate array (FPGA) implementation for ultrafast spiking neural network (SNN) inference at the edge, facilitates smart-pixel in-sensor filtering for high-energy physics experiments at the Large Hadron Collider (LHC). Utilizing the evolutionary optimization for neuromorphic systems (EONS) training method, we generate compact SNN models with 91% signal efficiency, akin to convolutional neural networks but with half the parameters. However, deploying near the detector poses a challenge because the SNN must handle a sustained input data rate exceeding 1013 GB/s. To overcome this, we propose a novel hardware architecture that uses high-level synthesis to construct a tuned architecture for the EONS-trained SNN. In addition to the analysis and validation with an AMD Xilinx Artix-A7 FPGA, our solution consumes only ç24% of FPGA LUT and flipflops. We also introduce an innovative quantization method that reduces FPGA resource utilization by ç15% without compromising accuracy. Our FPGA implementation achieves computing latency of ç10 ns for smart-pixel application inference on an edge FPGA.

Miniskar, Narasinga Rao↗
DOE OSTI2025

Fast jet tagging with MLP-Mixers on FPGAs

We explore the innovative use of MLP-Mixer models for real-time jet tagging and establish their feasibility on resource-constrained hardware like FPGAs. MLP-Mixers excel in processing sequences of jet constituents, achieving state-of-the-art performance on datasets mimicking Large Hadron Collider conditions. By using advanced optimization techniques such as High-Granularity Quantization and Distributed Arithmetic, we achieve unprecedented efficiency. These models match or surpass the accuracy of previous architectures, reduce hardware resource usage by up to 97%, double the throughput, and half the latency. Additionally, non-permutation-invariant architectures enable smart feature prioritization and efficient FPGA deployment, setting a new benchmark for machine learning in real-time data processing at particle colliders.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRSDate not supplied

Performance of A Real-Time Photon Counting Optical Receiver in the Presence of Emulated Channel Fading

Free-space optical communication links with terrestrial ground stations experience fading due to atmospheric scintillation and beam pointing. Fiber-coupled receiver systems experience additional fading at the interface between the fiber and free-space optics of the telescope. The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) has characterized a real-time photon-counting optical ground receiver system with an atmospheric fade emulation system. The receiver system is comprised of a fiber interconnect, an array of superconducting nanowire single photon detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. Two fiber interconnect/detector architectures have been studied. One architecture uses a 70-mode photonic lantern coupled to seven single pixel SNSPDs. The other architecture uses a 10-mode few-mode fiber (FMF) coupled to a 15-pixel SNSPD array. The receiver system complies with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency Coding and Synchronization Standard, which uses serially concatenated convolutionally coded pulse-position modulation (SCPPM). The CCSDS standard is designed for use in low photon flux missions, including the Orion Artemis-II Optical (O2O) communications demonstration. The standard utilizes a convolutional symbol interleaver which can be resized to mitigate different fades. The fade emulation system employed in this work emulates scintillation-induced, pointing-induced, and coupling-induced fading. This paper gives an overview of the real-time optical receiver system and the fade emulation system. It presents tests results which show the impact of fading on the performance on the receiver. The test results show that in the presence of channel fading, the 70-mode photonic lantern outperforms the 10-mode FMF under higher (D/r_0=9) turbulence conditions due to high fiber-coupling-induced fading and fiber coupling loss on the 10-mode FMF. When operating in lower turbulence (D/r_0=4), the 10-mode FMF outperforms the 70-mode photonic lantern. The paper also shows a larger convolutional interleaver improves the system performance as long as the receiver does not lose acquisition.

optical communications↗
NASA NTRSDate not supplied

Performance of a real-time photon counting optical receiver in the presence of emulated channel fading

Free-space optical communication links with terrestrial ground stations experience fading due to atmospheric scintillation and beam pointing. Fiber-coupled receiver systems experience additional fading at the interface between the fiber and free-space optics of the telescope. The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) has characterized a real-time photon-counting optical ground receiver system with an atmospheric fade emulation system. The receiver system is comprised of a fiber interconnect, an array of superconducting nanowire single photon detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. Two fiber interconnect/detector architectures have been studied. One architecture uses a 70-mode photonic lantern coupled to seven single pixel SNSPDs. The other architecture uses a 10-mode few-mode fiber (FMF) coupled to a 15-pixel SNSPD array. The receiver system complies with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency Coding and Synchronization Standard, which uses serially concatenated convolutionally coded pulse-position modulation (SCPPM). The CCSDS standard is designed for use in low photon flux missions, including the Orion Artemis-II Optical (O2O) communications demonstration. The standard utilizes a convolutional symbol interleaver which can be resized to mitigate different fades. The fade emulation system employed in this work emulates scintillation-induced, pointing-induced, and coupling-induced fading. This paper gives an overview of the real-time optical receiver system and the fade emulation system. It presents tests results which show the impact of fading on the performance on the receiver. The test results show that in the presence of channel fading, the 70-mode photonic lantern outperforms the 10-mode FMF under higher (D/r_0=9) turbulence conditions due to high fiber-coupling-induced fading and fiber coupling loss on the 10-mode FMF. When operating in lower turbulence (D/r_0=4), the 10-mode FMF outperforms the 70-mode photonic lantern. The paper also shows a larger convolutional interleaver improves the system performance as long as the receiver does not lose acquisition.

optical communications↗
NASA NTRS2011

Small Microprocessor for ASIC or FPGA Implementation

A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

Kleyner, Igor↗
DOE OSTI2025

Surrogate Modelling of 3rd Integer Resonant Extraction at Fermilab Delivery Ring

We present an ongoing work in which a surrogate model is being developed to reproduce the response dynamics of the third-integer resonant extraction process in the Delivery Ring (DR) at Fermilab. This effort is in pursuit of smoothly extracting circulating beam to the Mu2e Experiment s production target, wherein the goal is to extract a uniform slice of the circulating $1e12$ protons in the DR over 25,000 turns (43~ms). The DR contains 3 harmonic sextupoles which excite a third-integer resonance as well as three fast, tune-ramping quadrupole magnets which drive the horizontal tune towards the $29/3$ resonance. In our initial work the surrogate model trains on a semi-analytical simulation provided in the same format as live data. Using Reinforcement Learning (and other potential ML methods), the trained surrogate acts as the environment in which a simple ML control agent could learn to dynamically adjust the quadrupole ramp at 430 break points within the 43 microsecond spill window. The control agent will be hosted on a dedicated Arria 10 FPGA, introducing its own requirements on control agent architecture. In this work we report the accuracy and fidelity of surrogate models in comparison to the response dynamics of the physics simulator.

Narayanan, Aakaash [Fermilab] (ORCID:0000000157944↗
NASA NTRS2019

Optical Software Defined Radio Transmitter Extinction Ratio Enhancement with Differential Pulse Carving

A unique challenge in the development of a deep space optical software defined radio (SDR) transmitter is the optimization of the extinction ratio (ER). For a Mars to Earth optical link, an ER approaching 40dB may be necessary. However, a high ER can be difficult to achieve at the low PPM orders and narrow slot widths required for high data rates. The quality of the digital signal transmitted by the SDR does not meet the amplitude and timing characteristics needed by an analog optical modulator. The conflicting implementation constraints of these two fundamentally different systems, the digital SDR and analog optical modulator, can make achieving the required ER very difficult. In this paper, the causes of fidelity loss at the interface between the SDR and optical modulator are discussed. The SDR signal quality requirements are derived and explored. It is shown that increasing the SDR signal quality enough to meet these requirements is impractical to implement due to bandwidth limitations of electronic components as well as Field Programmable Gate Array (FPGA) clock speed constraints. A novel optical modulation architecture based on low-voltage differential signaling and dual Mach-Zehnder modulators is presented which reduces the signal quality requirements on the SDR and increases the system ER.

Electro-Optic Modulator↗
NASA NTRS2019

Optical Software Defined Radio Transmitter Extinction Ratio Enhancement with Differential Pulse Carving

A unique challenge in the development of a deep space optical software defined radio (SDR) transmitter is the optimization of the extinction ratio (ER). For a Mars to Earth optical link, an ER approaching 40dB may be necessary. However, a high ER can be difficult to achieve at the low PPM orders and narrow slot widths required for high data rates. The quality of the digital signal transmitted by the SDR does not meet the amplitude and timing characteristics needed by an analog optical modulator. The conflicting implementation constraints of these two fundamentally different systems, the digital SDR and analog optical modulator, can make achieving the required ER very difficult. In this paper, the causes of fidelity loss at the interface between the SDR and optical modulator are discussed. The SDR signal quality requirements are derived and explored. It is shown that increasing the SDR signal quality enough to meet these requirements is impractical to implement due to bandwidth limitations of electronic components as well as Field Programmable Gate Array (FPGA) clock speed constraints. A novel optical modulation architecture based on low-voltage differential signaling and dual Mach-Zehnder modulators is presented which reduces the signal quality requirements on the SDR and increases the system ER.

Electro-Optic Modulator↗
NASA NTRSDate not supplied

Testing of A Photon-Counting Optical Ground Receiver With Emulated Space-to-Ground Link Effects

The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) developed and previously characterized a photon-counting optical ground receiver system. The receiver is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications Coding and Synchronization High Photon Efficiency (HPE) Standard. The standard will be used on the Optical Artemis-2 Orion (O2O) communications demonstration and the Deep Space Optical Communication (DSOC) project aboard the Psyche spacecraft. The receiver system consists of a fiber interconnect, up to sixteen superconducting nanowire single-photon detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. Previously, the receiver system architecture was described and test results without emulated link effects were presented. SNSPD device properties, which impact detection jitter and time delay, can limit the receiver dynamic range, especially when operating with varying flux rates (>10 dB) between detectors. Codeword error-rate curves with and without simulated clock drifts attributed to Doppler shift and space transmitter clock differences are presented. Results with ±66 ppm clock differences show minimal performance impact (<0.2 dB). Test results show that the receiver dynamic range (>28 dB) is limited by changing SNSPD detection delays at high photon flux rates.

optical communications↗
NASA NTRSDate not supplied

Testing of A Photon-Counting Optical Ground Receiver With Emulated Space-to-Ground Link Effects

The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) developed and previously characterized a photon-counting optical ground receiver system. The receiver is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications Coding and Synchronization High Photon Efficiency (HPE) Standard. The standard will be used on the Optical Artemis-2 Orion (O2O) communications demonstration and the Deep Space Optical Communication (DSOC) project aboard the Psyche spacecraft. The receiver system consists of a fiber interconnect, up to sixteen superconducting nanowire single-photon detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. Previously, the receiver system architecture was described and test results without emulated link effects were presented. SNSPD device properties, which impact detection jitter and time delay, can limit the receiver dynamic range, especially when operating with varying flux rates (>10 dB) between detectors. Codeword error-rate curves with and without simulated clock drifts attributed to Doppler shift and space transmitter clock differences are presented. Results with ±66 ppm clock differences show minimal performance impact (<0.2 dB). Test results show that the receiver dynamic range (>28 dB) is limited by changing SNSPD detection delays at high photon flux rates.

optical communications↗