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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 55 records · Page 3
All sourcesNASA NTRSDOE OSTI
NASA NTRS2003

Advanced sensor systems for biotelemetry

The present invention relates to telemetry-based sensing systems that continuously measures physical, chemical and biological parameters. More specifically, these sensing systems comprise a small, modular, low-power implantable biotelemetry system capable of continuously sensing physiological characteristics using implantable transmitters, a receiver, and a data acquisition system to analyze and record the transmitted signal over several months. The preferred embodiment is a preterm labor and fetal monitoring system. Key features of the invention include Pulse Interval Modulation (PIM) that is used to send temperature and pressure information out of the biological environment. The RF carrier frequency is 174-216 MHz and a pair of RF bursts (pulses) is transmitted at a frequency of about 1-2 Hz. The transmission range is 3 to 10 feet, depending on the position of the transmitter in the body and its biological environment. The entire transmitter is encapsulated in biocompatible silicone rubber. Power is supplied by on-board silver-oxide batteries. The average power consumption of the current design is less than 30 .mu.W., which yields a lifetime of approximately 6-9 months. Chip-on-Board technology (COB) drastically reduces the size of the printed circuit board from 38.times.28 mm to 22.times.8 mm. Unpackaged dies are flip-chip bonded directly onto the printed circuit board, along with surface mount resistors and capacitors. The invention can monitor additional physiological parameters including, but not limited to, ECG, blood gases, glucose, and ions such as calcium, potassium, and sodium.

Hines, John W.↗
NASA NTRS2003

Advanced Sensor Systems for Biotelemetry

The present invention relates to telemetry-based sensing systems that continuously measures physical, chemical and biological parameters. More specifically, these sensing systems comprise a small, modular, low-power implantable biotelemetry system capable of continuously sensing physiological characteristics using implantable transmitters, a receiver, and a data acquisition system to analyze and record the transmitted signal over several months. The preferred embodiment is a preterm labor and fetal monitoring system. Key features of the invention include Pulse Interval Modulation (PIM) that is used to send temperature and pressure information out of the biological environment. The RF carrier frequency is 174-216 MHz and a pair of RF bursts (pulses) is transmitted at a frequency of about 1-2 Hz. The transmission range is 3 to 10 feet, depending on the position of the transmitter in the body and its biological environment. The entire transmitter is encapsulated in biocompatible silicone rubber. Power is supplied by on-board silver-oxide batteries. The average power consumption of the current design is less than 30 microW, which yields a lifetime of approximately 6 - 9 months. Chip-on-Board technology (COB) drastically reduces the size of the printed circuit board from 38 x 28 mm to 22 x 8 mm. Unpackaged dies are flip-chip bonded directly onto the printed circuit board, along with surface mount resistors and capacitors. The invention can monitor additional physiological parameters including, but not limited to, ECG, blood gases, glucose, and ions such as calcium, potassium, and sodium.

Hines, John W.↗
NASA NTRS2008

Electronic Switch Arrays for Managing Microbattery Arrays

Integrated circuits have been invented for managing the charging and discharging of such advanced miniature energy-storage devices as planar arrays of microscopic energy-storage elements [typically, microscopic electrochemical cells (microbatteries) or microcapacitors]. The architecture of these circuits enables implementation of the following energy-management options: dynamic configuration of the elements of an array into a series or parallel combination of banks (subarrarys), each array comprising a series of parallel combination of elements; direct addressing of individual banks for charging/or discharging; and, disconnection of defective elements and corresponding reconfiguration of the rest of the array to utilize the remaining functional elements to obtain the desited voltage and current performance. An integrated circuit according to the invention consists partly of a planar array of field-effect transistors that function as switches for routing electric power among the energy-storage elements, the power source, and the load. To connect the energy-storage elements to the power source for charging, a specific subset of switches is closed; to connect the energy-storage elements to the load for discharging, a different specific set of switches is closed. Also included in the integrated circuit is circuitry for monitoring and controlling charging and discharging. The control and monitoring circuitry, the switching transistors, and interconnecting metal lines are laid out on the integrated-circuit chip in a pattern that registers with the array of energy-storage elements. There is a design option to either (1) fabricate the energy-storage elements in the corresponding locations on, and as an integral part of, this integrated circuit; or (2) following a flip-chip approach, fabricate the array of energy-storage elements on a separate integrated-circuit chip and then align and bond the two chips together.

Mojarradi, Mohammad↗
NASA NTRS2004

Fabrication of a novel gigabit/second free-space optical interconnect - photodetector characterization and testing and system development

The time when computing power is limited by the copper wire inherent in the computer system and not the speed of the microprocessor is rapidly approaching. With constant advances in computer technology, many researchers believe that in only a few years, optical interconnects will begin to replace copper wires in your Central Processing Unit (CPU). On a more macroscopic scale, the telecommunications industry has already made the switch to optical data transmission as, to date, fiber optic technology is the only reasonable method of reliable, long range data transmission. Within the span of a decade, we will see optical technologies move from the macroscopic world of the telecommunications industry to the microscopic world of the computer chip. Already, the communications industry is marketing commercially available optical links to connect two personal computers, thereby eliminating the need for standard and comparatively slow wired and wireless Ethernet transfers and greatly increasing the distance the computers can be separated. As processing demands continue to increase, the realm of optical communications will continue to move closer to the microprocessor and quite possibly onto the microprocessor itself. A day may come when copper connections are used only to supply power, not transfer data. This summer s work marks some of the beginning stages of a 5 to 10 year, long-term research project to create and study a free-space, 1 Gigabit/sec optical interconnect. The research will result in a novel fabricated, chip-to-chip interconnect consisting of a Vertical Cavity Surface Emitting Laser (VCSEL) Diode linked through free space to a Metal- Semiconductor-Metal (MSM) Photodetector with the possible integration of microlenses for signal focusing and Micro-Electromechanical Systems (MEMS) devices for optical signal steering. The advantages, disadvantages, and practicality of incorporating flip-chip mounting technologies will also be addressed. My work began with the design and construction of a test setup for the experiment and then appropriate characterization of the test system. Specifically, I am involved in the characterization of a commercially available 1550nm wavelength, 5mW diode laser and a study of its modulation bandwidth. Commercially produced photodetectors as well as the incorporation of microwave technology, in the form of RF input and output, are used in the characterization procedure. The next stage involves the use of a probe station and network analyzer to characterize and test a series of photodetectors fabricated on a 2 inch, Indium Gallium Arsenide (InGaAs) wafer in the Branch s microlithography lab. Other project responsibilities include, but are not limited to the incorporation of a transimpedance amplifier to the photodetector circuit; a study of VCSEL technology; bit error rate analysis of an optical interconnect system; and analysis of free space divergence of the VCSEL, optical path length of the interconnect; and any other pertinent optical properties of the one gigabit per second interconnect for fabrication and testing.

Savich, Gregory R.↗
DOE OSTI2025

Mitigating cosmic-ray-like correlated events with a modular quantum processor

Quantum processors based on superconducting qubits are being scaled to larger qubit numbers, enabling the implementation of small-scale quantum error-correction codes. However, catastrophic chip-scale correlated errors have been observed in these processors, attributed to, e.g., cosmic ray impacts, which challenge conventional error-correction codes such as the surface code. These events are characterized by a temporary but pronounced suppression of the qubit-energy relaxation times. Here, in this study, we explore the potential for modular quantum computing architectures to mitigate such correlated energy decay events. We measure cosmic-ray-like events in a quantum processor comprising a motherboard and two flip-chip bonded daughterboard modules, each module containing two superconducting qubits. We monitor the appearance of correlated qubit decay events within a single module and across the physically separated modules. We find that while decay events within one module are strongly correlated (over 85%), events in separate modules only display approximately 2% correlations. We also report coincident decay events in the motherboard and in either of the two daughterboard modules, providing further insight into the nature of these decay events. These results suggest that modular architectures, combined with bespoke errorcorrection codes, offer a promising approach for protecting future quantum processors from chip-scale correlated errors.

Wu, Xuntao [Univ. of Chicago, IL (United States)] ↗
DOE OSTI2024

Noncontact excitation of multi-GHz lithium niobate electromechanical resonators

Abstract The demand for high-performance electromechanical resonators is ever-growing across diverse applications, ranging from sensing and time-keeping to advanced communication devices. Among the electromechanical materials being explored, thin-film lithium niobate stands out due to its strong piezoelectric properties and low acoustic loss. However, in nearly all existing lithium niobate electromechanical devices, the configuration is such that the electrodes are in direct contact with the mechanical resonator. This configuration introduces an undesirable mass-loading effect, producing spurious modes and additional damping. Here, we present an electromechanical platform that mitigates this challenge by leveraging a flip-chip bonding technique to separate the electrodes from the mechanical resonator. By offloading the electrodes from the resonator, our approach yields a substantial increase in the quality factor of these resonators, paving the way for enhanced performance and reliability for their device applications.

Instruments & Instrumentation↗
DOE OSTI2023

Antenna With Embedded Die in Glass Interposer for 6G Wireless Applications

This article presents the antenna-integrated glass interposer for D-band 6G wireless applications using dieembedding technology. Here, we implement the die-embedded package on glass substrates and characterize the electrical performance in the D-band. The electrical characterization employs embedded test dies with the 50-Ω ground–signal–ground (GSG) ports and coplanar waveguides. We achieve low-loss die-to-package transitions by using staggered dielectric vias, which are compared with the transitions of wire-bonding and flip-chip assembly. This article provides detailed information on the design, modeling, fabrication, and characterization of the die-to-package interconnects. This article also demonstrates the integration of microstrip patch antenna array and embedded dies in the D-band. The results show superior electrical performance provided by the die-embedded glass interposer. The die-to-package interconnect exhibits good matching (less than —10-dB S11) and low loss (0.2-dB loss) in the D-band. The integrated 1 × 8 patch antenna array shows 11.6-dB broadside gain and good matching with the embedded die. In addition, by using a temporary carrier, the antenna-integrated glass interposer also has great potential for further heterogeneous integration and thermal management.

42 ENGINEERING↗
DOE OSTI2020

sMF-BO-2CoGP: A sequential multi-fidelity constrained Bayesian optimization framework for design applications

Bayesian optimization (BO) is an effective surrogate-based method that has been widely used to optimize simulation-based applications. While the traditional Bayesian optimization approach only applies to single-fidelity models, many realistic applications provide multiple levels of fidelity with various levels of computational complexity and predictive capability. In this work, we propose a multi-fidelity Bayesian optimization method for design applications with both known and unknown constraints. The proposed framework, called sMF-BO-2CoGP, is built on a multi-level CoKriging method to predict the objective function. An external binary classifier, which we approximate using a separate CoKriging model, is used to distinguish between feasible and infeasible regions. Finally, the sMF-BO-2CoGP method is demonstrated using a series of analytical examples and a flip-chip application for design optimization to minimize the deformation due to warping under thermal loading conditions.

42 ENGINEERING↗
DOE OSTI2021

srMO-BO-3GP: A sequential regularized multi-objective Bayesian optimization for constrained design applications using an uncertain Pareto classifier

Bayesian optimization (BO) is an efficient and flexible global optimization framework that is applicable to a very wide range of engineering applications. To leverage the capability of the classical BO, many extensions, including multi-objective, multi-fidelity, parallelization, and latent-variable modeling, have been proposed to address the limitations of the classical BO framework. In this work, we propose a novel multi-objective BO formalism, called srMO-BO-3GP, to solve multi-objective optimization problems in a sequential setting. Three different Gaussian processes (GPs) are stacked together, where each of the GPs is assigned with a different task. The first GP is used to approximate a single-objective computed from the multi-objective definition, the second GP is used to learn the unknown constraints, and the third one is used to learn the uncertain Pareto frontier. At each iteration, a multi-objective augmented Tchebycheff function is adopted to convert multi-objective to single-objective, where the regularization with a regularized ridge term is also introduced to smooth the single-objective function. Finally, we couple the third GP along with the classical BO framework to explore the convergence and diversity of the Pareto frontier by the acquisition function for exploitation and exploration. The proposed framework is demonstrated using several numerical benchmark functions, as well as a thermomechanical finite element model for flip-chip package design optimization.

42 ENGINEERING↗
DOE OSTI2021

Leveraging Spin-Orbit Coupling in Ge/SiGe Heterostructures for Quantum Information Transfer

Hole spin qubits confined to lithographically - defined lateral quantum dots in Ge/SiGe heterostructures show great promise. On reason for this is the intrinsic spin - orbit coupling that allows all - electric control of the qubit. That same feature can be exploited as a coupling mechanism to coherently link spin qubits to a photon field in a superconducting resonator, which could, in principle, be used as a quantum bus to distribute quantum information. The work reported here advances the knowledge and technology required for such a demonstration. We discuss the device fabrication and characterization of different quantum dot designs and the demonstration of single hole occupation in multiple devices. Superconductor resonators fabricated using an outside vendor were found to have adequate performance and a path toward flip-chip integration with quantum devices is discussed. The results of an optical study exploring aspects of using implanted Ga as quantum memory in a Ge system are presented.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2021

Impacts of Substrate Thinning on FPGA Performance and Reliability [Slides]

Substrate thinning is necessary in devices with flip-chip BGA packages to enable both radiation testing and component qualification and high-spatial resolution beam-based failure analysis methods. We investigated three factors affecting device performance: subsurface damage from the thinning process, reduced heat spreading in thin substrates, and changes in device switching speed. We conclude subsurface damage to crystalline Si caused by the thinning process is removable with sufficient SiO 2 slurry polishing. Local temperature differences increase minimally in devices thinned to 3 μm. Compressive stress in the Si increases globally after device thinning and leads to slowing of ring oscillator frequency by about 0.5% compared to full-thickness devices. Future work will include extending the results to submicron Si thickness values, which also has important benefits for failure analysis, debug, and security assessments. We also plan to extend this type of work to other FPGAs and other devices like memory and processors.

36 MATERIALS SCIENCE↗
DOE OSTI2025

Characterization of Fine-Pitch Interconnects for Long-Lifetime HI Applications

This conference talk discusses optimizing gold-gold and gold-ENIG fine-pitch interconnections for Heterogeneous Integration applications, with a focus on longevity. We first look at electrical data from gold-gold bumps subjected to highly accelerated lifetime testing. Then, we discuss using chemical and physical data as a predictor for ENIG bump flip-chip success.

Humphrey, Nicholas James [Sandia National Laborato↗
NASA NTRS1995

Advancing MEMS Technology Usage through the MUMPS (Multi-User MEMS Processes) Program

In order to help provide access to advanced micro-electro-mechanical systems (MEMS) technologies and lower the barriers for both industry and academia, the Microelectronic Center of North Carolina (MCNC) and ARPA have developed a program which provides users with access to both MEMS processes and advanced electronic integration techniques. The four distinct aspects of this program, the multi-user MEMS processes (MUMP's), the consolidated micro-mechanical element library, smart MEMS, and the MEMS technology network are described in this paper. MUMP's is an ARPA-supported program created to provide inexpensive access to MEMS technology in a multi-user environment. It is both a proof-of-concept and educational tool that aids in the development of MEMS in the domestic community. MUMP's technologies currently include a 3-layer poly-silicon surface micromachining process and LIGA (lithography, electroforming, and injection molding) processes that provide reasonable design flexibility within set guidelines. The consolidated micromechanical element library (CaMEL) is a library of active and passive MEMS structures that can be downloaded by the MEMS community via the internet. Smart MEMS is the development of advanced electronics integration techniques for MEMS through the application of flip chip technology. The MEMS technology network (TechNet) is a menu of standard substrates and MEMS fabrication processes that can be purchased and combined to create unique process flows. TechNet provides the MEMS community greater flexibility and enhanced technology accessibility.

Koester, D. A.↗
NASA NTRS1995

A Micromechanical INS/GPS System for Small Satellites

The cost and complexity of large satellite space missions continue to escalate. To reduce costs, more attention is being directed toward small lightweight satellites where future demand is expected to grow dramatically. Specifically, micromechanical inertial systems and microstrip global positioning system (GPS) antennas incorporating flip-chip bonding, application specific integrated circuits (ASIC) and MCM technologies will be required. Traditional microsatellite pointing systems do not employ active control. Many systems allow the satellite to point coarsely using gravity gradient, then attempt to maintain the image on the focal plane with fast-steering mirrors. Draper's approach is to actively control the line of sight pointing by utilizing on-board attitude determination with micromechanical inertial sensors and reaction wheel control actuators. Draper has developed commercial and tactical-grade micromechanical inertial sensors, The small size, low weight, and low cost of these gyroscopes and accelerometers enable systems previously impractical because of size and cost. Evolving micromechanical inertial sensors can be applied to closed-loop, active control of small satellites for micro-radian precision-pointing missions. An inertial reference feedback control loop can be used to determine attitude and line of sight jitter to provide error information to the controller for correction. At low frequencies, the error signal is provided by GPS. At higher frequencies, feedback is provided by the micromechanical gyros. This blending of sensors provides wide-band sensing from dc to operational frequencies. First order simulation has shown that the performance of existing micromechanical gyros, with integrated GPS, is feasible for a pointing mission of 10 micro-radians of jitter stability and approximately 1 milli-radian absolute error, for a satellite with 1 meter antenna separation. Improved performance micromechanical sensors currently under development will be suitable for a range of micro-nano-satellite applications.

Barbour, N.↗
NASA NTRS2000

Correlation Between Material Properties of Ferroelectric Thin Films and Design Parameters for Microwave Device Applications: Modeling Examples and Experimental Verification

The application of thin ferroelectric films for frequency and phase agile components is the topic of interest of many research groups worldwide. Consequently, proof-of-concepts (POC) of different tunable microwave components using either (HTS, metal)/ferroelectric thin film/dielectric heterostructures or (thick, thin) film "flip-chip" technology have been reported. Either as ferroelectric thin film characterization tools or from the point of view of circuit implementation approach, both configurations have their respective advantages and limitations. However, we believe that because of the progress made so far using the heterostructure (i.e., multilayer) approach, and due to its intrinsic features such as planar configuration and monolithic integration, a study on the correlation of circuit geometry aspects and ferroelectric material properties could accelerate the insertion of this technology into working systems. In this paper, we will discuss our study performed on circuits based on microstrip lines at frequencies above 10 GHz, where the multilayer configuration offers greater ease of insertion due to circuit's size reduction. Modeled results of relevant circuit parameters such as the characteristic impedance, effective dielectric constant, and attenuation as a function of ferroelectric film's dielectric constant, tans, and thickness, will be presented for SrTiO3 and Ba(x)Sr(1-x)TiO3 ferroelectric films. A comparison between the modeled and experimental data for some of these parameters will be presented.

Miranda, Felix A.↗
NASA NTRS2001

System Miniaturization Via Heterogeneous Integration of Electronic Devices for Deep Space Missions

The scientific devices designed for each of the Outer Planets Program Focuses will likely be groundbreaking not only with respect to their scientific role but also regarding the electronics required to perform such investigations. In the past, the performance of packaged electronics was limited by the components themselves, with minimal influence of the packaging technology. The rapid development of integrated circuit technology, however, has drastically increased the importance of packaging technology in the ultimate performance of devices. If not carefully considered in the overall design, the packaging may become the limiting factor in the operation of the system. Although industry is responsible for several significant accomplishments in the field of electronics packaging, deep space/outer planet missions must take into account additional requirements such as extremely low temperatures, high radiation levels, hermetic sealing, and severe size and weight limitations. Therefore, the present investigation has been designed to meet the needs of NASA's sensor intensive outer planets program by combining (using flip chip technology) an array of devices (including analog, digital, power volt-age, passives, and MEMS) into a miniaturized heterogeneous system and utilizing optical buses to enable autonomy. Additional information is contained in the original extended abstract.

DelCastillo, L.↗
NASA NTRS2005

Nano-engineered Multiwall Carbon Nanotube-copper Composite Thermal Interface Material for Efficient Heat Conduction

Efforts in integrated circuit (IC) packaging technologies have recently been focused on management of increasing heat density associated with high frequency and high density circuit designs. While current flip-chip package designs can accommodate relatively high amounts of heat density, new materials need to be developed to manage thermal effects of next-generation integrated circuits. Multiwall carbon nanotubes (MWNT) have been shown to significantly enhance thermal conduction in the axial direction and thus can be considered to be a candidate for future thermal interface materials by facilitating efficient thermal transport. This work focuses on fabrication and characterization of a robust MWNT-copper composite material as an element in IC package designs. We show that using vertically aligned MWNT arrays reduces interfacial thermal resistance by increasing conduction surface area, and furthermore, the embedded copper acts as a lateral heat spreader to efficiently disperse heat, a necessary function for packaging materials. In addition, we demonstrate reusability of the material, and the absence of residue on the contacting material, both novel features of the MWNT-copper composite that are not found in most state-of-the-art thermal interface materials. Electrochemical methods such as metal deposition and etch are discussed for the creation of the MWNT-Cu composite, detailing issues and observations with using such methods. We show that precise engineering of the composite surface affects the ability of this material to act as an efficient thermal interface material. A thermal contact resistance measurement has been designed to obtain a value of thermal contact resistance for a variety of different thermal contact materials.

Ngo, Quoc↗
NASA NTRS1999

K-Band Phased Array Developed for Low- Earth-Orbit Satellite Communications

Future rapid deployment of low- and medium-Earth-orbit satellite constellations that will offer various narrow- to wide-band wireless communications services will require phased-array antennas that feature wide-angle and superagile electronic steering of one or more antenna beams. Antennas, which employ monolithic microwave integrated circuits (MMIC), are perfectly suited for this application. Under a cooperative agreement, an MMIC-based, K-band phased-array antenna is being developed with 50/50 cost sharing by the NASA Lewis Research Center and Raytheon Systems Company. The transmitting array, which will operate at 19 gigahertz (GHz), is a state-of-the-art design that features dual, independent, electronically steerable beam operation ( 42 ), a stand-alone thermal management, and a high-density tile architecture. This array can transmit 622 megabits per second (Mbps) in each beam from Earth orbit to small Earth terminals. The weight of the total array package is expected to be less than 8 lb. The tile integration technology (flip chip MMIC tile) chosen for this project represents a major advancement in phased-array engineering and holds much promise for reducing manufacturing costs.

Anzic, Godfrey↗